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Module 3a

This document covers gate-level modeling in Verilog, focusing on logic gate primitives, their instantiation, and the construction of Verilog descriptions from logic diagrams. It explains the types of gates available, including and/or and buf/not gates, as well as the concept of gate delays, including rise, fall, and turn-off delays. Additionally, it discusses min, typ, and max delay values to provide control over the timing characteristics of the gates in circuit design.

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132 views36 pages

Module 3a

This document covers gate-level modeling in Verilog, focusing on logic gate primitives, their instantiation, and the construction of Verilog descriptions from logic diagrams. It explains the types of gates available, including and/or and buf/not gates, as well as the concept of gate delays, including rise, fall, and turn-off delays. Additionally, it discusses min, typ, and max delay values to provide control over the timing characteristics of the gates in circuit design.

Uploaded by

karthik1947raj
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DSDV – BEC654A

Module 3
Gate-Level Modeling
Dataflow Modeling
Contents
Learning Objectives
• Identify logic gate primitives provided in Verilog.
• Understand instantiation of gates, gate symbols, and truth tables for
and/or and buf/not type gates.
• Understand how to construct a Verilog description from the logic
diagram of the circuit.
• Describe rise, fall, and turn-off delays in the gate-level design.
• Explain min, max, and typ delays in the gate-level design.
Gate Types
• A logic circuit can be designed by use of logic gates.
• Verilog supports basic logic gates as predefined primitives.
• These primitives are instantiated like modules except that they are
predefined in Verilog and do not need a module definition.
• All logic circuits can be designed by using basic gates.
• There are two classes of basic gates: and/or gates and buf/not gates.
And/Or Gates
• And/or gates have one scalar output and multiple scalar inputs.
• The first terminal in the list of gate terminals is an output and the
other terminals are inputs.
• The output of a gate is evaluated as soon as one of the inputs
changes.
• The and/or gates available in Verilog are: and, or, xor, nand, nor, xnor.
• The corresponding logic symbols for these gates are shown in Figure
3-1. Consider the gates with two inputs.
• The output terminal is denoted by out. Input terminals are denoted
by i1 and i2.
Buf/Not Gates
• Buf/not gates have one scalar input and one or more scalar outputs.
• The last terminal in the port list is connected to the input.
• Other terminals are connected to the outputs.
• Two basic buf/not gate primitives are provided in Verilog. buf not
Array of Instances
• There are many situations when repetitive instances are required.
• These instances differ from each other only by the index of the vector
to which they are connected.
• To simplify specification of such instances, Verilog HDL allows an array
of primitive instances to be defined.
Gate-level multiplexer
4-bit Ripple Carry Full Adder
Gate Delays
• Until now, circuits are described without any delays (i.e., zero delay).
In real circuits, logic gates have delays associated with them.
• Gate delays allow the Verilog user to specify delays through the logic
circuits.
• Pin-to-pin delays can also be specified in Verilog.
• There are three types of delays from the inputs to the output of a
primitive gate : Rise, Fall, and Turn-off Delays
Rise, Fall, and Turn-off Delays
• There are three types of delays from the inputs to the output of a
primitive gate:
• Rise delay
• Fall delay
• Turn-off delay
Turn off Delay
• The turn-off delay is associated with a gate output transition to the
high impedance value (z) from another value.
• If the value changes to x, the minimum of the three delays is
considered.
• Three types of delay specifications are allowed.
• If only one delay is specified, this value is used for all transitions.
• If two delays are specified, they refer to the rise and fall delay values.
The turn-off delay is the minimum of the two delays.
• If all three delays are specified, they refer to rise, fall, and turn-off
delay values.
• If no delays are specified, the default value is zero.
Min/Typ/Max Values
• Verilog provides an additional level of control for each type of delay
mentioned above.
• For each type of delay?rise, fall, and turn-off?three values, min, typ,
and max, can be specified.
• Any one value can be chosen at the start of the simulation.
• Min/typ/max values are used to model devices whose delays vary
within a minimum and maximum range because of the IC fabrication
process variations.
• Min value: The min value is the minimum delay value that the
designer expects the gate to have.
• Typ val: The typ value is the typical delay value that the designer
expects the gate to have.
• Max value: The max value is the maximum delay value that the
designer expects the gate to have.
• Min, typ, or max values can be chosen at Verilog run time.
• Method of choosing a min/typ/max value may vary for different
simulators or operating systems. (For Verilog XL , the values are
chosen by specifying options +maxdelays, +typdelays, and +mindelays
at run time. If no option is specified, the typical delay value is the
default).
• This allows the designers the flexibility of building three delay values
for each transition into their design. The designer can experiment
with delay values without modifying the design.
Delay Example

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