Digital System Design using Verilog

M RS . M A L I N I V L
A S S ISTANT P ROF ESSOR
DE PT OF ECE
BEC654A – DSDV SYLLABUS
Course Outcomes
At the end of the course the student will be able to:
1. Understand the Verilog HDL design flow.
2. Describe the basic concepts of Verilog HDL programming.
3. Write Verilog programs in Gate, Dataflow, Behavioral, and structural modeling
levels of Abstraction.
4. Write the programs more effectively using Verilog Tasks and Functions.
5. Perform Timing and Delay Simulation.
Suggested Learning Resources:
Text Books:
1. “Verilog HDL: A Guide to Digital Design and Synthesis”, Samir Palnitkar, Pearson education,
Second edition.
2. “HDL programming (VHDL and Verilog)”, Nazeih M Botros, John Wiley India Pvt. Ltd.,
2008.
Reference Books:
1. Donald E. Thomas, Philip R. Moorby, “The Verilog Hardware Description Language”,
Springer Science+Business Media, LLC, Fifth edition.
2. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL” Pearson (Prentice Hall),
Second edition.
3. Padmanabhan, Tripura Sundari, “Design through Verilog HDL”, Wiley, 2016 or earlier
 MODULE 1
OVERVIEW OF DIGITAL DESIGN WITH VERILOG
HIERARCHICAL MODELING CONCEPTS
Overview of Digital Design with Verilog HDL:

Evolution of Computer-Aided Digital Design (CAD)

Emergence of HDLs
Typical Design flow
 Importance of HDLs
Popularity of Verilog HDL
Trends in HDLs
 Evolution of Computer Aided Digital Design

Digital Circuits were designed with

 Vacuum tubes
 Transistors
 Integrated Circuits (ICs): Integrated circuits were then invented where logic gates were placed
on a single chip
 SSI (Small Scale Integration) chips - gate count is very small
 MSI (Medium Scale Integration) chips - hundreds of gates
 LSI (Large Scale Integration) chips - thousands of gates
 VLSI (Very Large Scale Integration) technology - more than 100,000 transistors
 ULSI (Ultra Large Scale Integration), a technology - millions or billions of transistors
 Electronic Design Automation (EDA) techniques began to evolve. Chip designers began to use
circuit and logic simulation techniques to verify the functionality of building blocks of the
order of about 100 transistors.
 Emergence of HDLs

Hardware Description Language (HDL)

 A hardware description language is the language that describes the hardware of digital systems in textual form
and resembles a programming language, but specifically oriented to describing hardware structures and
behavior.
 Allowed designed to model the concurrency of processes found in hardware elements
Verilog HDL originated in 1983
 VHDL was developed under contract from DARPA(Defense Advanced Research Projects Agency0
 Could be used to describe digital circuits at a register transfer level (RTL)
 Specify how the data flows between registers and how the design processes the data
 Logic synthesis tools can be used to produce gate-level netlist from the RTL description automatically
HDLs also began to be used for system-level design. HDLs were used for simulation of system boards,
interconnect buses, FPGAs (Field Programmable Gate Arrays), and PALs (Programmable Array Logic). A
common approach is to design each IC chip, using an HDL, and then verify system functionality via
simulation.
Different Levels of Abstraction
Architecture / Algorithm Level
Describe the functionality (behavior) of a circuit

 Register Transfer Logic (RTL) Level

Describe the data flow of a circuit
Gate Level
Describe the connectivity (structure) of a circuit

Switch Level
Typical Design Flow
Importance of HDLs
Popularity of Verilog HDL
History of the Verilog HDL
1984: Gateway Design Automation introduced the Verilog-XL digital logic simulator
 The Verilog language was part of the Verilog-XL simulator
 The language was mostly created by 1 person, Phil Moorby
 The language was intended to be used with only 1 product

 1989: Gateway merged into Cadence Design Systems

1990: Cadence made the Verilog HDL public domain
 Open Verilog International (OVI) controlled the language

1995: The IEEE standardized the Verilog HDL (IEEE 1364)

 2001: The IEEE enhanced the Verilog HDL for modeling scalable designs, deep submicron
accuracy, etc.
Popularity of Verilog HDL
Useful Features of the Verilog HDL
A general-purpose HDL
Easy to learn and use
Syntax is similar to C (VHDL is similar to PASCAL)
 Allows different levels of abstraction to be mixed in the same model
 In terms of switches, gates, RTL, or behavioral code
 Need to learn only for stimulus and hierarchical design
 Most popular logic synthesis tools support Verilog
Rich of Verilog HDL libraries
Provided by fabrication vendors for postlogic synthesis simulation
 Allows the widest choice of vendors while designing a chip
 With powerful PLI (Programming Language Interface)
Write custom C code to interact with internal data structure
Trends in HDLs
Higher levels of abstraction
 Think only in terms of functionality for designers
CAD tools take care of the implementation details
 Behavioral modeling
Design directly in terms of algorithms and the behavior of the circuit
 Formal verification
Supports for Mixed-level design
 Ex: very high speed and timing-critical circuits like μPs
 Mix gate-level description directly into the RTL description
System-level design in a mixed bottom-up methodology
Use either existing Verilog modules, basic building blocks, or IPs
Ex: SystemC for SoC designs
Hierarchical Modeling Concepts
Design Methodologies
Top-down and Bottom-up design methodology
Modules
Instances
Components of a Simulation
Design Block
Stimulus Block (Test Bench) with example
Learning Objectives
• Understand top-down and bottom-up design methodologies for digital design.
• Explain differences between modules and module instances in Verilog.
• Describe four levels of abstraction?behavioral, data flow, gate level, and switch level?to
represent the same module.
• Describe components required for the simulation of a digital design. Define a stimulus block
and a design block. Explain two methods of applying stimulus
Design Methodologies
There are two basic types of digital design methodologies:
 a top-down design methodology and
a bottom-up design methodology
Top down Design Methodology
In a top-down design methodology, we define the top-level block and identify the sub-blocks
necessary to build the top-level block.
We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot
further be divided
Bottom-up Design Methodology
In a bottom-up design methodology, we first identify the building blocks that are available to
us.
We build bigger cells, using these building blocks.
These cells are then used for higher-level blocks until we build the top-level block in the design
4-bit Ripple Carry Counter
A n-bit ripple counter can count up to 2 n states.
It is also known as MOD n counter.
It is known as ripple counter because of the way the clock pulse ripples its way through the flip-
flops.
Some of the features of ripple counter are:
It is an asynchronous counter. Different flip-flops are used with a different clock pulse.
All the flip-flops are used in toggle mode.
Only one flip-flop is applied with an external clock pulse and another flip-flop clock is obtained
from the output of the previous flip-flop.
The flip-flop applied with external clock pulse act as LSB (Least Significant Bit) in the counting
sequence.
Different Levels of Abstraction
Behavioral or algorithmic level
• This is the highest level of abstraction provided by Verilog HDL. A module can be
implemented in terms of the desired design algorithm without concern for the hardware
implementation details. Designing at this level is very similar to C programming
 Dataflow level
• At this level, the module is designed by specifying the data flow. The designer is aware of how
data flows between hardware registers and how the data is processed in the design.
 Gate level
• The module is implemented in terms of logic gates and interconnections between these gates.
Design at this level is similar to describing a design in terms of a gate-level logic diagram
 Gate level
• The module is implemented in terms of logic gates and interconnections between these gates.
Design at this level is similar to describing a design in terms of a gate-level logic diagram
Instances
A module provides a template from which you can create actual objects.
When a module is invoked, Verilog creates a unique object from the template.
Each object has its own name, variables, parameters, and I/O interface.
The process of creating objects from a module template is called instantiation, and the objects
are called instances
 In Example Ripple carry counter, the top-level block creates four instances from the T-flipflop
(T_FF) template. Each T_FF instantiates a D_FF and an inverter gate.
Each instance must be given a unique name.
Note that // is used to denote single-line comments.
Components of a Simulation
Once a design block is completed, it must be tested.
The functionality of the design block can be tested by applying stimulus and checking results.
We call such a block the stimulus block.
It is good practice to keep the stimulus and design blocks separate.
The stimulus block can be written in Verilog.
A separate language is not required to describe stimulus.
The stimulus block is also commonly called a test bench.
 Different test benches can be used to thoroughly test the design block.
First style, the stimulus block instantiates the design
block and directly drives the signals in the design
block
The second style of applying stimulus is to instantiate
both the stimulus and design blocks in a top-level
dummy module
Example:- 4 bit Ripple Counter
•To illustrate the concepts discussed in the previous sections, let us build the complete simulation
of a ripple carry counter. We will define the design block and the stimulus block.
•We will apply stimulus to the design block and monitor the outputs.
•As we develop the Verilog models, you do not need to understand the exact syntax of each
construct at this stage.
•At this point, you should simply try to understand the design process. We discuss the syntax in
much greater detail in the later modules.
Stimulus Block