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VLSI Testing PG

The document outlines the VLSI Testing & Verification course (MECV202), detailing its objectives, modules, assessment methods, and learning resources. The course covers topics such as fault modeling, test generation techniques, built-in self-test (BIST), and design verification concepts. It aims to equip students with skills in digital circuit testing and verification, culminating in a comprehensive understanding of VLSI design and embedded systems.

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Bhavya Gowda
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34 views3 pages

VLSI Testing PG

The document outlines the VLSI Testing & Verification course (MECV202), detailing its objectives, modules, assessment methods, and learning resources. The course covers topics such as fault modeling, test generation techniques, built-in self-test (BIST), and design verification concepts. It aims to equip students with skills in digital circuit testing and verification, culminating in a comprehensive understanding of VLSI design and embedded systems.

Uploaded by

Bhavya Gowda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VLSI Testing &Verification

Course Code MECV202 CIE Marks 50


Teaching Hours/ Week (L:P:SDA) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Hours of Teaching Total Marks 100
Credits 03 Exam Hours 03
Course Learning objectives:
 To study Faults in digital circuits.
 To learn various algorithms for test generation of Combinational Logic Circuits.
 To study the approach to deal with the testing problems at the chip level (BIST).
 To know about Design Verification Concepts, Simulator Architectures and Operations.
Module-1
Faults in digital circuits: Failures and Faults, Modeling of faults, Temporary Faults.
Test generation for Combinational Logic circuits: Fault Diagnosis of digital circuits, Test generation techniques for
combinational circuits (One-Dimensional Path Sensitization, Boolean Difference, D-Algorithm). RBT Levels: L2, L3
Module-2
Test generation for Combinational Logic circuits: Test generation techniques for combinational circuits (PODEM, FAN,
Delay Fault Detection), Detection of multiple faults in Combinational logic circuits.
Design of testable sequential circuits: Controllability and Observability, Ad-Hoc design rules for improving testability,
design of diagnosable sequential circuits, the scan-path technique for testable sequential circuit design.
RBT Levels: L2, L3
Module-3
Built-In Self-Test: Test pattern generation for BIST, Output response analysis, Circular BIST, BIST Architectures.
RBT Levels: L2, L3
Module-4
An Invitation to Design Verification: What is design verification? The basic verification principle, Verification
methodology, Simulation-based verification versus formal verification, Limitations of formal verification, A quick overview
of Verilog scheduling and execution semantics.
Coding for Verification: Functional correctness, Timing correctness. RBT Levels: L2, L3
Module-5
Simulator Architectures and Operations: The compilers, The simulators, Simulator taxonomy and comparison, Simulator
operations and applications. RBT Levels: L2, L3

Assessment Details(both CIE and SEE)


The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The minimum
passing mark for the CIE is 50% of the maximum marks. Minimum passing marks in SEE is 40% of the maximum marks
of SEE.A student shall be deemed to have satisfied the academic requirements and earned the credits allotted to each
subject/ course if the student secures not less than 50% (50 marks out of 100) in the sum total of the CIE (Continuous
Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:


1. Two Unit Tests each of 25 Marks
2. Two assignments each of 25 Marks or one Skill Development Activity of 50marks to attain the COs and POs

The sum of two tests, two assignments/skill Development Activities, will be scaled down to 50 marks CIE methods /
question paper is designed to attain the different levels of Bloom’s taxonomy as per the outcome defined for the
course.

Semester-End Examination:
1. The SEE question paper will be set for 100 marks and the marks scored will be proportionately reduced to 50.
2. The question paper will have ten full questions carrying equal marks.
3. Each full question is for 20 marks. There will be two full questions (with a maximum off our sub- questions) from
each module.
4. Each full question will have a sub-question covering all the topics under a module.
5. The students will have to answer five full questions, selecting one full question from each module
Suggested Learning Resources:
Books
1) Lala Parag K, “Digital Circuit Testing and Testability”, New York, Academic Press 1997.
2) Abramo vici M,Breuer M A, “Digital Systems Testing and Testable Design and Friedman AD”, Wiley 1994.
3) WilliamK.Lam, “Hardware Design Verification: Simulation and Formal Method - Based Approaches”, Prentice Hall
PTR, 2005.
4) Vishwani D Agarwal,“Essential of Electronic Testing for Digital, Memory and Mixed Signal Circuits”, Springer 2002
Web links and Video Lectures(e-Resources):
 https://www.youtube.com/watch?v=O5lyBoWR-PA&list=PLx98Qgh5zPjh6oWI73QfQHZAmAiyt8Wkf
 https://www.youtube.com/watch?v=Abld-fSxjNM&list=PLbMVogVj5nJTClnafWQ9FK2nt3cGG8kCF
 https://www.youtube.com/watch?v=MEaMm423t0w&list=PLZjlBaHNchvOFBWBAtAP9exwQgYpKqsO4&i ndex=1
Skill Development Activities Suggested:
1) Interact with industry (small, medium and large).
2) Involve in research / testing / projects to understand their problems and help creative and innovative methods to
solve the problem.
3) Involve incase studies and field visits /fieldwork.
4) Accustom to the use of standards/codes etc., to narrow the gap between academia and industry.
5) Handle advanced instruments to enhance technical talent.
6) Gain confidence in modeling of systems and algorithms for transient and steady-state operations, thermal study,
etc.
7) Work on different software/s (tools) to simulate, analyze and authenticate the output to inter pretend conclude.

All activities should enhance student’s abilities to employment and/or self-employment opportunities, management
skills, Statistical analysis, fiscal expertise, etc.
Students and the course instructor/s to involve either individually or in groups to interact together to enhance the
learning and application skills of the study they have undertaken. The students with the help of the course teacher can
take up relevant technical–activities which will enhance their skill. The prepared report shall be evaluated for CIE marks.

Course outcome (Course Skill Set)


At the end of the course the student will be able to:
Sl. Blooms
Description
No. Level
CO1 Analyze the need for fault modeling and testing of digital circuits L3
CO2 Generate fault lists for digital circuits and compress the tests for efficiency L2, L3
CO3 Apply boundary scan technique to validate the performance of digital circuits L3, L4
CO4 Design built-in self tests for complex digital circuits L3
CO5 Apply the Verification Concepts to Digital Circuits. L3
Program Outcome of this course
Sl.
Description POs
No.
1 Independently carry out research / investigation and development work to solve practical problems PO1
related to VLSI Design and embedded systems.
2 Demonstrate a degree of mastery over the areas of VLSI Design and embedded systems. The mastery PO2
should be at a Level higher than the requirements in the bachelor's in Electronics & Communication
Engineering.
3 Apply appropriate methodologies and modern engineering/IT tools to meet international standards PO3
in the areas of VLSI Design and Embedded Systems
4 Acquire competency in areas of VLSI and Embedded Systems, IC Fabrication, Design, Testing, PO4
Verification and Integrate multiple sub-systems to develop System On Chip to optimize its
performance and excel in industry sectors related to VLSI/ Embedded domain.
5 Understand the impact of professional engineering solutions in societal and environmental contexts, PO5
and demonstrate the knowledge required for sustainable development

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