Microprocessor - Answer Key

Q1.
a. Discuss the Flag register of 80386DX
A flag is a flip-flop that controls certain EU activities or signals a situation carried on by the
execution of an instruction. Thirteen flags are present in the EFLAG register. EFLAGS, a 32-bit
register, operates as the flags register. FLAGS is the name given to the low-order 16 bits of
EFLAGS and can be treated as a unit. This feature is useful for running 8086 and 80286 programs
because this component of EFLAGS is similar to the FLAGS register of the 8086 and the 80286.
These flags can be categorized into three different groups.
1. Status flags: These flags reflect the state of a particular program.
2. Control flags: These flags directly affect the operation of a few instructions.
3. System flags: These flags reflect the current status of the machine and are usually used by the
operating systems than by application programs.

b. Differentiate between real Mode, Virtual Mode and Protected Mode of 80386 Processor
Real Mode: In real mode, the 80386 processor operates similar to its 16-bit predecessors. It can
directly access 1 MB of memory and executes in a single task. It lacks memory protection and
multitasking capabilities.
Virtual Mode: Virtual mode allows the 80386 processor to run multiple 8086 or 80286 programs
concurrently. It provides a virtual 8086 mode, enabling the execution of multiple real-mode
applications simultaneously. This mode is used for running legacy 16-bit applications in a
multitasking environment.
Protected Mode: Protected mode offers advanced features such as memory protection,
multitasking, and extended memory access. It allows the processor to address up to 4 GB of
physical memory and provides support for virtual memory, privilege levels, and multitasking.
Operating systems like Windows and Linux utilize protected mode for enhanced system stability
and security.

c. Draw and Explain floating point pipeline for Pentium processor

The floating-point pipeline of the Pentium processor is responsible for executing floating-point
arithmetic operations. It consists of several stages that handle different aspects of floating-point
computation.
1. Instruction Decode: In this stage, the processor decodes the incoming floating-point instruction
and prepares it for execution.
2. Operand Fetch: The operands required for the floating-point operation are fetched from the
register file or memory.
3. Execution: The actual floating-point operation, such as addition, subtraction, multiplication, or
division, is performed in this stage.
4. Result Write-back: The result of the floating-point operation is written back to the destination
register or memory location.
5. Exception Handling: This stage handles exceptional conditions, such as overflow, underflow, or
invalid operation, and triggers the appropriate response.

d. Discuss data cache organization of Pentium processor

• Both caches are organized as 2-way set associative caches with 128 sets (total 256 entries)
• There are 32 bytes in a line (8K/256)
• An LRU algorithm is used to select victims in each cache.
• Each entry in a set has its own tag.
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 • Tags in the data cache are triple ported, used for
• U pipeline
• V pipeline
• Bus snooping
• Bus Snooping: It is used to maintain consistent data in a multiprocessor system
where each processor has a separate cache
• Each entry in data cache can be configured for writethrough or write-back

e. What are the Features of Pentium-4 Net Burst Architecture?

Pentium 4 was developed base on NetBurst micro-architecture.
It consists of 42 million transistors.
Clock speed of Pentium 4 varies from 1.3 GHz to 3.8 GHz.
It operates in hyper-pipelined technology and it has a 20-stage pipeline.
Pentium 4 has on-die 256 Kb non-blocking, 8-way set associative L2 cache. The L2 cache uses a
256-bit interface that transports data-transfer rates of 48 GB/s at 1.5 GHz.
The instruction set of the Pentium 4 processor is compatible with x86 (i386), x 86-64, MMX,
SSE, SSE2, and SSE3 instructions. These instructions include 128-bit SIMD integer arithmetic
and 128-bit SIMD double-precision floating-point operations.
It has 8 KB L1 data cache and an execution trace cache to store up to 12 K decoded micro-
operations (μ-ops) in the order of program execution.
Another features of Pentium 4 Processor is that it supports faster system bus at 400 MHz to 1066
MHz with 3.2 GB/s of bandwidth.
The Pentium 4 processor has two arithmetic logic units (ALUs) which are operated at twice the
core processor frequency.
It is fabricated in 0.18 micron CMOS process.
It has advanced dynamic execution.
It has enhanced branch prediction.
It has a rapid execution engine.
It has enhanced floating point/multimedia applications.

f. Write short note on hyper threading technology and its use in Pentium 4
Hyper-Threading Technology (HTT) is a technology developed by Intel to improve parallelization
of computations performed on x86 microprocessors. It allows a single physical processor core to
behave like two logical processors, enabling better performance for multi-threaded applications.
In the context of Pentium 4, HTT was introduced to improve the processor's efficiency in handling
multiple tasks simultaneously. It works by duplicating certain sections of the processor—those that
store the architectural state—but not duplicating the main execution resources. This allows the
processor to schedule the execution of multiple threads in parallel, leading to improved overall
performance.
HTT was particularly beneficial for Pentium 4 processors because it helped to mitigate the
performance limitations of the NetBurst micro architecture. Which was known for its relatively
long pipeline and high clock speeds. By enabling better utilization of the processor's resources,
HTT improved the overall efficiency of Pentium 4 processors in handling multitasking workloads
and multi-threaded applications.
Overall, Hyper-Threading Technology in Pentium 4 allowed the processor to execute multiple
threads more efficiently, leading to improved performance and responsiveness in multitasking
environments.

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Q2 a. Explain the Register Organization of 80386 Processor.

The 80386 microprocessor has several important registers that play key roles in its operation. These
registers can be categorized into the following types:

Data Registers
The 80386 has eight 32-bit general-purpose data registers named EAX, EBX, ECX, EDX, ESI,
EDI, EBP, and ESP.
These registers are used for general arithmetic and data manipulation operations.
Pointer and Index Registers
EIP (Instruction Pointer): This 32-bit register holds the offset address of the next instruction to be
executed.
ESP (Stack Pointer): It points to the top of the stack.
EBP (Base Pointer): It is used to reference parameters and local variables on the stack.
Segment Registers
CS (Code Segment): Points to the segment where the instruction resides.
DS (Data Segment): Points to the segment where data is located.
SS (Stack Segment): Points to the segment of the stack.
ES (Extra Segment): An additional segment register for data.
Control Registers
CR0, CR2, CR3: These are control registers used for controlling and managing the operation of the
processor.
Status Registers
EFLAGS: This register contains status flags that indicate the result of arithmetic and logical
operations.
Debug Registers
DR0-DR7: These registers are used for debugging purposes.
Model-Specific Registers (MSRs)
These registers are used for processor-specific functions and are accessed using the RDMSR and
WRMSR instructions.
In summary, the 80386 microprocessor has a diverse set of registers that serve various purposes,
including data manipulation, addressing, control, status, and debugging.

b. Describe the Branch Prediction Mechanism of Pentium Processor.

The Pentium processor uses a branch prediction mechanism to improve performance by predicting
the outcome of conditional branches. Here's how it works:
The processor predicts whether a conditional branch will be taken or not taken based on historical
behavior and other factors.
If the prediction is correct, the processor continues executing instructions without any delay.
If the prediction is incorrect, the processor discards the incorrectly predicted instructions and starts
executing the correct ones, incurring a delay.
The Pentium processor employs various techniques for branch prediction, including:
Static Prediction: Simple prediction based on the type of branch instruction.
Dynamic Prediction: Using historical behavior and pattern analysis to predict branch outcomes.
Branch Target Buffer (BTB): Storing the target addresses of recent branches to predict the next
instruction's location.
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These mechanisms help reduce the performance impact of conditional branches, improving the
overall efficiency of the processor.

Q3. a. Compare 80386, Pentium 1 Pentium 2, and Pentium 3 Processor.

Year Clock Data Bus Address Bus

Processor Features
Released Speed Width Width
12-40 275,000 transistors, 1.5-3.1
80386 1985 32-bit 32-bit
MHz MIPS

60-300 Superscalar architecture,

Pentium 1 1993 32-bit 32-bit
MHz MMX technology

233-450 MMX technology, improved

Pentium 2 1997 32-bit 36-bit
MHz performance

450-1400 SSE instructions, improved

Pentium 3 1999 64-bit 36-bit
MHz performance

The 80386 was the first 32-bit processor in the x86 family, while the Pentium 1 introduced
superscalar architecture and MMX technology. The Pentium 2 increased clock speeds and
introduced a 36-bit address bus. The Pentium 3 further improved performance with SSE
instructions and higher clock speeds.

b. Design and Explain in detail Intel NetBurst Micro Architecture.

The Pentium 4 NetBurst microarchitecture was introduced by Intel in 2000. It was designed to
deliver high clock speeds and improved performance compared to its predecessors. The key
features of the NetBurst microarchitecture include:

Deep Pipeline: The Netburst microarchitecture featured a deep pipeline with 20 stages, allowing
for higher clock speeds. However, this also led to increased pipeline stalls and inefficiencies.
Rapid Execution Engine (REX): This feature aimed to improve the efficiency of instruction
execution by allowing the processor to handle more instructions per clock cycle.It included a "rapid
execution engine" to improve the execution of certain types of instructions, aiming to enhance
overall performance.

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Hyper Pipelined Technology: The NetBurst microarchitecture included a deeper pipeline
compared to previous architectures, allowing for higher clock speeds and potentially higher
performance.This technology, introduced with the Pentium 4, allowed a single physical processor
core to execute multiple threads simultaneously, improving overall efficiency.

Advanced Transfer Cache (ATC): The ATC was designed to improve the efficiency of data
transfer between the processor and the system memory.
SSE2 Instructions: The NetBurst microarchitecture introduced the Streaming SIMD Extensions 2
(SSE2) instruction set, which aimed to enhance multimedia and floating-point performance.
Netburst introduced the SSE2 (Streaming SIMD Extensions 2) instruction set, which enhanced
multimedia and gaming performance by enabling the processor to handle multiple data elements in
parallel.

INTEL Netburst Microarchitecture

Performance and Issues:

The Netburst microarchitecture initially achieved high clock speeds, but it also faced criticism for
its relatively lower performance in comparison to AMD's Athlon 64 processors, especially in terms
of power efficiency and real-world application performance. The deep pipeline design led to higher
power consumption and heat generation, which became a significant challenge for INTEL.
In summary, the Netburst microarchitecture was a significant departure from its predecessors,
focusing on high clock speeds and multimedia performance. However, it faced challenges in terms
of power efficiency and real-world performance, ultimately leading INTEL to transition to the more
efficient Core microarchitecture with the Core 2 Duo processors.