MODULE –3 PIPELINING

Pipeline:
Pipelining is a technique where multiple instructions are overlapped during
execution. It is a way of speeding up the execution of instructions.
Pipelining is the process of accumulating instruction from the processor
through a pipeline. It allows storing and executing instructions in an orderly
process. It is also known as pipeline processing. Pipeline is divided into
stages and these stages are connected with one another to form a pipe like
structure. Instructions enter from one end and exit from another end.
Traditional Pipeline Concept
Laundry Example
• Any, Bran, Charles, David each have one load of clothes to wash, dry,
and fold.
• Washer takes 30 minutes
• Dryer takes 40 minutes
• “Folder” takes 20 minutes

Sequential Laundry
 Pipelined Laundry

Pipelined laundry takes 3.5 hours

Observations:
 A task has a series of stages;
 Stage dependency:
e.g wash before dry;
 Multi tasks with overlapping stages;
 Simultaneously to speed up;
 Slowest stage determines the finish time;

An implementation technique whereby multiple instructions are overlapped in

execution.
e.g., B wash while A dry
 Essence: Start executing one instruction before completing the previous
one.
 Significance: Make fast CPUs
  Latency: the time for an instruction to complete.
 Throughput of a CPU: the number of instructions completed per second.
 Clock cycle: everything in CPU moves in lockstep; synchronized by the
clock.
 Processor Cycle: time required between moving an instruction one step
down the pipeline;
= time required to complete a pipe stage;
= max(times for completing all stages);
 CPI: clock cycles per instruction

TYPES OF PIPELINE:
 ARITHMETIC PIPELINE
 INSTRUCTION PIPELINE

ARITHMETIC PIPELINE:
Arithmetic pipelines are usually found in most of the computers. They are
used for floating point operations, multiplication of fixed point numbers
etc. For example: The input to the Floating Point Adder pipeline is:
X = A*2^a
Y = B*2^b
Here A and B are mantissas (significant digit of floating point numbers),
while a and b are exponents.

The floating point addition and subtraction is done in 4 parts:

 Compare the exponents.
 Align the mantissas.
 Add or subtract mantissas
 Produce the result.

Registers are used for storing the intermediate results between the above
operations.
 Example:

X= 0.952 x 10^3
Y= 0.82 x 10^2

1) Compare: 10^ 3 and 10^2

Choose the higher exponent i.e 3
2) Alignment: x=0.952 x10^3
y=0.082 x10^3
3) Add: z=1.034 x10^3
4) Normalize: z=0.1034 x10^4

Instruction Pipeline:

A stream of instructions can be executed by

overlapping fetch, decode and execute phases of an instruction cycle. This
type of technique is used to increase the throughput of the computer
system.
Instruction pipeline has 6 operations:
❑ Fetch instruction from memory(FI).
❑ Decode the instruction(DI).
❑ Calculate the Operands(CO).
❑ Fetch the operands from memory(FO).
❑ Execute the instruction(EI).
❑ Write Result(WR).

Instruction Fetch:
➢ IF stage is responsible for obtaining the requested instruction from
memory.
➢ The instruction and the program counter are stored in the register as
temporary storage.
Decode Instruction:
➢ DI stage is responsible for decoding the instruction and sending out
the various control lines to the other parts of the processor.
Calculate Operands:
➢ CO stage is where any calculations are performed. The main
component in this stage is ALU. The ALU is made up of arithmetic,
logic and capabilities.
Fetch Operands & Execute Instructions:
➢ FO and EI stages are responsible for storing and loading values to and
from memory. They also responsible for input and output from the
processor respectively.
Write Operands:
➢ WO stage is responsible for writing the result of calculation, memory
access or input into register file.

6 stage Pipeline Instruction

Example:

If 1 stage of an instruction takes 1 clock cycle of time and 1 instruction has 6

stages, then total time taken by 1 instruction is
Time=1 cc x 6= 6 cc
Suppose we have 5 instruction s to execute
Then total time taken by 5 instructions in non-pipeline architecture will be
6cc x 5= 30 cc

Stages/time 1 2 3 4 5 6 7 8 9 10
S1 I1 I2 I3 I4 I5
S2 I1 I2 I3 I4 I5
S3 I1 I2 I3 I4 I5
S4 I1 I2 I3 I4 I5
S5 I1 I2 I3 I4 I5
S6 I1 I2 I3 I4 I5

Total time taken by 5 instructions in pipeline architecture will be 10 cc.

First instruction will take time equals to no. of stages in 1 instruction. Rest
instructions will be completed by (n-1) time if n is the no. of instructions.

Performance of Pipelined processor:

Here we will assume a segment pipeline as 'k' and the clock cycle time 'Tp'.
Suppose the pipeline processor needs to complete the 'n' number of tasks. Now
the first instruction will come out from the pipeline by taking the 'k' cycle. On the
other hand, 'n-1' instructions will take only '1' cycle each. That means the 'n-1'
instruction will take the total 'n-1' cycle. In a pipeline processor, when we try to
execute the 'n' instructions, then the time taken to do this is described as follows:

ET pipeline = k + n -1 cycle

= (k + n -1) Tp
In a non-pipeline processor, when we take the same case and try to execute the
'n' instructions, then the time taken to do this is described as follows:

ET non-pipeline = n * k * Tp

So, when we perform 'n' tasks on the same processor, the speedup (S) of pipeline
processor over non-pipelined processor is described as follows:

S = Performance of pipeline processor / Performance of Non-pipelined processor

As the execution time and the performance of process is inversely proportional to

each other. So we have the following relation:

S = ET non-pipeline / ET pipeline

S = [n * k * Tp] / [(k + n -1) * Tp]

S = [n * k] / [k + n - 1]

The following relation will contain if the n number of tasks is larger than 'k' that
means n >>k.

S=n*k/n

S=k

Here K is used to indicate the number of stages in the pipeline.

Also, Efficiency = S / Smax

Here S is used to show the max speed up, and Smax is used to indicate the
Maximum speed up.

We know that Smax = k

So, Efficiency = S / k
Now throughput can be described like this:

Throughput = Number of instruction / Total time to complete the instruction

So throughput = n / (k + n + 1) * Tp

Pipeline Hazards:

1. Timing Variations: All stages cannot take same amount of time. This problem
generally occurs in instruction processing where different instructions have
different operand requirements and thus different processing time.

2. Data Hazards: When several instructions are in partial execution, and if they
reference same data then the problem arises. We must ensure that next
instruction does not attempt to access data before the current instruction,
because this will lead to incorrect results.

3. Branching: In order to fetch and execute the next instruction, we must know
what that instruction is. If the present instruction is a conditional branch, and its
result will lead us to the next instruction, then the next instruction may not be
known until the current one is processed.

4. Interrupts: Interrupts set unwanted instruction into the instruction stream.

Interrupts effect the execution of instruction.

5. Data Dependency: It arises when an instruction depends upon the result of a

previous instruction but this result is not yet available.