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Module 2 Ar Reviewer

The document outlines the fundamental functions of a computer, which include input, processing, output, and storage. It explains the von Neumann architecture, detailing how instructions are fetched and executed sequentially from memory, and introduces various types of interrupts that can occur during processing. Additionally, it describes the I/O function and the structure of an I/O program, emphasizing the importance of handling multiple interrupts in computing tasks.

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13 views2 pages

Module 2 Ar Reviewer

The document outlines the fundamental functions of a computer, which include input, processing, output, and storage. It explains the von Neumann architecture, detailing how instructions are fetched and executed sequentially from memory, and introduces various types of interrupts that can occur during processing. Additionally, it describes the I/O function and the structure of an I/O program, emphasizing the importance of handling multiple interrupts in computing tasks.

Uploaded by

210497colandog
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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MODULE 2 AR REVIEWER  We can think of the process of

connecting the various components in


“COMPUTER FUNCTION AND
the desired configuration as a form of
INTERCONNECTION”
programming.
Taking data and instructions from a user,  The resulting “program” is in the form of
processing the data as per instructions, hardware and is termed a hardwired
and displaying or storing the processed program.
data, are the FOUR MAJOR FUNCTIONS
OF A COMPUTER. These functions are also
known as the input function, process
function, output function, and storage
function, respectively.

INSTRUCTION FETCH AND EXECUTE


At the beginning of each instruction cycle, the
processor fetches an instruction from memory. In a
typical processor, a register called the program
counter (PC) holds the address of the instruction to
COMPUTER COMPONENTS be fetched next. Unless told otherwise, the
processor always increments the PC after each
Virtually all contemporary computer designs instruction fetch so that it will fetch the next
are based on concepts developed by John instruction in sequence (i.e., the instruction located
von Neumann at the Institute for Advanced at the next higher memory address).
Studies, Princeton. Such a design is referred
 So, for example, consider a computer in which each
to as the von Neumann architecture and is
instruction occupies one 16-bit word of memory.
based on three key concepts:  Assume that the program counter is set to memory
 Data and instructions are stored in a location 300, where the location address refers to a
16-bit word.
single read–write memory.
 The processor will next fetch the instruction at
 The contents of this memory are
location 300. On succeeding instruction cycles, it
addressable by location, without will fetch instructions from locations 301, 302, 303,
regard to the type of data contained and so on.
there.
 Execution occurs in a sequential fashion The fetched instruction is loaded into a register in
(unless explicitly modified) from one the processor known as the instruction register (IR).
The instruction contains bits that specify the action
instruction to the next.
the processor is to take. The processor interprets
the instruction and performs the required action.

 There is a small set of basic logic In general, these actions fall into four categories.
components that can be combined in  Processor-Memory
various ways.  Processor-I/O
 If there is a particular computation to be  Data Processing
performed, a configuration of logic  Control
components.
Program counter (PC) = Address of instruction  The printer will generate an interrupt every
Instruction register (IR) = Instruction being executed
time it completes a print operation.
 The communication line controller will
Accumulator (AC) = Temporary storage generate an interrupt every time a unit of
CLASSES OF INTERRUPTS data arrives.
 The unit could either be a single character
Program Generated by some condition or a block, depending on the nature of
that occurs as a result of an instruction the communications discipline In any
execution, such as arithmetic overflow, case, it is possible for a communications
division by zero, attempt to execute an interrupt to occur while a printer interrupt
illegal machine instruction, or reference is being processed.
outside a user's allowed memory space.
I/O Function
Timer Generated by a timer within the
processor. This allows the operating  An I/O module (e.g., a disk controller)
system to perform certain functions on a can exchange data directly with the
regular basis. processor.
 Just as the processor can initiate a read
I/O Generated by an I/O controller, to or write with memory, designating the
signal normal completion of an operation, address of a specific location, the
request service from the processor, or to processor can also read data from or
signal a variety of error conditions. write data to an I/O module.
 In this latter case, the processor
Hardware Failure Generated by a failure
identifies a specific device that is
such as power failure or memory parity
controlled by a particular I/O module.
error.
The I/O program consists of three
sections:
 A sequence of instructions, labeled 4 in
the figure, to prepare for the actual I/O
operation.
 The actual I/O command. Without the use
of interrupts, once this command is
issued, the program must wait for the I/O
device to perform the requested function
(or periodically poll the device).
 A sequence of instructions, labeled 5 in
the figure, to complete the operation.
This may include setting a flag indicating
the success or failure of the operation.
MULTIPLE INTERRUPTS
 For example, a program may be receiving
data from a communications line and
printing results.

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