CTS

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CTS

Clock Tree Synthesis (CTS) is one of the most important stages in PnR. CTS QoR decides ming convergence &
power. In most of the ICs clock consumes 30-40 % of total power. So efficient clock architecture, clock ga ng &
clock tree implementa on helps to reduce power.

The process of distribu ng the clock and balancing the load is called CTS. Basically, delivering the clock to all
sequen al elements. CTS is the process of inser on of buffers or inverters along the clock paths of ASIC design
in order to achieve zero/minimum skew or balanced skew. Before CTS, all clock pins are driven by a single
clock source. CTS star ng point is clock source and CTS ending point is clock pins of sequen al cells.

Inputs of CTS:

- Technology file (. )

- Netlist

- SDC

- Library files (.lib & .lef) & TLU+ file

- Placement DEF file

- Clock specifica on file which contains Inser on delay, skew, clock transi on, clock cells, NDR, CTS tree
type, CTS excep ons, list of buffers/inverters etc...

CTS Targets:

- Skew

- Inser on delay
CTS Goals/Constraints:

- Max transi on

- Max capacitance

- Max fanout

CTS Flow:

- Read CTS SDC

- Compile CTS using CTS spec file

- Place clock tree cells

- Route clock tree

Clock Latency/Inser on Delay:

The me taken by the clock to reach the sink point from the clock source is called Latency. It is divided into
two parts – Clock Source Latency and Clock Network Latency.
Clock Source Latency:
- The delay between the clock waveform origin point to the defini on point.
Clock Network Latency:
- The delay from the clock defini on point to the des na on/sink point.
Clock Skew:

The difference in the clock latencies of two flops belong to the same clock domain.
- If the capture clock latency is more than the launch clock, then it is posi ve skew. This helps to meet
setup.
- If the capture clock latency is less than the launch clock, then it is nega ve skew. This helps to meet hold.
Local Skew:
- The difference in the clock latencies of two logically connected flops of same clock domain.
Global Skew:
- The difference in the lowest clock latency and highest clock latency of two flops of same clock domain.
Clock Tree Reference:
By default, each clock tree references list contains all the clock buffers and clock inverters in the logic library.
The clock tree reference list is,

- Clock tree synthesis

- Boundary cell inser ons

- Sizing

- Delay inser on

Boundary cell inser ons:

- A boundary cell is a fixed buffer that is inserted immediately a er the boundary clock pins to preserve the
boundary condi ons of the clock pin.
 - When boundary cell inser on is enabled, buffer is inserted from the clock tree reference list immediately
a er the boundary clock pins. For mul -voltage designs, buffers are inserted at the boundary in the default
voltage area.

- The boundary cells are fixed for clock tree synthesis a er inser on; it can’t be moved or sized. In addi on,
no cells are inserted between a clock pin and its boundary cell.

Delay inser on:

- Advantage is the size and also power reduc on. But it has high varia on, so usage of delay cells in clock
tree is not recommended.

Clock Tree Excep ons:

Non-Stop pin:
Non-stop pins trace through the endpoints that are normally considered as endpoints of the clock tree.

Example:

- The clock pin of sequen al cells driving generated clock are implicit non-stop pins.

- Clock pin of ICG cells

Exclude pin are clock tree endpoints that are excluded from clock tree ming calcula on and op miza on.
The tool considers exclude pins only in calcula on and op miza ons for design rule constraints. During CTS,
the tool isolates exclude pins from the clock tree by inser ng a guide buffer before the pin or these pins are
need not to be considered during the clock tree propaga on.

Example - Non clock input pin of sequen al cell

In the above figure, beyond the exclude pin the tool never perform skew or inser on delay op miza on but
does perform design rule fixing.

Float pin:

Float pins are clock pins that have special inser on delay requirements and balancing is done according to the
delay [Macro modeling]. This is same as sync pin but internal clock latency of the pin is taken into
considera on while building the clock tree. To adjust the clock arrival for specific endpoints with respect to all
other endpoints.

Example - Clock entry pin of hard macros

Stop pin:

Stop pins are the endpoints of clock tree that are used for delay balancing. In CTS, the tool uses stop pins in
calcula on & op miza on for both DRC and clock tree ming.

Example - Clock sink are implicit stop pins

The op miza on is done only upto the stop pin as shown in the above fig. The clock signal should not
propagate a er reaching the stop/sync. This pin needs to be considered for building the clock tree.
Don't Touch Sub-tree:

If we want to preserve a por on of an exis ng clock tree, we put don’t touch excep on on the sub-tree.

- CLK1 is the pre-exis ng clock and path 1 is op mized with respect to CLK1.

- CLK2 is the new generated clock. Don’t touch sub-tree a ribute is set w.r.t C1.

Example:

- If path1 is 300ps and path2 is 200ps, during balancing delay are added in path2.

- If path1 is 200ps and path2 is 300ps, during balancing delay can’t be added on path1 because on path1
don’t touch a ribute is set and we get viola on.

Don't Buffer Net:

It is used in order to improve the results, by preven ng the tool from buffering certain nets. Don’t buffer nets
have high priority than DRC. CTS do not add buffers on such nets.

Example - If the path is a false path, then no need of balancing the path. So set don’t buffer net a ribute.

Don't Size Cell:

To prevent sizing of cells on the clock path during CTS and op miza on, we must iden fy the cell as don’t size
cells.

Specifying Size-Only Cells:

During CTS & op miza on, size only cells can only be sized not moved or split. A er sizing, if the cells overlap
with an adjacent cell a er sizing, the size-only cell might be moved during the legaliza on step.
Clock Tree Structures:

Cluster Based:

Most commonly used approach. Based on loca on of clock sinks, group them into clusters. It builds tree for all
individual clusters. Balance clusters by adding buffers at the root of the cluster.

H-Tree:

It is called Binary tree. Each driver has 2 symmetric sinks. Can be able to achieve very low skew with
reasonable buffer/inverter count. Clock port will be at the centre and skew will be minimal because of its
nature (branching kind of model). H-Tree structure will be routed in higher layers.

Advantages:

- Balanced latencies & Low skew

Disadvantages:

- Requires big driver, thus lots of power

- Requires more rou ng resources

X-Tree:

Advantages:

- Balanced latencies & Low skew

Disadvantages:

- Crosstalk
Conven onal Clock Tree & Clock Mesh:

Generally used on very high speed design like MCUs. The clock mesh includes a clock source, pre-mesh
drivers, mesh drivers, the mesh net, clock gates, mesh receivers and loads. The clock ga ng cells are spread
uniformally in design area irrespec ve of the clock sinks. Based on placement, clock sinks are connected to
clock ga ng cells.

The main difference between conven onal clock tree and clock mesh is the presence of the mesh net.
Another major difference is that the mesh drivers are connected to the mesh net as a mul -driven net.

Advantages:

- Low skew

- High OCV tolerance

Disadvantages:

- Requires more power charge the parasi c R&C of mesh

- Requires more rou ng resources

- Difficult to implement for the designs having more than one clock

Spine Tree:

The spine tree (Fish bone) arrangement makes it easy to reduce the skew but it is heavily influenced by
process parameters and may have problems with phase delay.
CTS Op miza on Techniques:

1. Buffer/Gate Sizing:

Sizes up or down buffers and gates to improve both skew and inser on delay.

2. Buffer/Gate Reloca on:

Physical loca on of the buffer or gate is moved to reduce skew and inser on delay.

3. Delay Inser on:

Delay is inserted for shortest paths.

4. Dummy Load Inser on:

Uses load balancing to fine tune the clock skew by increasing the shortest path delay.

Outputs of CTS:

- Timing report

- Conges on report

- Skew report

- Inser on delay report

- CTS DEF file