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Crack Sheet COA

The document outlines a Frequently Asked Theory Set (FATS) for assembly language programming and computer architecture topics, detailing the frequency of questions and their corresponding course outcomes. It provides preparation tips, a unit-wise breakdown of essential topics, and a practice paper formatted for examination. Key areas of focus include assembly language, memory instructions, CPU architecture, and cache coherence.

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2 views5 pages

Crack Sheet COA

The document outlines a Frequently Asked Theory Set (FATS) for assembly language programming and computer architecture topics, detailing the frequency of questions and their corresponding course outcomes. It provides preparation tips, a unit-wise breakdown of essential topics, and a practice paper formatted for examination. Key areas of focus include assembly language, memory instructions, CPU architecture, and cache coherence.

Uploaded by

aku1510aku
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Top Frequently Asked Theory Set (FATS)

No. Question / Topic Frequency Likely CO

1 Assembly language programming (add, subtract, multiply, loop) 6 times CO3

2 Memory reference instructions (AND, STA, etc.) 4 times CO2

3 Addressing modes (list & explain any 3/5 with examples) 4 times CO1

4 RISC vs CISC 4 times CO4

5 Associative / Direct / Set-associative cache mapping 4 times CO5

6 Microprogrammed control organization (with diagram) 3 times CO2

7 Booth's multiplication algorithm (with flowchart or example) 3 times CO1

8 Pipelining (conflicts, execution stages, 4-segment pipeline) 3 times CO4

9 Cache coherence problem and solutions 3 times CO5

10 First pass of assembler (with flowchart and explanation) 3 times CO3

11 Memory hierarchy (diagram/explanation) 3 times CO5

12 Register stack vs memory stack 3 times CO2

13 Instruction cycle (phases or full flowchart) 3 times CO2

14 Flynn's classification 3 times CO4

Create By: R.B.Navdariya


Top Tips for Preparation
1. Prioritize FATS topics – They typically cover over 60% of the exam.

2. Practice key diagrams – Instruction cycle, pipeline stages, control unit, Booth’s
algorithm, assembler pass.

3. Write assembly programs – For operations like addition, subtraction, multiplication


using loops or restricted instructions.

4. Memorize using structured tables – For registers, instruction formats, addressing


modes.

5. Master comparisons – Frequently asked: RISC vs CISC, SRAM vs DRAM, direct vs


indirect addressing.

6. Prepare CO-wise – Align your prep with course outcomes to focus your study
sessions.

Frequently Asked Theory Set (Unit-Wise Breakdown)


Unit 1: Basic Structure & Register Transfer (CO1)

• Register Transfer Language (RTL) with example – 2 times

• Basic Computer Registers (list with functionality) – 4 times

• Instruction Cycle with flowchart – 3 times

• Instruction formats and types – 3 times

• Addressing Modes (any 5 with examples) – 4 times

• Block diagram of Basic Computer – 2 times

Unit 2: Microoperations & Control Unit (CO2)

• Arithmetic & Logic Microoperations – 2 times

• Microprogrammed Control Organization (with diagram) – 3 times

• Address sequencing in control memory – 2 times

• Control word & Microinstruction format – 3 times

Unit 3: Programming the Basic Computer (CO3)

• Memory Reference Instructions (AND, STA, etc.) – 4 times

Create By: R.B.Navdariya


• Register Stack vs Memory Stack – 3 times

• Assembly Language Programs – 6 times

• Two/One/Zero Address Instruction Programs – 3 times

• BSA/BUN Instruction usage – 2 times

• First Pass of Assembler – 3 times

Unit 4: CPU & Pipelining (CO4)

• Pipelining Technique – 3 times

• RISC vs CISC – 4 times

• Flynn’s Classification – 3 times

• CPU-IOP Communication – 2 times

• SIMD/Arithmetic Pipeline – 2 times

Unit 5: Memory & I/O Organization (CO5)

• Cache Mapping (Direct, Associative, Set-associative) – 4 times

• Cache Coherence Problem – 3 times

• Memory Hierarchy – 3 times

• Virtual Memory – 2 times

• DMA and Interconnection Structures – 3 times

• RAM vs ROM / SRAM vs DRAM – 3 times

Create By: R.B.Navdariya


Practice Paper – COA (GTU Format)
Time: 2.5 Hours Total Marks: 70
Instructions:

1. Attempt all questions.

2. Make suitable assumptions wherever necessary.

3. Figures to the right indicate full marks.

4. Non-programmable calculator is allowed.

Q.1

(a) Convert (–29)₁₀ into 8-bit using:

• Signed Magnitude

• 1’s Complement

• 2’s Complement [03 Marks]

(b) List the Basic Computer’s registers with their size and function. [04 Marks]

(c) Explain the instruction cycle with a neat flowchart. [07 Marks]

Q.2

(a) Differentiate between direct and indirect addressing modes with examples. [03 Marks]

(b) Write an assembly program to subtract two numbers. [04 Marks]

(c) Write two-address and one-address instruction programs for:

X = (A + B) * (C – D)
Also, discuss their advantages and limitations. [07 Marks]

OR

(c) Explain Booth’s algorithm for A = +5 and B = –3 (4-bit representation). [07 Marks]

Q.3

(a) List and explain three types of pipeline conflicts. [03 Marks]

Create By: R.B.Navdariya


(b) Compare register stack vs memory stack. [04 Marks]

(c) Draw and explain a four-segment instruction pipeline. [07 Marks]

OR

(a) Write a short note on SIMD array processor. [03 Marks]

(b) Explain Fetch subroutine of microprogrammed control. [04 Marks]

(c) Explain addition and subtraction with signed magnitude data. Also list hardware required.
[07 Marks]

Q.4

(a) Differentiate associative and direct mapping in cache memory. [03 Marks]

(b) Write an assembly program to multiply using only the ADD instruction. [04 Marks]

(c) Explain address translation and the working of TLB with an example. [07 Marks]

OR

(a) Explain functionality of flags used in Basic Computer. [03 Marks]

(b) What is handshaking? Explain source-initiated data transfer with diagram. [04 Marks]

(c) Draw the flowchart for the first pass of an assembler and explain it. [07 Marks]

Q.5

(a) Compare write-through and write-back cache policies. [03 Marks]

(b) Describe the cache coherence problem and mention any two solutions. [04 Marks]

(c) Explain any three multiprocessor interconnection structures:

• Crossbar Interconnection

• Multistage Switching Network

• Hypercube Interconnection [07 Marks]

OR

(a) Differentiate tightly coupled and loosely coupled multiprocessor systems. [03 Marks]

(b) Write a short note on content addressable memory. [04 Marks]

(c) Discuss cache coherence problem and its solutions. [07 Marks]

Create By: R.B.Navdariya

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