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CA Lab8

The document explains the concept of critical datapath length in MIPS architecture, which is the longest delay through the datapath for any instruction and defines the minimum clock cycle time. It outlines the five pipeline stages of MIPS instructions and provides examples of different instruction paths, emphasizing that operations like 'lw' and custom operations such as 'conv' or 'gather' typically form the longest paths, while ALU-only operations have shorter datapaths. Additionally, it discusses optimization techniques like multicycle, pipelining, and forwarding to improve performance.

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Bùi Thế Tùng-44-A10
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32 views5 pages

CA Lab8

The document explains the concept of critical datapath length in MIPS architecture, which is the longest delay through the datapath for any instruction and defines the minimum clock cycle time. It outlines the five pipeline stages of MIPS instructions and provides examples of different instruction paths, emphasizing that operations like 'lw' and custom operations such as 'conv' or 'gather' typically form the longest paths, while ALU-only operations have shorter datapaths. Additionally, it discusses optimization techniques like multicycle, pipelining, and forwarding to improve performance.

Uploaded by

Bùi Thế Tùng-44-A10
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Understanding Critical Datapath

Length in MIPS Architecture

1. Introduction to Datapath
In computer architecture, a datapath is a collection of functional units such
as ALUs, multiplexers, and registers connected by buses where data flows. In
the MIPS architecture, the datapath is responsible for executing instructions.

The critical datapath length is the longest delay through the datapath for
any instruction — it defines the minimum clock cycle time.

2. MIPS Pipeline Stages


Each instruction goes through these 5 pipeline stages:

 IF: Instruction Fetch

 ID: Instruction Decode / Register Fetch

 EX: Execute / Address Calculation

 MEM: Memory Access

 WB: Write Back

3. Critical Path:
 Example with lw
 Instruction: lw $t1, 0($t2)
 Purpose: Load a word from memory into register $t1.

Path:

PC -> Instruction Memory -> Register File -> ALU -> Data Memory ->
Register File

lw $t1, 0($t2)
+ Given t1= the whole of your digit ID, please draw pipeline stages

4. Shorter Path: add and sub


Instructions:

add $t1, $t2, $t3

sub $t1, $t2, $t3

Path: PC -> Instruction Memory -> Register File -> ALU -> Register File

No need to access data memory.

+ Given t2= the whole of your digit ID, and t3=2089 please draw
pipeline stages

5. Multiply Example (mult)


Instruction:

mult $t1, $t2

mflo $t3 # Move result from LO

Path: Longer because multiplication is slower than addition. May


use multicycle units.

+ Given t1= the whole of your digit ID, and t2=2, please draw
pipeline stages

6. Gather Operation (Simulated)


High-level: gather = A[B[i]]

MIPS Equivalent:

lw $t0, 0($s1) # $s1 points to B[i], load index

sll $t0, $t0, 2 # Multiply index by 4


add $t1, $s2, $t0 # Base of A + offset

lw $t2, 0($t1) # Load A[B[i]]

+Given A=[12, 45, 67,0,5, -2,20,35], and i=3, please explain the
sample code above

7. Slice Operation (Bitwise)


High-level: Get bits 8–15 from register

MIPS Equivalent:

sll $t1, $t0, 16 # Shift left to remove higher bits

srl $t1, $t1, 24 # Shift right to isolate bits 8–15

+ Given t1= the whole of your digit ID, please draw pipeline stages

8. Convolution Example (1D 3-tap)


High-level: conv = a[i-1]*w1 + a[i]*w2 + a[i+1]*w3

MIPS Equivalent:

lw $t0, -4($s1) # a[i-1]

lw $t1, 0($s1) # a[i]

lw $t2, 4($s1) # a[i+1]

mul $t3, $t0, $s2 # w1

mul $t4, $t1, $s3 # w2

mul $t5, $t2, $s4 # w3

add $t6, $t3, $t4

add $t6, $t6, $t5 # final result


+Given A=[12, 45, 67,0,5, -2,20,35], and i=3, please explain the
sample code above

9. Summary
 Critical path determines minimum clock cycle.

 lw and custom operations like conv or gather often form the longest
path.

 ALU-only operations (e.g., add, sub) have shorter datapaths.

 Real-world designs use multicycle, pipelining, or forwarding to


optimize.

Image:

10. Questions for Students

1. Which MIPS instruction typically determines the clock cycle time in a


single-cycle processor?

2. How does the mult instruction impact datapath timing?

3. Why is gather or conv considered high-latency?

4. Give a high-latency instruction pattern below in MIPS and


explain why.

A sequence like lw, followed by div, then mflo is high-latency. For


example:

lw $t0, 0($s1)

lw $t1, 4($s1)

div $t0, $t1

mflo $t2
+ Explain:

+ Run and draw datapath of given instructions

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