ARM ARCHITECTURE

Introduction:

A complex instruction set computer, commonly known as CISC, is in complete contrast to the reduced instruction set computer, commonly known as RISC. Both stand for two entirely different philosophies in modern computer architecture. Some microcontrollers supports the RISC architecture some microcontrollers supports the CISC architecture. The example of the RISC architecture is 8085 microcontroller and ARM microcontrollers supports the RISC architecture.

DIFFERENCES BETWEEN THE RISC AND CISC ARCHITETURES:

What is CISC? In 1964 IBM released the IBM 360 to much acclaim. It is regarded as the first modern processor system and adopted the concept of microcoded control. Micro-coded control accommodated the use of complex instruction sets which is a vital concept within CISC architecture. A CISC central processing unit recognizes an enormous amount of instructions that denote highly complex task. The CISC based

architecture tends to throw the kitchen sink at the problem, items that are common to the architecture include:

It allowed for a much less complicated compiler as extremely complex tasks were implemented in micro-coding Instruction sets for loops Instruction sets for procedure calls Complex addressing modes Small program sizes, complex routines completed by hardware

What is RISC? A RISC (Reduced Instruction Set Computer) based system contains a much more minimized instruction set, allowing the programmer to break their application into much smaller steps, doing less, and simplifying their solutions. It was developed in response to the CISC approach and maintained that complex addressing took many instruction cycles to perform and would be much better facilitated by sequences of simpler instructions at a much higher frequency. RISC emphasized the instructions that were used most often and further optimized them for the fastest possible execution. RISC architecture would have the following common characteristics:

Uniform instruction formats Identical and many more general purpose registers Extremely simple addressing modes Very few data types A reduced instruction set Simplified architecture

Larger program sizes, complex routines are completed by the compiler Less costly to design, test, and manufacture Faster instruction execution

RISC maintains a few, simple pipelined instructions with fixed length and typically 1 instruction/cycle. They support only register-to-register operations and a few simple addressing modes (usually register addressing). Uses of CISC: Some common CISC based processors included the System/360, VAX, PDP-11, Motorola 68000 family, and Intel x86 architecture based processors. The CISC based architecture's crowning glory has to have been the Intel x86 lines in my opinion. The x86 generation defines the first few processor generations which were backward compatible with the original Intel 8086 and has revolutionized personal computing as we know it. The x86 architecture is now supported by an enormous amount of software and operating platforms such as the following systems, from MS-DOS, Windows, BSD, Linux, Solaris and recently more recently Mac OS-X. Through these systems, CISC can be seen throughout all industries from fashion to finance and from engineering to healthcare. To further push the CISC architecture, Intel aggressively marketed the Pentium 486 processors, this single act allowed people to have CISC based processors at a fraction of their development cost and changed the layout of the RISC versus CISC debate. Uses of RISC:

The RISC based architecture has become more prominent in the computer industry however it is only in recent times that this has become evident. The RISC chip is faster than its CISC counterpart as it is designed and built more economically, and predominantly retains those instructions that can be executed in one machine cycle or less. The RISC chip's influence can be seen lately within the Apple IPod, its ARM architecture dominates the market for high precision, lower power, low cost mobile embedded devices and is used in high class gaming consoles such as the Nintento Wii, Sony Play station 3 and throughout many other consoles such as the XBOX 360 (Controller). The RISC based architecture has very little impact on the desktop PC market where Intels x86 architecture remains the dominant processor, however it is making large inroads into the high-end server market, it should also be noted that in 2008 a RISC based architecture, Power Architecture-based Cell processors, within the IBM's Roadrunner is the number one recognized supercomputer in the world. It should still be noted that the vast majority of other supercomputers are using the x86 CISC architecture too.

FEATURES OF ARM ARCHITECTURE

Key features:

 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of onchip flash memory; 128-bit wide interface/accelerator enables high-speed 60 MHz operation In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software, single flash sector or full chip erase in 400 ms and programming of 256 B in 1 ms. Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip Real Monitor software and high-speed tracing of instruction execution USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA One or two (LPC2141/42 vs, LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog inputs, with conversion times as low as 2.44 ms per channel Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only) Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog. Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s), SPI and SSP with buffering and variable data length capabilities

 Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package Up to 21 external interrupt pins available 60 MHz maximum CPU clock available from programmable onchip PLL with settling time of 100 ms On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz Power saving modes include Idle and Power-down Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization Processor wake-up from Power-down mode via external interrupt or BOD Single power supply chip with POR and BOD circuits: CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.

CRITERIA FOR CHOOSING A MICROCONTROLLER

1. The first and foremost criterion for choosing a microcontroller is

that it must meet task at hands efficiently and cost effectively. In analyzing the needs of a microcontroller based project we must first see whether it is an 8-bit, 16-bit or 32-bit microcontroller

and how best it can handle the computing needs of the task most effectively. The other considerations in this category are: (a) Speed: The highest speed that the microcontroller supports (b) Packaging: Is it 40-pin DIP or QPF or some other packaging format? This is important in terms of space, assembling and prototyping the End product. (c) Power Consumption: This is especially critical for batterypowered Products. (d) The amount of RAM and ROM on chip (e) The number of I/O pins and timers on the chip. (f) Cost per unit: This is important in terms of final product in

which a microcontroller is used. 2. The second criteria in choosing a microcontroller are how easy it is to develop products around it. Key considerations include the availability of an assembler, debugger, a code efficient C language compiler, emulator, technical support and both in house and outside expertise. In many cases third party vendor support for chip is required.

3. The third criteria in choosing a microcontroller is it readily available in needed quantities both now and in future. For some

designers this is even more important than first two criterias. Currently, of leading 8bit microcontrollers, the 89C51 family has the largest number of diversified (multiple source) suppliers. By suppliers meant a producer besides the originator of microcontroller in the case of the 89C51, which was originated by Intel, several companies are also currently producing the 89C51. Viz: INTEL, ATMEL, These companies include PHILIPS, SIEMENS, and DALLAS-SEMICONDUCTOR. It should be noted that Motorola, Zilog and Microchip Technologies have all dedicated massive resource as to ensure wide and timely availability of their product since their product is stable, mature and single sourced. In recent years they also have begun to sell the ASIC library cell of the microcontroller.

CHAPTER III LPC2148 MICROCONTROLLER

LPC 2148 MICROCONTROLLER

General description of LPC 2148: The LPC2148 microcontrollers is based on a 32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine microcontrollers with embedded high-speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADCs, 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers suitable for industrial control and medical systems.

General overview of in system programming (ISP):

In-System Programming (ISP) is a process whereby a blank device mounted to a circuit board can be programmed with the end-user code without the need to remove the device from the circuit board. Also, a previously programmed device can be erased and Re programmed without removal from the circuit board. In order to perform ISP operations the microcontroller is powered up in a special ISP mode. ISP mode allows the microcontroller to communicate with an external host device through the serial port, such as a PC or terminal. The microcontroller receives commands and data from the host, erases and reprograms code memory, etc. Once the ISP operations have been completed the device is reconfigured so that it will operate normally the next time it is either reset or power removed and reapplied. All of the Philips microcontrollers shown in Table 1 and Table 2 have a 1 kbyte factory-masked ROM located in the upper 1 kbyte of code memory space from FC00 to FFFF. This 1 kbyte ROM is in addition to the memory blocks shown in Table 1 and Table 2. This ROM is referred to as the Bootrom. This Bootrom contains a set of instructions which allows the microcontroller to perform a number of Flash programming and erasing functions. The Bootrom also provides communications through the serial port. The use of the Bootrom is key to the concepts

of both ISP and In-Application Programming (IAP). The contents of the bootrom are provided by Philips and masked into every device. When the device is reset or power applied, and the EA/ pin is high or at the VPP voltage, the microcontroller will start executing instructions from either the user code memory space at address 0000h (normal mode) or will execute instructions from the Bootrom (ISP mode).

General Overview of IN APPLICATION PROGRAMMING:

Some applications may have a need to be able to erase and program code memory under the control fo the application. For example, an application may have a need to store calibration information or perhaps need to be able to download new code portions. This ability to erase and program code memory in the end-user application is InApplication Programming (IAP). The Bootrom routines which perform functions on the Flash memory during ISP mode such as programming, erasing, and reading, are also available to end-user programs. Thus it is possible for an end-user application to perform operations on the Flash memory. A common entry point (FFF0h) to these routines has been provided to simplify interfacing to the end-users application. Functions are performed by setting up specific registers as required by a specific operation and performing a call to the common entry point. Like any other subroutine call, after completion of the function, control will return to the end-users code. The Bootrom is shadowed with the user code memory in the address range from FC00h to FFFFh. This shadowing is controlled by the ENBOOT bit (AUXR1.5). When set, accesses to internal code memory in this address range will be from

the boot ROM. When cleared, accesses will be from the users code memory. It will be NECESSARY for the end-users code to set the ENBOOT bit prior to calling the common entry point for IAP operations, even for devices with 16 kbyte, 32 kbyte, and 64 kbyte of internal code memory. (ISP operation is selected by certain hardware conditions and control of the ENBOOT bit is automatic when ISP mode is activated).

BLOCK DIAGRAM:

PIN CONFIGURATION:

Pin Description:

P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while P0.31 is output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block.

P0.0/TXD0/PWM1:

P0.0

General purpose input/output digital pin (GPIO)

TXD0 Transmitter output for UART0 PWM1 Pulse Width Modulator output 1

P0.1/RXD0/PWM3/EINT0:

P0.1 General purpose input/output digital pin (GPIO) RXD0 Receiver input for UART0 PWM3 Pulse Width Modulator output 3 EINT0 External interrupt 0 input

P0.2/SCL0/ CAP0.0:

P0.2 General purpose input/output digital pin (GPIO) SCL0 I2C0 clock input/output, open-drain output (for I2C-bus compliance) CAP0.0 Capture input for Timer 0, channel 0

P0.3/SDA0/ MAT0.0/EINT1:

P0.3 General purpose input/output digital pin (GPIO) SDA0 I2C0 data input/output, open-drain output (for I2C-bus compliance) MAT0.0 Match output for Timer 0, channel 0 EINT1 External interrupt 1 input

P0.4/SCK0/ CAP0.1/AD0.6

P0.4 General purpose input/output digital pin (GPIO) SCK0 Serial clock for SPI0, SPI clock output from master or input to slave

CAP0.1 Capture input for Timer 0, channel 0 AD0.6 ADC 0, input 6.

P0.5/MISO0/ MAT0.1/AD0.7

P0.5 General purpose input/output digital pin (GPIO) MISO0 Master In Slave OUT for SPI0, data input to SPI master or data output from SPI slave. MAT0.1 Match output for Timer 0, channel 1 AD0.7 ADC 0, input 7

P0.6/MOSI0/ CAP0.2/AD1.0

P0.6 General purpose input/output digital pin (GPIO) MOSI0 Master out Slave In for SPI0, data output from SPI master or data Input to SPI slave CAP0.2 Capture input for Timer 0, channel 2 AD1.0 ADC 1, input 0, available in LPC2144/46/48 only

P0.7/SSEL0/PWM2/EINT2

P0.7 General purpose input/output digital pin (GPIO) SSEL0 Slave Select for SPI0, selects the SPI interface as a slave PWM2 Pulse Width Modulator output 2 EINT2 External interrupt 2 input

P0.8/TXD1/PWM4/AD1.1

P0.8 General purpose input/output digital pin (GPIO) TXD1 Transmitter output for UART1 PWM4 Pulse Width Modulator output 4 AD1.1 ADC 1, input 1, available in LPC2144/46/48 only

P0.9/RXD1/ PWM6/EINT3:

P0.9 General purpose input/output digital pin (GPIO) RXD1 Receiver input for UART1

PWM6 Pulse Width Modulator output 6 EINT3 External interrupt 3 input

P0.10/RTS1/ CAP1.0/AD1.2:

P0.10 General purpose input/output digital pin (GPIO) RTS1 Request to send output for UART1, LPC2144/46/48 only CAP1.0 Capture input for Timer 1, channel 0 AD1.2 ADC 1, input 2, available in LPC2144/46/48 only

P0.11/CTS1/ CAP1.1/SCL1:

P0.11 General purpose input/output digital pin (GPIO) CTS1 Clear to send input for UART1, available in LPC2144/46/48 only CAP1.1 Capture input for Timer 1, channel 1 SCL1 I2C1 clock input/output, open-drain output (for I2C-bus compliance)

P0.12/DSR1/MAT1.0/AD1.3:

P0.12 General purpose input/output digital pin (GPIO) DSR1 Data Set Ready input for UART1, available in LPC2144/46/48 only MAT1.0 Match output for Timer 1, channel 0 AD1.3 ADC input 3, available in LPC2144/46/48 only

P0.13/DTR1/ MAT1.1/AD1.4:

P0.13 General purpose input/output digital pin (GPIO) DTR1 Data Terminal Ready output for UART1, LPC2144/46/48 only MAT1.1 Match output for Timer 1, channel 1 AD1.4 ADC input 4, available in LPC2144/46/48 only

P0.14/DCD1/EINT1/SDA1:

P0.14 General purpose input/output digital pin (GPIO) DCD1 Data Carrier Detect input for UART1, LPC2144/46/48 only EINT1 External interrupt 1 input

SDA1 I2C1 data input/output, open-drain output (for I2C-bus compliance LOW on this pin while RESET is LOW forces on-chip boot loader to take over control of the part after reset

P0.15/RI1/ EINT2/AD1.5:

P0.15 General purpose input/output digital pin (GPIO) RI1 Ring Indicator input for UART1, available in LPC2144/46/48 only EINT2 External interrupt 2 input AD1.5 ADC 1, input 5, available in LPC2144/46/48 only

P0.16/EINT0/MAT0.2/CAP0.2:

P0.16 General purpose input/output digital pin (GPIO) EINT0 External interrupt 0 input MAT0.2 Match output for Timer 0, channel 2 CAP0.2 Capture input for Timer 0, channel 2

P0.17/CAP1.2/ SCK1/MAT1.2:

P0.17 General purpose input/output digital pin (GPIO) CAP1.2 Capture input for Timer 1, channel 2 SCK1 Serial Clock for SSP, clock output from master or input to slave MAT1.2 Match output for Timer 1, channel 2

P0.18/CAP1.3/MISO1/MAT1.3:

P0.18 General purpose input/output digital pin (GPIO) CAP1.3 Capture input for Timer 1, channel 3 MISO1 Master In Slave Out for SSP, data input to SPI master or data output from SSP slave MAT1.3 Match output for Timer 1, channel 3

P0.19/MAT1.2/MOSI1/CAP1.2:

P0.19 General purpose input/output digital pin (GPIO)

MAT1.2 Match output for Timer 1, channel 2 MOSI1 Master out Slave In for SSP, data output from SSP master or data Input to SSP slave CAP1.2 Capture input for Timer 1, channel 2

P0.20/MAT1.3/SSEL1/EINT3:

P0.20 General purpose input/output digital pin (GPIO) MAT1.3 Match output for Timer 1, channel 3 SSEL1 Slave Select for SSP, selects the SSP interface as a slave EINT3 External interrupt 3 input

P0.21/PWM5/AD1.6/CAP1.3:

P0.21 General purpose input/output digital pin (GPIO) PWM5 Pulse Width Modulator output 5 AD1.6 ADC 1, input 6, available in LPC2144/46/48 only CAP1.3 Capture input for Timer 1, channel 3

P0.22/AD1.7/CAP0.0/MAT0.0:

P0.22 General purpose input/output digital pin (GPIO) AD1.7 ADC 1, input 7, available in LPC2144/46/48 only CAP0.0 Capture input for Timer 0, channel 0 MAT0.0 Match output for Timer 0, channel 0

P0.23/VBUS:

P0.23 General purpose input/output digital pin (GPIO) VBUS Indicates the presence of USB bus power This signal must be HIGH for USB reset to occur

P0.25/AD0.4/AOUT:

P0.25 General purpose input/output digital pin (GPIO) AD0.4 ADC 0, input 4 AOUT DAC output, available in LPC2142/44/46/48 only

P0.28/AD0.1/CAP0.2/MAT0.2:

P0.28 General purpose input/output digital pin (GPIO) AD0.1 ADC 0, input 1 CAP0.2 Capture input for Timer 0, channel 2 MAT0.2 Match output for Timer 0, channel 2

P0.29/AD0.2/CAP0.3/MAT0.3:

P0.29 General purpose input/output digital pin (GPIO) AD0.2 ADC 0, input 2 CAP0.3 Capture input for Timer 0, Channel 3 MAT0.3 Match output for Timer 0, channel 3

P0.30/AD0.3/EINT3/CAP0.0:

P0.30 General purpose input/output digital pin (GPIO) AD0.3 ADC 0, input 3 EINT3 External interrupt 3 input CAP0.0 Capture input for Timer 0, channel 0

P0.31/UP_LED/CONNECT

P0.31 General purpose output only digital pin (GPO) UP_LED USB Good Link LED indicator, it is LOW when device is configured (non-control endpoints enabled), it is HIGH when the device is not configured or during global suspend CONNECT Signal used to switch an external 1.5 kohms resistor under the Software control, used with the Soft Connect USB feature Important: This is a digital output only pin, this pin MUST NOT be externally pulled LOW when RESET pin is LOW or the JTAG port will be disabled P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit, the operation of port 1 pins depends upon the pin function selected via the pin connect block, pins 0 through 15 of port 1 are not Available.

P1.16/TRACEPKT0

P1.16 General purpose input/output digital pin (GPIO) TRACEPKT0 Trace Packet, bit 0, standard I/O port with internal pullup

P1.17/TRACEPKT1

P1.17 General purpose input/output digital pin (GPIO) TRACEPKT1 Trace Packet, bit 1, standard I/O port with internal pullup

P1.18/TRACEPKT2

P1.18 General purpose input/output digital pin (GPIO) TRACEPKT2 Trace Packet, bit 2, standard I/O port with internal pullup

P1.19/TRACEPKT3

P1.19 General purpose input/output digital pin (GPIO) TRACEPKT3 Trace Packet, bit 3, standard I/O port with internal pullup

P1.20/TRACESYNC

P1.20 General purpose input/output digital pin (GPIO) TRACESYNC Trace Synchronization, standard I/O port with internal pull-up Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to operate as Trace port after reset

P1.21/PIPESTAT0

P1.21 General purpose input/output digital pin (GPIO) PIPESTAT0 Pipeline Status, bit 0, standard I/O port with internal pull-up

P1.22/PIPESTAT1

P1.22 General purpose input/output digital pin (GPIO) PIPESTAT1 Pipeline Status, bit 1, standard I/O port with internal pull-up

P1.23/PIPESTAT2

P1.23 General purpose input/output digital pin (GPIO)

PIPESTAT2 Pipeline Status, bit 2, standard I/O port with internal pull-up

P1.24/TRACECLK

P1.24 General purpose input/output digital pin (GPIO) TRACECLK Trace Clock, standard I/O port with internal pull-up

P1.25/EXTIN0

P1.25 General purpose input/output digital pin (GPIO) EXTIN0 External Trigger Input, standard I/O with internal pull-up

P1.26/RTCK

P1.26 General purpose input/output digital pin (GPIO) RTCK Returned Test Clock output, extra signal added to the JTAG port, assists debugger synchronization when processor frequency varies, bidirectional pin with internal pull-up Note: LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate a Debug port after reset

P1.27/TDO

P1.27 General purpose input/output digital pin (GPIO) TDO Test Data out for JTAG interface

P1.28/TDI

P1.28 General purpose input/output digital pin (GPIO) TDI Test Data in for JTAG interface

P1.29/TCK

P1.29 General purpose input/output digital pin (GPIO) TCK Test Clock for JTAG interface

P1.30/TMS

P1.30 General purpose input/output digital pin (GPIO) TMS Test Mode Select for JTAG interface

P1.31/TRST

P1.31 General purpose input/output digital pin (GPIO) TRST Test Reset for JTAG interface

D+: USB bidirectional D+ line

D- : USB bidirectional D- line

RESET External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0, TTL with hysteretic, 5 V tolerant

XTAL1: Input to the oscillator circuit and internal clock generator circuits XTAL2: Output from the oscillator amplifier RTCX1: I Input to the RTC oscillator circuit

RTCX2: Output from the RTC oscillator circuit

VSS: 6, 18, 25, 42, 50 pins are for supply voltage.

Ground: 0 V reference.

VSSA Analog ground: 0 V reference, this should nominally be the same voltage as VSS, but should be isolated to minimize noise and error

VDD 23, 43, 51 I 3.3 V power supply: This is the power supply voltage for the core and I/O ports.

VDDA 7 I Analog 3.3 V power supply: This should be nominally the same voltage as VDD but should be isolated to minimize noise and error, this voltage is only used to power the on-chip ADC(s) and DAC

VREF ADC reference voltage: This should be nominally less than or equal to the VDD voltage but should be isolated to minimize noise and error, level on this

Pin is used as a reference for ADC(s) and DAC

VBAT RTC power supply voltage: 3.3 V on this pin supplies the power to the RTC. Functional Description:

Architectural Overview: The ARM7TDMI-S is a general purpose 32-bit

microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput And impressive real-time interrupt response from a small and costeffective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set.

Essentially, the ARM7TDMI-S processor has two instruction sets: The standard 32-bit ARM set A 16-bit Thumb set

The Thumb sets 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMs performance advantage over a traditional 16-bit processor using 16bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections (such as interrupt service routines and DSP algorithms) in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30 % over Thumb mode. On-Chip Flash Program memory:

The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is

running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. Due to the architectural solution chosen for an on-chip boot loader, flash memory available for users code on LPC2141/42/44/46/48 is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively.

The LPC2141/42/44/46/48 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data-retention. On-Chip Static RAM:

On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB, 16 kB and 32 kB of static RAM respectively. In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution.

Memory Map:

The LPC2141/42/44/46/48 memory map incorporates several distinct regions, as shown below.

 Interrupt controller:

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.

Fast interrupt request (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.

Interrupt Sources: Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Pin Connect Block:

The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

The Pin Control Module with its pin select registers defines the functionality of the microcontroller in a given hardware environment. After reset all pins of Port 0 and Port 1 are configured as input with the following exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality; if trace is enabled, the Trace pins will assume their trace functionality. The pins associated with the I2C0 and I2C1 interface are open drain.

Fast General purpose Parallel I/O: Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow the setting or clearing of any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. LPC2141/42/44/46/48 introduces accelerated GPIO functions over prior LPC2000 devices:

GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing Mask registers allow treating sets of port bits as a group, leaving other bits unchanged All GPIO registers are byte addressable Entire port value can be written in one instruction

 Bit-level set and clear registers allow a single instruction to set or clear any number of bits in one port Direction control of individual bits Separate control of output set and clear All I/O default to inputs after reset

10 bit ADC: The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital converters. These converters are single 10-bit successive approximation analog to digital converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.

I. Features: 10 bit successive approximation analog to digital converter Measurement range of 0 V to VREF (2.0 V VREF VDDA) Each converter capable of performing more than 400000 10-bit samples per second Every analog input has a dedicated result register to reduce interrupt overhead

Burst conversion mode for single or multiple inputs

 Optional conversion on transition on input pin or timer match signal Global Start command for both converters (LPC2142/44/46/48 only).

10 bit DAC: The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The maximum DAC output voltage is the VREF voltage. I. Features: 10-bit DAC Buffered output Power-down mode available Selectable speed versus power USB 2.0 Device controller:

The USB is a 4-wire serial bus that supports communication between a host and a number (127 max) of peripherals. The host controller allocates the USB bandwidth to Attached devices through a token based protocol. The bus supports hot plugging, unplugging, and dynamic configuration of the devices. All transactions are initiated by the host controller.

The LPC2141/42/44/46/48 is equipped with a USB device controller that enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint buffer and the USB RAM.

I. Features: Fully compliant with USB 2.0 Full-speed specification Supports 32 physical (16 logical) endpoints Supports control, bulk, interrupt and isochronous endpoints Scalable realization of endpoints at run time Endpoint maximum packet size selection (up to USB maximum Specification) by software at run time RAM message buffer size based on endpoint realization and maximum packet size Supports SoftConnect and Good Link LED indicator, these two functions packet size Supports bus-powered capability with low suspend current one pin Supports DMA transfer on all non-control endpoints (LPC2146/48 only)

 One duplex DMA channel serves all endpoints (LPC2146/48 only) Allows dynamic switching between CPU controlled and DMA modes (only in LPC2146/48) Double buffer implementation for bulk and isochronous endpoints

UARTS: The LPC2141/42/44/46/48 each contains two UARTs. In addition to standard transmit and receive data lines, the LPC2144/46/48 UART1 also provide a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware (UART1 in LPC2144/46/48 only).

I. Features 16 B Receive and Transmit FIFO Register locations conform to 16C550 industry standard Receiver FIFO triggers points at 1 B, 4 B, 8 B, and 14 B Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs

 LPC2144/46/48 UART1 equipped with standard modem interface signals, this module also provides full support for hardware flow control (auto-CTS/RTS) I2C Bus Serial I/O Controller

The LPC2141/42/44/46/48 each contains two I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiveronly device (e.g., an LCD driver or a transmitter with the capability to both receive and send information (such as memory)). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus; it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s (Fast I2C-bus).

I. Features: Compliant with standard I2C-bus interface Easy to configure as master, slave, or master/slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi-master bus (no central master)

 Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus

SPI Serial I/O Controller:

The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.

I. Features: Compliant with SPI specification Synchronous, Serial, Full Duplex, Communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate

SSP Serial I/O Controller

The LPC2141/42/44/46/48 each contains one SSP. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Micro wire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. Often only one of these data flows carries meaningful data. I. Features Compatible with Motorolas SPI, TIs 4-wire SSI and National Semiconductors Microwire buses Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive Four bits to 16 bits per frame

General Purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signals transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with or and

and,

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The

LPC2141/42/44/46/48 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts.

I. Features: A 32-bit timer/counter with a programmable 32-bit prescaler External event counter or timer operation Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions, a capture event may also optionally generate an interrupt

Four 32-bit match registers that allow: Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Four external outputs per timer/counter corresponding to match registers, with the following capabilities: Set LOW on match Set HIGH on match Toggle on match Do nothing on match

 Watchdog Timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. I. Feature: Internally resets chip if not periodically reloaded Debug mode Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled Incorrect/Incomplete feed sequence causes reset/interrupt if enabled Flag to indicate watchdog reset Programmable 32-bit timer with internal pre-scaler Selectable time period from (Tcy (PCLK) 256 4) to (Tcy(PCLK) 232

Real Time Clock: The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).

I. Features: Measures the passage of time to maintain a calendar and clock Ultra-low power design to support battery powered systems Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year Can use either the RTC dedicated 32 kHz oscillator input or clock derived RTC Dedicated power supply pin can be connected to a battery or the main 3.3 V from the external crystal/oscillator input at XTAL1, programmable reference clock divider allows fine adjustment of the

Pulse width modulator The PWM is based on the standard timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-

phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions.

Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two matches registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).

I. Features: Seven match registers allow up to six single edge controlled or three double edge controlled PWM outputs, or a mix of both types

 The match registers also allow: Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must release new match values before they can become effective. May be used as a standard timer if the PWM mode is not enabled A 32-bit Timer/Counter with a programmable 32-bit Rescale

System Control

1. Crystal Oscillator: On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected. 2. PLL: The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 ms.

3. Reset and Wake up Timer:

Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.

4. Brown out Detector

The LPC2141/42/44/46/48 includes 2-stage monitoring of the voltage on the VDD pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register.

The second stage of low voltage detection asserts reset to inactivate the LPC2141/42/44/46/48 when the voltage on the VDD pins falls below 2.6 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the POR circuitry maintains the overall reset.

Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition.

5. Code Security This feature of the LPC2141/42/44/46/48 allows an application to control whether it can be debugged or protected from observation. If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321 from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be protected from observation. Once debugging is disabled, it can be enabled only by performing a full chip erase using the ISP.

6. External Interrupt Inputs:

The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake-up the processor from Power-down mode. Additionally capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode.

7. Memory Mapping Control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.

8. Power Control

The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and Power-down mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved

throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip RTC will enable the microcontroller to have the RTC active during Power-down mode. Power-down current is increased with RTC active. However, it is significantly lower than in Idle mode. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during active and Idle mode.

9. VPB BUS:

The VPB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The first is to provide peripherals with the desired PCLK via VPB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be slowed down to 12 to 14 of the processor clock rate. Because the VPB bus must work properly at power-up (and its timing cannot be altered if it does not work since the VPB divider control registers reside on the VPB bus), the default condition at reset is for the VPB bus to run at 14 of the processor clock rate. The second purpose of the VPB divider is to allow power savings when an application does not require any peripherals to run at the full processor

rate. Because the VPB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.

10. Emulation and Debugging:

The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port0 are available during the development and debugging phase as they are when the application is run in the embedded system

11. Embedded ICE

Standard ARM Embedded ICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an Embedded ICE protocol converter. Embedded ICE protocol converter converts the remote debug protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the Embedded ICE logic.

12. Embedded Trace:

Since the LPC2141/42/44/46/48 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macro cell (ETM) provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the

trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction.

13. Real Monitor:

Real Monitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the Embedded ICE logic. The LPC2141/42/44/46/48 contains a specific configuration of Real Monitor software programmed into the on-chip flash memory.