LT8705

80V VIN and VOUT

Synchronous 4-Switch Buck-
Boost DC/DC Controller
FEATURES DESCRIPTION
n Single Inductor Allows VIN Above, Below, or Equal The LT®8705 is a high performance buck-boost switch-
to Regulated VOUT ing regulator controller that operates from input voltages
n VIN Range 2.8V (Need EXTVCC > 6.4V) to 80V above, below or equal to the output voltage. The part has
n VOUT Range: 1.3V to 80V integrated input current, input voltage, output current
n Quad N-Channel MOSFET Gate Drivers and output voltage feedback loops. With a wide 2.8V to
n Synchronous Rectification: Up to 98% Efficiency 80V input and 1.3V to 80V output range, the LT8705 is
n Input and Output Current Monitor Pins compatible with most solar, automotive, telecom and
n Synchronizable Fixed Frequency: 100kHz to 400kHz battery-powered systems.
n Integrated Input Current, Input Voltage, Output
The LT8705 includes servo pins to indicate which feedback
Current and Output Voltage Feedback Loops
loops are active. The MODE pin selects among Burst Mode®
n Clock Output Usable To Monitor Die Temperature
operation, discontinuous or continuous conduction mode
n Available in 38-Lead (5mm × 7mm) QFN and TSSOP
at light loads. Additional features include a 3.3V/12mA
Packages with the TSSOP Modified for Improved
LDO, a synchronizable fixed operating frequency, onboard
High Voltage Operation
gate drivers, adjustable UVLO, along with input and output
APPLICATIONS current monitoring with programmable maximum levels.
L, LT, LTC, LTM, Linear Technology, Burst Mode, µModule and the Linear logo are registered
n High Voltage Buck-Boost Converters trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
n Input or Output Current Limited Converters

TYPICAL APPLICATION
Telecom Voltage Stabilizer
M1
VIN 22µH M4 VOUT
×2
36V TO 48V
80V + 220µF 4.7µF M3 4.7µF
+ 220µF 5A
M2
×2 ×4 ×2 ×6 ×2
TO TO
DIODE DIODE
0.22µF 1nF 10Ω 0.22µF
2Ω 10mΩ
1nF 10Ω
×2 2Ω
×2
392k
Efficiency and Power Loss
TG1 BOOST1 SW1 BG1 CSP CSN GND BG2 SW2 BOOST2 TG2 100 6
CSNIN CSPOUT
5
CSPIN CSNOUT
95
VIN EXTVCC
POWER LOSS (W)

4
EFFICIENCY (%)

SHDN FBOUT
100k
SWEN INTVCC 10k 90 3
LDO33 LT8705 GATEVCC 4.7µF
MODE SRVO_FBIN 2
4.7µF 85
FBIN SRVO_FBOUT
1
RT SRVO_IIN 4Ω VOUT = 48V
ILOAD = 2A
71.5k SS SRVO_IOUT 80 0
30 40 50 60 70 80
IMON_IN
1µF TO TO VIN (V) 8705 TA01b

VC IMON_OUT BOOST1 BOOST2

CLKOUT SYNC
20k 215k
56.2k
202kHz
4.7µF 1µF 220pF 3.3nF

8705 TA01

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LT8705
ABSOLUTE MAXIMUM RATINGS (Note 1)

VCSP-VCSN, VCSPIN-VCSNIN, FBIN, SHDN Voltage.................................... –0.3V to 30V

VCSPOUT-VCSNOUT...................................... –0.3V to 0.3V CSNIN, CSPIN, CSPOUT, CSNOUT Voltage...–0.3V to 80V
SS, CLKOUT, CSP, CSN Voltage.................... –0.3V to 3V VIN, EXTVCC Voltage................................... –0.3V to 80V
VC Voltage (Note 2).................................... –0.3V to 2.2V SW1, SW2 Voltage.......................................81V (Note 7)
RT, LDO33, FBOUT Voltage........................... –0.3V to 5V BOOST1, BOOST2 Voltage.......................... –0.3V to 87V
IMON_IN, IMON_OUT Voltage...................... –0.3V to 5V BG1, BG2, TG1, TG2............................................ (Note 6)
SYNC Voltage............................................. –0.3V to 5.5V Operating Junction Temperature Range
INTVCC, GATEVCC Voltage............................. –0.3V to 7V LT8705E (Notes 3, 8).......................... –40°C to 125°C
VBOOST1-VSW1, VBOOST2-VSW2...................... –0.3V to 7V LT8705I (Notes 3, 8)........................... –40°C to 125°C
SWEN, MODE Voltage................................... –0.3V to 7V Storage Temperature Range................... –65°C to 150°C
SRVO_FBIN, SRVO_FBOUT Voltage............ –0.3V to 30V Lead Temperature (Soldering, 10 sec)
SRVO_IIN, SRVO_IOUT Voltage.................. –0.3V to 30V FE Package........................................................ 300°C

PIN CONFIGURATION
TOP VIEW

TOP VIEW INTVCC 1 38 VIN

IMON_IN

MODE 2 37 CSPIN
INTVCC

CSNIN
CSPIN
MODE
SWEN

IMON_IN 3 36 CSNIN
VIN

38 37 36 35 34 33 32 SHDN 4
SHDN 1 31 CSPOUT CSN 5 34 CSPOUT
CSN 2 30 CSNOUT CSP 6
CSP 3 29 EXTVCC LDO33 7 32 CSNOUT
LDO33 4 28 SRVO_FBOUT FBIN 8
FBIN 5 27 SRVO_IOUT FBOUT 9 30 EXTVCC
FBOUT 6 39 26 SRVO_IIN IMON_OUT 10 39
GND GND
IMON_OUT 7 25 SRVO_FBIN
VC 11 28 BOOST1
VC 8 24 NC
SS 12
SS 9 23 BOOST1
CLKOUT 13 26 TG1
CLKOUT 10 22 TG1
SYNC 14
SYNC 11 21 SW1
RT 15 24 SW1
RT 12 20 NC
GND 16
13 14 15 16 17 18 19
BG1 17 22 SW2
GND
BG1
GATEVCC
BG2
BOOST2
TG2
SW2

GATEVCC 18 21 TG2
BG2 19 20 BOOST2
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN FE PACKAGE
TJMAX = 125°C, θJA = 34°C/W VARIATION: FE38(31)
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB 38-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 25°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

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 LT8705
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8705EUHF#PBF LT8705EUHF#TRPBF 8705 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LT8705IUHF#PBF LT8705IUHF#TRPBF 8705 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LT8705EFE#PBF LT8705EFE#TRPBF LT8705FE 38-Lead Plastic TSSOP –40°C to 125°C
LT8705IFE#PBF LT8705IFE#TRPBF LT8705FE 38-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Voltage Supplies and Regulators
VIN Operating Voltage Range EXTVCC = 0V l 5.5 80 V
EXTVCC = 7.5V l 2.8 80 V
VIN Quiescent Current Not Switching, VEXTVCC = 0 2.65 4.2 mA
VIN Quiescent Current in Shutdown VSHDN = 0V 0 1 µA
EXTVCC Switchover Voltage IINTVCC = 20mA, VEXTVCC Rising l 6.15 6.4 6.6 V
EXTVCC Switchover Hysteresis 0.18 V
INTVCC Current Limit Maximum Current Draw from INTVCC and LDO33
Pins Combined. Regulated from VIN or EXTVCC (12V)
INTVCC = 5.25V l 90 127 165 mA
INTVCC = 4.5V l 28 42 55 mA
INTVCC Voltage Regulated from VIN, IINTVCC = 20mA l 6.15 6.35 6.55 V
Regulated from EXTVCC (12V), IINTVCC = 20mA l 6.15 6.35 6.55 V
INTVCC Load Regulation IINTVCC = 0mA to 50mA –0.5 –1.5 %
INTVCC, GATEVCC Undervoltage Lockout INTVCC Falling, GATEVCC Connected to INTVCC l 4.45 4.65 4.85 V
INTVCC, GATEVCC Undervoltage Lockout Hysteresis GATEVCC Connected to INTVCC 160 mV
INTVCC Regulator Dropout Voltage VIN-VINTVCC, IINTVCC = 20mA 245 mV
LDO33 Pin Voltage 5mA from LDO33 Pin l 3.23 3.295 3.35 V
LDO33 Pin Load Regulation ILDO33 = 0.1mA to 5mA –0.25 –1 %
LDO33 Pin Current Limit l 12 17.25 22 mA
LDO33 Pin Undervoltage Lockout LDO33 Falling 2.96 3.04 3.12 V
LDO33 Pin Undervoltage Lockout Hysteresis 35 mV
Switching Regulator Control
Maximum Current Sense Threshold (VCSP – VCSN) Boost Mode, Minimum M3 Switch Duty Cycle l 102 117 132 mV
Maximum Current Sense Threshold (VCSN – VCSP) Buck Mode, Minimum M2 Switch Duty Cycle l 69 86 102 mV
Gain from VC to Maximum Current Sense Voltage Boost Mode 150 mV/V
(VCSP-VCSN) (A5 in the Block Diagram) Buck Mode –150 mV/V
SHDN Input Voltage High SHDN Rising to Enable the Device l 1.184 1.234 1.284 V
SHDN Input Voltage High Hysteresis 50 mV
SHDN Input Voltage Low Device Disabled, Low Quiescent Current l 0.35 V

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LT8705
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SHDN Pin Bias Current VSHDN = 3V 0 1 µA
VSHDN = 12V 11 22 µA
SWEN Rising Threshold Voltage (Note 5) l 1.156 1.206 1.256 V
SWEN Threshold Voltage Hysteresis (Note 5) 22 mV
MODE Pin Forced Continuous Mode Threshold l 0.4 V
MODE Pin Burst Mode Range l 1.0 1.7 V
MODE Pin Discontinuous Mode Threshold l 2.3 V
Soft-Start Charging Current VSS = 0.5V 13 19 25 µA
Soft-Start Discharge Current VSS = 0.5V 9.5 µA
Voltage Regulator Loops (Refer to Block Diagram to Locate Amplifiers)
Regulation Voltage for FBOUT VC = 1.2V l 1.193 1.207 1.222 V
Regulation Voltage for FBIN VC = 1.2V l 1.184 1.205 1.226 V
Line Regulation for FBOUT and FBIN Error Amp Reference VIN = 12V to 80V 0.002 0.005 %/V
Voltage
FBOUT Pin Bias Current Current Out of Pin 15 nA
FBOUT Error Amp EA4 gm 315 µmho
FBOUT Error Amp EA4 Voltage Gain 220 V/V
FBIN Pin Bias Current Current Out of Pin 10 nA
FBIN Error Amp EA3 gm 130 µmho
FBIN Error Amp EA3 Voltage Gain 90 V/V
SRVO_FBIN Activation Threshold (Note 5) (VFBIN Falling) – (Regulation Voltage for FBIN), 56 72 89 mV
VFBOUT = VIMON_IN = VIMON_OUT = 0V
SRVO_FBIN Activation Threshold Hysteresis (Note 5) VFBOUT = VIMON_IN = VIMON_OUT = 0V 33 mV
SRVO_FBOUT Activation Threshold (Note 5) (VFBOUT Rising) – (Regulation Voltage for FBOUT), –37 –29 –21 mV
VFBIN = 3V, VIMON_IN = VIMON_OUT = 0V
SRVO_FBOUT Activation Threshold Hysteresis (Note 5) VFBIN = 3V, VIMON_IN = 0V, VIMON_OUT = 0V 15 mV
SRVO_FBIN, SRVO_FBOUT Low Voltage (Note 5) I = 100μA l 110 330 mV
SRVO_FBIN, SRVO_FBOUT Leakage Current (Note 5) VSRVO_FBIN = VSRVO_FBOUT = 2.5V l 0 1 µA
Current Regulation Loops (Refer to Block Diagram to Locate Amplifiers)
Regulation Voltages for IMON_IN and IMON_OUT VC = 1.2V l 1.187 1.208 1.229 V
Line Regulation for IMON_IN and IMON_OUT Error Amp VIN = 12V to 80V 0.002 0.005 %/V
Reference Voltage
CSPIN, CSNIN Bias Current BOOST Capacitor Charge Control Block Not Active
ICSPIN + ICSNIN, VCSPIN = VCSNIN = 12V 31 µA
CSPIN, CSNIN Common Mode Operating Voltage Range l 1.5 80 V
CSPIN, CSNIN Differential Operating Voltage Range l –100 100 mV
VCSPIN-CSNIN to IMON_IN Amplifier A7 gm VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V 0.95 1 1.05 mmho
l 0.94 1 1.06 mmho
IMON_IN Maximum Output Current l 100 µA
IMON_IN Overvoltage Threshold l 1.55 1.61 1.67 V
IMON_IN Error Amp EA2 gm 185 µmho
IMON_IN Error Amp EA2 Voltage Gain 130 V/V

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 LT8705
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
CSPOUT, CSNOUT Bias Current BOOST Capacitor Charge Control Block Not Active
ICSPOUT + ICSNOUT, VCSPOUT = VCSNOUT = 12V 45 µA
ICSPOUT + ICSNOUT, VCSPOUT = VCSNOUT = 1.5V 4 µA
CSPOUT, CSNOUT Common Mode Operating Voltage Range l 0 80 V
CSPOUT, CSNOUT Differential Mode Operating Voltage Range l –100 100 mV
VCSPOUT-CSNOUT to IMON_OUT Amplifier A6 gm VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V 0.95 1 1.05 mmho
VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V l 0.94 1 1.085 mmho
VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V 0.65 1 1.35 mmho
VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V l 0.55 1 1.6 mmho
IMON_OUT Maximum Output Current l 100 µA
IMON_OUT Overvoltage Threshold l 1.55 1.61 1.67 V
IMON_OUT Error Amp EA1 gm 185 µmho
IMON_OUT Error Amp EA1 Voltage Gain 130 V/V
SRVO_IIN Activation Threshold (Note 5) (VIMON_IN Rising) – (Regulation Voltage for –60 –49 –37 mV
IMON_IN), VFBIN = 3V, VFBOUT = 0V, VIMON_OUT = 0V
SRVO_IIN Activation Threshold Hysteresis (Note 5) VFBIN = 3V, VFBOUT = 0V, VIMON_OUT = 0V 22 mV
SRVO_IOUT Activation Threshold (Note 5) (VIMON_OUT Rising) – (Regulation Voltage for IMON_ –62 –51 –39 mV
OUT), VFBIN = 3V, VFBOUT = 0V, VIMON_IN = 0V
SRVO_IOUT Activation Threshold Hystersis (Note 5) VFBIN = 3V, VFBOUT = 0V, VIMON_IN = 0V 22 mV
SRVO_IIN, SRVO_IOUT Low Voltage (Note 5) I = 100μA l 110 330 mV
SRVO_IIN, SRVO_IOUT Leakage Current (Note 5) VSRVO_IIN = VSRVO_IOUT = 2.5V l 0 1 µA
NMOS Gate Drivers
TG1, TG2 Rise Time CLOAD = 3300pF (Note 4) 20 ns
TG1, TG2 Fall Time CLOAD = 3300pF (Note 4) 20 ns
BG1, BG2 Rise Time CLOAD = 3300pF (Note 4) 20 ns
BG1, BG2 Fall Time CLOAD = 3300pF (Note 4) 20 ns
TG1 Off to BG1 On Delay CLOAD = 3300pF Each Driver 100 ns
BG1 Off to TG1 On Delay CLOAD = 3300pF Each Driver 80 ns
TG2 Off to BG2 On Delay CLOAD = 3300pF Each Driver 100 ns
BG2 Off to TG2 On Delay CLOAD = 3300pF Each Driver 80 ns
Minimum On-Time for Main Switch in Boost Operation Switch M3, CLOAD = 3300pF 265 ns
(tON(M3,MIN))
Minimum On-Time for Synchronous Switch in Buck Switch M2, CLOAD = 3300pF 260 ns
Operation (tON(M2,MIN))
Minimum Off-Time for Main Switch in Steady-State Boost Switch M3, CLOAD = 3300pF 245 ns
Operation
Minimum Off-Time for Synchronous Switch in Switch M2, CLOAD = 3300pF 245 ns
Steady-State Buck Operation
Oscillator
Switch Frequency Range SYNCing or Free Running 100 400 kHz
Switching Frequency, fOSC RT = 365k l 102 120 142 kHz
RT = 215k l 170 202 235 kHz
RT = 124K l 310 350 400 kHz

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LT8705
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SYNC High Level for Synchronization l 1.3 V
SYNC Low Level for Synchronization l 0.5 V
SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 20 80 %
Recommended Minimum SYNC Ratio fSYNC/fOSC 3/4
CLKOUT Output Voltage High 1mA Out of CLKOUT Pin 2.3 2.45 2.55 V
CLKOUT Output Voltage Low 1mA Into CLKOUT Pin 25 100 mV
CLKOUT Duty Cycle TJ = –40°C 22.7 %
TJ = 25°C 44.1 %
TJ = 125°C 77 %
CLKOUT Rise Time CLOAD = 200pF 30 ns
CLKOUT Fall Time CLOAD = 200pF 25 ns
CLKOUT Phase Delay SYNC Rising to CLKOUT Rising, fOSC = 100kHz l 160 180 200 Deg

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: Do not apply a voltage or current source to these pins. They must
may cause permanent damage to the device. Exposure to any Absolute be connected to capacitive loads only, otherwise permanent damage may
Maximum Rating condition for extended periods may affect device occur.
reliability and lifetime. Note 7: Negative voltages on the SW1 and SW2 pins are limited, in an
Note 2: Do not force voltage on the VC pin. application, by the body diodes of the external NMOS devices, M2 and
Note 3: The LT8705E is guaranteed to meet performance specifications M3, or parallel Schottky diodes when present. The SW1 and SW2 pins
from 0°C to 125°C junction temperature. Specifications over the –40°C are tolerant of these negative voltages in excess of one diode drop below
to 125°C operating junction temperature range are assured by design, ground, guaranteed by design.
characterization and correlation with statistical process controls. The Note 8: This IC includes overtemperature protection that is intended
LT8705I is guaranteed over the full –40°C to 125°C junction temperature to protect the device during momentary overload conditions. Junction
range. temperature will exceed the maximum operating junction temperature
Note 4: Rise and fall times are measured using 10% and 90% levels. when overtemperature protection is active. Continuous operation above
Delay times are measured using 50% levels. the specified maximum operating junction temperature may impair device
Note 5: This specification not applicable in the FE38 package. reliability.

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 LT8705
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified.

Efficiency vs Output Current Efficiency vs Output Current Efficiency vs Output Current

(Boost Region-Figure 14) (Buck-Boost Region-Figure 14) (Buck Region-Figure 14)
100 100 100
90 90 90
80 80 80
70 70 70
EFFICIENCY (%)

EFFICIENCY (%)

EFFICIENCY (%)
60 60 60
50 50 50
40 40 40
30 VIN = 36V 30 VIN = 48V 30 VIN = 72V
VOUT = 48V VOUT = 48V VOUT = 48V
20 BURST 20 BURST 20 BURST
10 CCM 10 CCM 10 CCM
DCM DCM DCM
0 0 0
10 100 1000 10000 10 100 1000 10000 10 100 1000 10000
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
8705 G01 8705 G02 8705 G03

Feedback Voltages FBOUT Voltages (Five Parts) Oscillator Frequency

1.23 1.23 400
VC = 1.2V VC = 1.2V RT = 124k
350
1.22 1.22
300
FBOUT VOLTAGE (V)

FREQUENCY (kHz)
1.21 1.21
PIN VOLTAGE (V)

250
RT = 215k
1.20 1.20 200

150 RT = 365k
1.19 1.19
IMON_OUT 100
1.18 IMON_IN 1.18
FBOUT 50
FBIN
1.17 1.17 0
–55 –30 –5 20 45 70 95 120 145 –45 –20 5 30 55 80 105 130 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
8705 G04 8795 G05 8705 G06

Maximum Inductor Current Sense Inductor Current Sense Voltage at Maximum Inductor Current Sense
Voltage vs Duty Cycle Minimum Duty Cycle Voltage at Minimum Duty Cycle
140 120 120 120
BUCK REGION BOOST REGION
100 100
120 100
80 80
100 60 60 80 BUCK REGION
|CSP-CSN| (mV)
|CSP-CSN| (mV)

CSN-CSP (mV)

CSP-CSN (mV)

40 40
80 BOOST REGION BUCK REGION
20 20 60
60 BOOST REGION
0 0
40
40 –20 –20
–40 –40 20
20
–60 –60
0 –80 –80 0
0 20 40 60 80 100 0.5 1 1.5 2 –40 –20 0 20 40 60 80 100 120
M2 OR M3 DUTY CYCLE (%) VC (V) TEMPERATURE (°C)
8705 G07 8705 G08 8705 G09

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LT8705
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified.

Minimum Inductor Current Sense INTVCC Line Regulation INTVCC Line Regulation
Voltage in Forced Continuous Mode (EXTVCC = 0V) (VIN = 12V)
0 7.0 7.0

–20 6.5
BUCK REGION
–40
6.0 6.5
–|CSP-CSN| (mV)

EXTVCC RISING

INTVCC (V)

INTVCC (V)
–60
5.5
EXTVCC FALLING
–80
5.0 6.0
–100 BOOST REGION

–120 4.5

–140 4.0 5.5

0 20 40 60 80 100 4 6 8 10 12 14 16 18 20 4 6 8 10 12
M2 OR M3 DUTY CYCLE (%) VIN (V) EXTVCC (V)
8705 G10 8705 G11 8705 G12

VIN Supply Current vs Voltage

Maximum VC vs SS (Not Switching) IMON Output Currents
2.0 3.5 200
TJ = 25°C GATEVCC CONNECTED TO INTVCC
1.8 175
BOOST AND 3.0
1.6 BUCK
BUCK-BOOST REGIONS 150
REGION

IMON_OUT, IMON_IN (µA)

1.4 2.5
125
MAXIMUM VC (V)

1.2
2.0
IIN (mA)

100
1.0
1.5 75
0.8
50
0.6 1.0
0.4 25
0.5 125°C
0.2 25°C 0
–40°C
0 0 –25
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 5 15 25 35 45 55 65 75 –100 –50 0 50 100 150 200
SS (V) VIN (V) CSPIN-CSNIN (mV)
8705 G13 8705 G14 CSPOUT-CSNOUT (mV) 8705 G15

LDO33 Pin Regulation SHDN and SWEN Pin Thresholds

CLKOUT Duty Cycle (ILDO33 = 1mA) vs Temperature
100 3.5 1.30
1.28
80 1.26
PIN THRESHOLD VOLTAGE (V)

3.0
1.24
DUTY CYCLE (%)

60
1.22 RISING
LDO (V)

2.5 1.20
40 1.18
FALLING
1.16
2.0
20 125°C 1.14
25°C 1.12 SHDN
–40°C SWEN
0 1.5 1.10
–50 –25 0 25 50 75 100 125 150 2.5 3 3.5 4 4.5 5 5.5 6 –55 –35 –15 5 25 45 65 85 105 125 145
TEMPERATURE (°C) INTVCC (V) TEMPERATURE (°C)
8705 G16 8705 G17 8705 G18

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 LT8705
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified.

SRVO_xx Pin Activation

SHDN and MODE Pin Currents Internal VIN UVLO Thresholds
18 3.0 125
16

VPIN APPROACHING VREGULATION (mV)

MODE 100
2.5
14 SHDN
75
CURRENT INTO PIN (µA)

12

VPIN-VREGULATION
2.0
50

VIN UVLO (V)

10 FBIN
1.5 FBOUT
8 25
IMON_IN
6 IMON_OUT
0
1.0
4
–25
2
0.5
0 –50

–2 0 –75
0 3 6 9 12 15 18 21 24 27 30 –40 –20 0 20 40 60 80 100 120 –50 –25 0 25 50 75 100 125 150
PIN VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C)
8705 G19 8705 G20 8705 G21

SRVO_xx Pin Activation Threshold Forced Continuous Mode

Hysteresis Discontinuous Mode (Figure 14) (Figure 14)
50
PIN ACTIVATION THRESHOLD HYSTERSIS (mV)

SW1
40 20V/DIV
SW1
50V/DIV
30

SW2
20 20V/DIV
SW2
50V/DIV
FBIN
10 FBOUT IL IL
IMON_IN 2A/DIV 2A/DIV
IMON_OUT
0 8705 G23 8705 G24
–50 –25 0 25 50 75 100 125 150 VIN = 72V 5µs/DIV VIN = 36V 5µs/DIV
TEMPERATURE (°C) VOUT = 48V VOUT = 48V
8705 G22

Forced Continuous Mode Forced Continuous Mode

(Figure 14) (Figure 14)

SW1
20V/DIV SW1
50V/DIV

SW2 SW2
20V/DIV 20V/DIV

IL IL
2A/DIV 2A/DIV

8705 G25 8705 G26

VIN = 48V 5µs/DIV VIN = 72V 5µs/DIV
VOUT = 48V VOUT = 48V

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LT8705
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified.

Burst Mode Operation (Figure 14) Burst Mode Operation (Figure 14) Load Step (Figure 14)

VOUT VOUT
VOUT
100mV/DIV 500mV/DIV
100mV/DIV

IL
IL IL 2A/DIV
1A/DIV 5A/DIV

8705 G27 8705 G28 8705 G29

VIN = 36V 2ms/DIV VIN = 72V 5ms/DIV VIN = 36V 500µs/DIV
VOUT = 48V VOUT = 48V VOUT = 48V
LOAD STEP = 1A TO 3A

Load Step (Figure 14) Load Step (Figure 14)

VOUT VOUT
500mV/DIV 500mV/DIV

IL IL
2A/DIV 2A/DIV

8705 G31
VIN = 48V 500µs/DIV 8705 G30
VIN = 72V 500µs/DIV
VOUT = 48V VOUT = 48V
LOAD STEP = 1A TO 3A LOAD STEP = 1A TO 3A

Line Transient (Figure 14) Line Transient (Figure 14)

VIN VIN
36V TO 72V 72V TO 36V

VC VC
0.5V/DIV
0.5V/DIV
VOUT VOUT
0.5V/DIV 0.5V/DIV

IL IL
2A/DIV 2A/DIV

8705 G32 8705 G33

2ms/DIV 2ms/DIV

8705f

10 For more information www.linear.com/LT8705

 LT8705
PIN FUNCTIONS (QFN/TSSOP)

SHDN (Pin 1/Pin 4): Shutdown Pin. Tie high to enable RT (Pin 12/Pin 15): Timing Resistor Pin. Adjusts the switch-
device. Ground to shut down and reduce quiescent current ing frequency. Place a resistor from this pin to ground to
to a minimum. Do not float this pin. set the free-running frequency. Do not float this pin.
CSN (Pin 2/Pin 5): The (–) Input to the Inductor Current BG1, BG2 (Pins 14, 16/Pins 17, 19): Bottom Gate Drive.
Sense and Reverse-Current Detect Amplifier. Drives the gates of the bottom N-channel MOSFETs be-
tween ground and GATEVCC.
CSP (Pin 3/Pin 6): The (+) Input to the Inductor Current
Sense and Reverse-Current Detect Amplifier. The VC pin GATEVCC (Pin 15/Pin 18): Power Supply for Gate Drivers.
voltage and built-in offsets between CSP and CSN pins, in Must be connected to the INTVCC pin. Do not power from
conjunction with the RSENSE resistor value, set the current any other supply. Locally bypass to GND.
trip threshold.
BOOST1, BOOST2 (Pins 23, 17/Pins 28, 20): Boosted
LDO33 (Pin 4/Pin7): 3.3V Regulator Output. Bypass this Floating Driver Supply. The (+) terminal of the bootstrap
pin to ground with a minimum 0.1μF ceramic capacitor. capacitor connects here. The BOOST1 pin swings from a
FBIN (Pin 5/Pin 8): Input Feedback Pin. This pin is con- diode voltage below GATEVCC up to VIN + GATEVCC. The
BOOST2 pin swings from a diode voltage below GATEVCC
nected to the input error amplifier input.
up to VOUT + GATEVCC
FBOUT (Pin 6/Pin 9): Output Feedback Pin. This pin
TG1, TG2 (Pins 22, 18/Pins 26, 21): Top Gate Drive. Drives
connects the error amplifier input to an external resistor
the top N-channel MOSFETs with voltage swings equal
divider from the output.
to GATEVCC superimposed on the switch node voltages.
IMON_OUT (Pin 7/Pin 10): Output Current Monitor Pin. The
SW1, SW2 (Pins 21, 19/Pins 24, 22): Switch Nodes. The
current out of this pin is proportional to the output current.
(–) terminals of the bootstrap capacitors connect here.
See the Operation and Applications Information sections.
SRVO_FBIN (Pin 25 QFN Only): Open-Drain Logic Out-
VC (Pin 8/Pin 11): Error Amplifier Output Pin. Tie external
compensation network to this pin. put. This pin is pulled to ground when the input voltage
feedback loop is active.
SS (Pin 9/Pin 12): Soft-Start Pin. Place at least 100nF of
capacitance here. Upon start-up, this pin will be charged SRVO_IIN (Pin 26 QFN Only): Open-Drain Logic Output.
by an internal resistor to 2.5V. The pin is pulled to ground when the input current loop
is active.
CLKOUT (Pin 10/Pin 13): Clock Output Pin. Use this pin to
synchronize one or more compatible switching regulator SRVO_IOUT (Pin 27 QFN Only): Open-Drain Logic Out-
ICs to the LT8705. CLKOUT toggles at the same frequency put. The pin is pulled to ground when the output current
as the internal oscillator or as the SYNC pin, but is ap- feedback loop is active.
proximately 180° out of phase. CLKOUT may also be used SRVO_FBOUT (Pin 28 QFN Only): Open-Drain Logic Out-
as a temperature monitor since the CLKOUT duty cycle put. This pin is pulled to ground when the output voltage
varies linearly with the part’s junction temperature. The feedback loop is active.
CLKOUT pin can drive capacitive loads up to 200pF.
EXTVCC (Pin 29/Pin 30): External VCC Input. When EXTVCC
SYNC (Pin 11/Pin 14): To synchronize the switching fre- exceeds 6.4V (typical), INTVCC will be powered from this
quency to an outside clock, simply drive this pin with a pin. When EXTVCC is lower than 6.22V (typical), INTVCC
clock. The high voltage level of the clock needs to exceed will be powered from VIN.
1.3V, and the low level should be less than 0.5V. Drive this CSNOUT (Pin 30/Pin 32): The (–) Input to the Output Cur-
pin to less than 0.5V to revert to the internal free-running rent Monitor Amplifier. Connect this pin to VOUT when not
clock. See the Applications Information section for more in use. See Applications Information section for proper
information. use of this pin.
8705f

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LT8705
PIN FUNCTIONS (QFN/TSSOP)

CSPOUT (Pin 31/Pin 34): The (+) Input to the Output SWEN (Pin 36 QFN Only): Switch Enable Pin. Tie high
Current Monitor Amplifier. This pin and the CSNOUT pin to enable switching. Ground to disable switching. Don’t
measure the voltage across the sense resistor, RSENSE2, float this pin. This pin is internally tied to INTVCC in the
to provide the output current signals. Connect this pin TSSOP package.
to VOUT when not in use. See Applications Information
IMON_IN (Pin 38/Pin 3): Input Current Monitor Pin. The
section for proper use of this pin.
current out of this pin is proportional to the input current.
CSNIN (Pin 32/Pin 36): The (–) Input to the Input Current See the Operation and Applications Information sections.
Monitor Amplifier. This pin and the CSPIN pin measure
MODE (Pin 37/Pin 2): Mode Pin. The voltage applied to
the voltage across the sense resistor, RSENSE1, to provide
this pin sets the operating mode of the controller. When
the input current signals. Connect this pin to VIN when not
the applied voltage is less than 0.4V, the forced continu-
in use. See Applications Information section for proper
ous current mode is active. When this pin is allowed to
use of this pin.
float, Burst Mode operation is active. When the MODE pin
CSPIN (Pin 33/Pin 37): The (+) Input to the Input Cur- voltage is higher than 2.3V, discontinuous mode is active.
rent Monitor Amplifier. Connect this pin to VIN when not
GND (Pin 13, Exposed Pad Pin 39/Pin 16, Exposed Pad
in use. See Applications Information section for proper
Pin 39): Ground. Tie directly to local ground plane.
use of this pin.
VIN (Pin 34/Pin 38): Main Input Supply Pin. It must be
locally bypassed to ground.
INTVCC (Pin 35/Pin 1): Internal 6.35V Regulator Output.
Must be connected to the GATEVCC pin. INTVCC is powered
from EXTVCC when the EXTVCC voltage is higher than
6.4V, otherwise INTVCC is powered from VIN . Bypass this
pin to ground with a minimum 4.7μF ceramic capacitor.

8705f

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 LT8705
BLOCK DIAGRAM
VIN

RSENSE1

RSENSE

CSN CSP SWEN

DB1
BOOST1

+ TG1 CB1
D1
CSNIN – M1
(OPT)
+ A8 SW1
A7 A5 –
CSPIN + BUCK M2
– LOGIC
GATEVCC
VIN
BG1
IMON_IN GND

MODE BOOST CAPACITOR

CHARGE CONTROL

CLKOUT BG2

SYNC M3
OSC BOOST SW2
LOGIC D2
TG2 (OPT)
RT M4
+ CB2
A9 BOOST2

– DB2
2.5V CSPOUT
UV_INTVCC OT OI_IN OI_OUT
+
A6
RSENSE2
CSNOUT
– VOUT
STARTUP IMON_OUT
SS
–
AND FAULT
LOGIC FAULT_INT EA1
+

UV_LDO33 UV_VIN UV_GATEVCC 1.208V

+
RSHDN1
SHDN EA2
VIN
+ IMON_IN
–
RSHDN2 RFBIN1
FBIN
1.234V – +
EA3 RFBIN2
6.4V + – 1.205V
LDO 3.3V
EXTVCC REG LDO
– VIN REG
+ 1.207V
6.35V EN EN 6.35V INTERNAL EA4 RFBOUT1
LDO LDO SUPPLY2 FBOUT
REG REG –
INTVCC INTERNAL RFBOUT2
VC
SUPPLY1
LDO33 SRVO_IOUT SRVO_IIN SRVO_FBIN SRVO_FBOUT

8705 F01

Figure 1. Block Diagram

8705f

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LT8705
OPERATION
Refer to the Block Diagram (Figure 1) when reading the The GATEVCC pin directly powers the bottom MOSFET
following sections about the operation of the LT8705. drivers for switches M2 and M3. GATEVCC should always
be connected to INTVCC and should not be powered or
Main Control Loop connected to any other source. Undervoltage lock outs
The LT8705 is a current mode controller that provides an (UVLOs) monitoring INTVCC and GATEVCC disable the
output voltage above, equal to or below the input voltage. switching regulator when the pins are below 4.65V (typical).
The LTC proprietary topology and control architecture The LDO33 pin is available to provide power to external
employs a current-sensing resistor (RSENSE) in buck or components such as a microcontroller and/or to provide an
boost modes. The inductor current is controlled by the accurate bias voltage. Load current is limited to 17.25mA
voltage on the VC pin, which is the diode-AND of error (typical). As long as SHDN is high the LDO33 output is
amplifiers EA1-EA4. In the simplest form, where the output linearly regulated from the INTVCC pin and is not affected
is regulated to a constant voltage, the FBOUT pin receives by the INTVCC or GATEVCC UVLOs or the SWEN pin volt-
the output voltage feedback signal, which is compared to age. LDO33 will remain regulated as long as SHDN is high
the internal reference voltage by EA4. Low output voltages and sufficient voltage is available on INTVCC (typically >
would create a higher VC voltage, and thus more current 4.0V). An undervoltage lockout, monitoring LDO33, will
would flow into the output. Conversely, higher output volt- disable the switching regulator when LDO33 is below
ages would cause VC to drop, thus reducing the current 3.04V (typical).
fed into the output.
The LT8705 contains four error amplifiers (EA1-EA4) al- Start-Up
lowing it to regulate or limit the output current (EA1), input Figure 2 illustrates the start-up sequence for the LT8705.
current (EA2), input voltage (EA3) and/or output voltage The master shutdown pin for the chip is SHDN. When
(EA4). In a typical application, the output voltage might be driven below 0.4V the chip is disabled (chip off state) and
regulated using EA4, while the remaining error amplifiers quiescent current is minimal. Increasing the SHDN voltage
are monitoring for excessive input or output current or an can increase quiescent current but will not enable the chip
input undervoltage condition. In other applications, such until SHDN is driven above 1.234V (typical) after which
as a battery charger, the output current regulator (EA1) can the INTVCC and LDO33 regulators are enabled (switcher
facilitate constant current charging until a predetermined off state). External devices powered by the LDO33 pin can
voltage is reached where the output voltage (EA4) control become active at this time if enough voltage is available
would take over. on VIN or EXTVCC to raise INTVCC, and thus LDO33, to
an adequate voltage.
INTVCC/EXTVCC/GATEVCC/LDO33 Power
Starting up the switching regulator happens after SWEN
Power for the top and bottom MOSFET drivers, the LDO33 (switcher enable) is also driven above 1.206V (typical),
pin and most internal circuitry is derived from the INTVCC INTVCC and GATEVCC have risen above 4.81V (typical) and
pin. INTVCC is regulated to 6.35V (typical) from either the the LDO33 pin has risen above 3.08V (typical) (initialize
VIN or EXTVCC pin. When the EXTVCC pin is left open or state). The SWEN pin is not available in the TSSOP pack-
tied to a voltage less than 6.22V (typical), an internal low age. In this package the SWEN pin is internally connected
dropout regulator regulates INTVCC from VIN. If EXTVCC to INTVCC.
is taken above 6.4V (typical), another low dropout regula-
tor will instead regulate INTVCC from EXTVCC. Regulating Start-Up: Soft-Start of Switch Current
INTVCC from EXTVCC allows the power to be derived from
In the initialize state, the SS (soft-start) pin is pulled low
the lowest supply voltage (highest efficiency) such as the
to prepare for soft starting the regulator. If forced continu-
LT8705 switching regulator output (see INTVCC Regulators
ous mode is selected (MODE pin low), the part is put into
and EXTVCC Connection in the Applications Information
discontinuous mode during soft-start to prevent current
section for more details).
8705f

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 LT8705
OPERATION
TJUNCTION < 160°C
AND
SHDN < 1.184V OR SHDN > 1.234V AND VIN > 2.5V TYPICAL VALUES
VIN < 2.5V OR TYPICAL VALUES AND
TJUNCTION > 165°C (SWEN* < 1.184V OR (INTVCC AND GATEVCC < 4.65V)
OR LDO33 < 3.04V)

CHIP OFF SWITCHER OFF

• SWITCHER OFF • SWITCHER DISABLED
• LDOs OFF • INTVCC AND LDO33 OUTPUTS
ENABLED

SHDN > 1.234V AND VIN > 2.5V

AND SWEN* > 1.206V AND TYPICAL VALUES
(INTVCC AND GATEVCC > 4.81V) AND
LDO33 > 3.075V
INITIALIZE
• SS PULLED LOW FAULT
• FORCE DISCONTINOUS
MODE UNLESS Burst Mode
OPERATION SELECTED

SS < 50mV
FAULT DETECTED
SOFT-START
FAULT • SS CHARGES UP
• SS CHARGES UP • SWITCHER DISABLED
• SWITCHER ENABLED • CLKOUT DISABLED

SS > 1.6V AND

NO FAULT CONDITIONS
NORMAL MODE STILL DETECTED
• NORMAL OPERATION
• WHEN SS > 1.6V ... POST FAULT DELAY
FAULT FAULT
• CLKOUT ENABLED • SS SLOWLY DISCHARGES
• ENABLE FORCED
CONTINUOUS MODE
IF SELECTED SS < 50mV

*SWEN IS CONNECTED TO INTVCC IN THE TSSOP PACKAGE

FAULT = OVERVOLTAGE (IMON_IN OR IMON_OUT > 1.61V TYP)

8705 F02

Figure 2. Start-Up and Fault Sequence

from being drawn out of the output and forced into the is allowed to enter forced continuous mode (if MODE is
input. After SS has been discharged to less than 50mV, low) and an internal regulator pulls SS up quickly to ≅2.5V.
a soft-start of the switching regulator begins (soft-start Typical values for the external soft-start capacitor range
state). The soft-start circuitry provides for a gradual from 100nF to 1μF. A minimum of 100nF is recommended.
ramp-up of the inductor current by gradually allowing the
VC voltage to rise (refer to VC vs SS Voltage in the Typical Fault Conditions
Performance Characteristics). This prevents abrupt surges The LT8705 activates a fault sequence under certain op-
of current from being drawn out of the input power sup- erating conditions. If any of these conditions occur (see
ply. An integrated 100k resistor pulls the SS pin to ≅2.5V. Figure 2) the CLKOUT pin and internal switching activity
The ramp rate of the SS pin voltage is set by this 100k are disabled. At the same time, a timeout sequence com-
resistor and the external capacitor connected to this pin. mences where the SS pin is charged up to a minimum
Once SS gets to 1.6V, the CLKOUT pin is enabled, the part of 1.6V (fault detected state). The SS pin will continue
8705f

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LT8705
OPERATION
charging up to 2.5V and be held there in the case of a fault is turned on first. Inductor current is sensed by amplifier
event that persists. After the fault condition had ended and A5 while switch M2 is on. A slope compensation ramp is
SS is greater than 1.6V, SS will then slowly discharge to added to the sensed voltage which is then compared by A8
50mV (post fault delay state). This timeout period relieves to a reference that is proportional to VC. After the sensed
the part and other downstream power components from inductor current falls below the reference, switch M2 is
electrical and thermal stress for a minimum amount of turned off and switch M1 is turned on for the remainder
time as set by the voltage ramp rate on the SS pin. After of the cycle. Switches M1 and M2 will alternate, behaving
SS has discharged to < 50mV, the LT8705 will enter the like a typical synchronous buck regulator.
soft-start state and restart switching activity.
CLOCK

Power Switch Control

SWITCH M1
Figure 3 shows a simplified diagram of how the four SWITCH M2
power switches are connected to the inductor, VIN, VOUT
OFF
and ground. Figure 4 shows the regions of operation for SWITCH M3
ON
the LT8705 as a function of VOUT -VIN or switch duty cycle SWITCH M4

DC. The power switches are properly controlled so the IL

transfer between modes is continuous. 8705 F05

Figure 5. Buck Region (VIN >> VOUT)

VIN VOUT

The part will continue operating in the buck region over a

TG1 M1 M4 TG2
SW1
L
SW2
range of switch M2 duty cycles. The duty cycle of switch M2
in the buck region is given by:
BG1 M2 M3 BG2
 V 
DC(M2,BUCK) =  1– OUT  •100%
RSENSE  VIN 
8705 F03

As VIN and VOUT get closer to each other, the duty cycle
Figure 3. Simplified Diagram of the Output Switches
decreases until the minimum duty cycle of the converter
SWITCH
M3 DCMAX
in buck mode reaches DC(ABSMIN,M2,BUCK). If the duty
M1 ON, M2 OFF
cycle becomes lower than DC(ABSMIN,M2,BUCK) the part
BOOST REGION
PWM M3, M4 SWITCHES will move to the buck-boost region.
SWITCH
VOUT -VIN

0 BUCK/BOOST REGION 4-SWITCH PWM

M3 DCMIN
DC(ABSMIN,M2,BUCK) ≅ tON(M2,MIN) • f • 100%
SWITCH
M2 DCMIN
M4 ON, M3 OFF
where:
BUCK REGION
PWM M1, M2 SWITCHES
SWITCH tON(M2,MIN) is the minimum on-time for the synchronous
8705 F04 M2 DCMAX
switch in buck operation (260ns typical, see Electrical
Figure 4. Operating Regions vs VOUT-VIN Characteristics).
f is the switching frequency
Power Switch Control: Buck Region (VIN >> VOUT) When VIN is much higher than VOUT the duty cycle of
When VIN is significantly higher than VOUT, the part will switch M2 will increase, causing the M2 switch off-time
run in the buck region. In this region switch M3 is always to decrease. The M2 switch off-time should be kept above
off. Also, switch M4 is always on unless reverse current is 245ns (typical, see Electrical Characteristics) to maintain
detected while in Burst Mode operation or discontinuous steady-state operation, avoid duty cycle jitter, increased
mode. At the start of every cycle, synchronous switch M2 output ripple and reduction in maximum output current.
8705f

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 LT8705
OPERATION
Power Switch Control: Buck-Boost (VIN ≅ VOUT) Power Switch Control: Boost Region (VIN << VOUT)
When VIN is close to VOUT, the controller enters the buck- When VOUT is significantly higher than VIN, the part will
boost region. Figure 6 shows typical waveforms in this run in the boost region. In this region switch M1 is always
region. Every cycle, if the controller starts with switches M2 on and switch M2 is always off. At the start of every
and M4 turned on, the controller first operates as if in the cycle, switch M3 is turned on first. Inductor current is
buck region. When A8 trips, switch M2 is turned off and sensed by amplifier A5 while switch M3 is on. A slope
M1 is turned on until the middle of the clock cycle. Next, compensation ramp is added to the sensed voltage which
switch M4 turns off and M3 turns on. The LT8705 then is then compared (A9) to a reference that is proportional
operates as if in boost mode until A9 trips. Finally switch to VC. After the sensed inductor current rises above the
M3 turns off and M4 turns on until the end of the cycle. reference voltage, switch M3 is turned off and switch M4
is turned on for the remainder of the cycle. Switches M3
If the controller starts with switches M1 and M3 turned
and M4 will alternate, behaving like a typical synchronous
on, the controller first operates as if in the boost region.
boost regulator.
When A9 trips, switch M3 is turned off and M4 is turned
on until the middle of the clock cycle. Next, switch M1 The part will continue operating in the boost region over
turns off and M2 turns on. The LT8705 then operates as a range of switch M3 duty cycles. The duty cycle of
if in buck mode until A8 trips. Finally switch M2 turns off switch M3 in the boost region is given by:
and M1 turns on until the end of the cycle.
 V 
DC(M3,BOOST) =  1– IN  •100%
CLOCK
 VOUT 
SWITCH M1
As VIN and VOUT get closer to each other, the duty cycle
SWITCH M2 decreases until the minimum duty cycle of the converter
in boost mode reaches DC(ABSMIN,M3,BOOST). If the duty
SWITCH M3
cycle becomes lower than DC(ABSMIN,M3,BOOST) the part
SWITCH M4 will move to the buck-boost region:
IL
8705 F06a
DC(ABSMIN,M3,BOOST) ≅ tON(M3,MIN) • f • 100%
(6a) Buck-Boost Region (VIN ≥ VOUT) where:
tON(M3,MIN) is the minimum on-time for the main switch
CLOCK in boost operation (265ns typical, see Electrical Char-
SWITCH M1 acteristics)
SWITCH M2 f is the switching frequency
SWITCH M3
CLOCK

SWITCH M4 ON
SWITCH M1
OFF
IL SWITCH M2
8705 F06b
SWITCH M3
(6b) Buck-Boost Region (VIN ≤ VOUT)
SWITCH M4
Figure 6. Buck-Boost Region
IL
8705 F07

Figure 7. Boost Region (VIN << VOUT)

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LT8705
OPERATION
When VOUT is much higher than VIN the duty cycle of age current is delivered to the output. During soft-start,
switch M3 will increase, causing the M3 switch off-time when the SS pin is below 1.6V, the part will be forced
to decrease. The M3 switch off-time should be kept above into discontinuous mode to prevent pulling current from
245ns (typical, see Electrical Characteristics) to maintain the output to the input. After SS rises above 1.6V, forced
steady-state operation, avoid duty cycle jitter, increased continuous mode will be enabled.
output ripple and reduction in maximum output current.
Voltage Regulation Loops
Light Load Current Operation (MODE Pin)
The LT8705 provides two constant-voltage regulation
Under light current load conditions, the LT8705 can be set
loops, one for output voltage and one for input voltage.
to operate in discontinuous mode, forced continuous mode,
A resistor divider between VOUT, FBOUT and GND senses
or Burst Mode operation. To select forced continuous mode, the output voltage. As with traditional voltage regulators,
tie the MODE pin to a voltage below 0.4V (i.e., ground). To when FBOUT rises near or above the reference voltage of
select discontinuous mode, tie MODE to a voltage above EA4 (1.207V typical, see Block Diagram), the VC voltage
2.3V (i.e., LDO33). To select Burst Mode operation, float is reduced to command the amount of current that keeps
the MODE pin or tie it between 1.0V and 1.7V. VOUT regulated to the desired voltage.
Discontinuous Mode: When the LT8705 is in discontinu- The input voltage can also be sensed by connecting a
ous mode, synchronous switch M4 is held off whenever resistor divider between VIN, FBIN and GND. When the
reverse current in the inductor is detected. This is to prevent FBIN voltage falls near or below the reference voltage of
current draw from the output and/or feeding current to the EA3 (1.205V typical, see Block Diagram), the VC voltage is
input supply. Under very light loads, the current compara- reduced to also reduce the input current. For applications
tor may also remain tripped for several cycles and force with a high input source impedance (i.e., a solar panel), the
switches M1 and M3 to stay off for the same number of input voltage regulation loop can prevent the input voltage
cycles (i.e., skipping pulses). Synchronous switch M2 will from becoming too low under high output load conditions.
remain on during the skipped cycles, but since switch M4 For applications with a lower input source impedance (i.e.,
is off, the inductor current will not reverse. batteries and voltage supplies), the FBIN pin can be used
Burst Mode Operation: Burst Mode operation sets a to stop switching activity when the input power supply
VC level, with about 25mV of hysteresis, below which voltage gets too low for proper system operation. See the
switching activity is inhibited and above which switching Applications Information section for more information
activity is re-enabled. A typical example is when, at light about setting up the voltage regulation loops.
output currents, VOUT rises and forces the VC pin below the
threshold that temporarily inhibits switching. After VOUT Current Monitoring and Regulation
drops slightly and VC rises ~25mV the switching is resumed, The LT8705 provides two constant-current regulation
initially in the buck-boost region. Burst Mode operation loops, one for input current and one for output current. A
can increase efficiency at light load currents by eliminating sensing resistor close to the input capacitor, sensed by
unnecessary switching activity and related power losses. CSPIN and CSNIN, monitors the input current. A current,
Burst Mode operation handles reverse-current detection linearly proportional to the sense voltage (VCSPIN-VCSNIN),
similar to discontinuous mode. The M4 switch is turned is forced out of the IMON_IN pin and into an external re-
off when reverse current is detected. sistor. The resulting voltage VIMON_IN is therefore linearly
Forced Continuous Mode: The forced continuous mode proportional to the input current. Similarly, a sensing
allows the inductor current to reverse directions without resistor close to the output capacitor, and sensed by
any switches being forced “off” to prevent this from hap- CSPOUT and CSNOUT will monitor the output current and
pening. At very light load currents the inductor current generate a voltage VIMON_OUT that is linearly proportional
will swing positive and negative as the appropriate aver- to the output current.
8705f

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 LT8705
OPERATION
When the input or output current causes the respective its regulation voltage (≅1.2V typical). The SRVO pins can
IMON_IN or IMON_OUT voltage to rise near or above therefore be used as indicators of when their respective
1.208V (typical), the VC pin voltage will be pulled down to feedback loops are active. For example, the SRVO_FBOUT
maintain the desired maximum input and/or output current pin pulls low when FBOUT rises to within 29mV (typical, see
(see EA1 and EA2 on the Block Diagram). The input current Electrical Characteristics) of its regulation voltage (1.207V
limit function prevents overloading the DC input source, typical). The pull-down turns off after FBOUT falls to more
while the output current limit provides a building block than 44mV (typical) lower than its regulation voltage.
for battery charger or LED driver applications. It can also As another example, the SRVO_IOUT pin can be read to
serve as short-circuit protection for a constant-voltage determine when the output current has nearly reached its
regulator. See the Applications Information section for more predetermined limit. A logic “1” on SRVO_IOUT indicates
information about setting up the current regulation loops. that the output current has not reached the current limit
and a logic “0” indicates that it has.
SRVO Pins
The QFN package has four open-drain SRVO pins: CLKOUT and Temperature Sensing
SRVO_FBIN, SRVO_FBOUT, SRVO_IIN, SRVO_IOUT. The CLKOUT pin toggles at the LT8705’s internal clock
Place pull-up resistors from the desired SRVO pin(s) to a frequency whether the internal clock is synchronized to an
power supply less than 30V (i.e., the LDO33 pin) to enable external source or is free-running based on the external RT
reading of their logic states. The SRVO_FBOUT, SRVO_IIN resistor. The CLKOUT pin can be used to synchronize other
and SRVO_IOUT pins are pulled low when their associ- devices to the LT8705’s switching frequency. Also, the duty
ated error amp (EA4, EA2, EA1) input voltages are near cycle of CLKOUT is proportional to the die temperature
or greater than their regulation voltages (≅1.2V typical). and can be used to monitor the die for thermal issues.
SRVO_FBIN is pulled low when FBIN is near or lower than

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LT8705
APPLICATIONS INFORMATION
The first page shows a typical LT8705 application circuit. where fOSC is in kHz and RT is in kΩ. Conversely, RT (in
After the switching frequency is selected, external compo- kΩ) can be calculated from the desired frequency (in
nent selection continues with the selection of RSENSE and kHz) using:
the inductor value. Next, the power MOSFETs are selected.
 43,750 
Finally, CIN and COUT are selected. The following examples RT =  – 1 kΩ
and equations assume continuous conduction mode un-  fOSC 
less otherwise specified. The circuit can be configured
for operation up to an input and/or output voltage of 80V. SYNC Pin and Clock Synchronization
Operating Frequency Selection The operating frequency of the LT8705 can be synchronized
to an external clock source. To synchronize to the external
The LT8705 uses a constant frequency architecture source, simply provide a digital clock signal into the SYNC
between 100kHz and 400kHz. The frequency can be set pin. The LT8705 will operate at the SYNC clock frequency.
using the internal oscillator or can be synchronized to an
external clock source. Selection of the switching frequency The duty cycle of the SYNC signal must be between 20%
is a trade-off between efficiency and component size. and 80% for proper operation. Also, the frequency of the
Low frequency operation increases efficiency by reducing SYNC signal must meet the following two criteria:
MOSFET switching losses, but requires more inductance 1. SYNC may not toggle outside the frequency range of
and/or capacitance to maintain low output ripple voltage. 100kHz to 400KHz unless it is stopped low to enable
For high power applications, consider operating at lower the free-running oscillator.
frequencies to minimize MOSFET heating from switching
losses. The switching frequency can be set by placing an 2. The SYNC pin frequency can always be higher than the
appropriate resistor from the RT pin to ground and tying free-running oscillator set frequency, fOSC, but should
the SYNC pin low. The frequency can also be synchronized not be less than 25% below fOSC.
to an external clock source driven into the SYNC pin. The After SYNC begins toggling, it is recommended that
following sections provide more details. switching activity is stopped before the SYNC pin stops
toggling. Excess inductor current can result when SYNC
Internal Oscillator stops toggling as the LT8705 transitions from the external
The operating frequency of the LT8705 can be set using SYNC clock source to the internal free-running oscillator
the internal free-running oscillator. When the SYNC pin clock. Switching activity can be stopped by driving either
is driven low (<0.5V), the frequency of operation is set the SWEN or SHDN pin low.
by the value of a resistor from the RT pin to ground. An
internally trimmed timing capacitor resides inside the IC. CLKOUT Pin and Clock Synchronization
The oscillator frequency is calculated using the following The CLKOUT pin can drive up to 200pF and toggles at the
formula: LT8705’s internal clock frequency whether the internal clock
is synchronized to the SYNC pin or is free-running based
 43,750 
fOSC =  kHz on the external RT resistor. The rising edge of CLKOUT is
 R T +1  approximately 180° out of phase from the internal clock’s

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rising edge or the SYNC pin’s rising edge if it is toggling. a reduction of maximum inductor current in the boost
CLKOUT toggles only in normal mode (see Figure 2). region, and an increase of the maximum inductor current
The CLKOUT pin can be used to synchronize other de- in the buck region. For example, refer to the Maximum
vices to the LT8705’s switching frequency. For example, Inductor Current Sense Voltage vs Duty Cycle graph in the
the CLKOUT pin can be tied to the SYNC pin of another Typical Performance Characteristics section. The graph
LT8705 regulator which will operate approximately 180° shows that, with VC at its maximum voltage, the maximum
inductor sense voltage VRSENSE is between 78mV and
out of phase of the master LT8705 due to the CLKOUT
117mV depending on the duty cycle. It also shows that
phase shift. The frequency of the master LT8705 can be
the maximum inductor valley current in the buck region
set by the external RT resistor or by toggling the SYNC
pin. CLKOUT will begin oscillating after the master LT8705 is 86mV increasing to ~130mV at higher duty cycles.
enters normal mode (see Figure 2). Note that the RT pin RSENSE Selection and Maximum Current
of the slave LT8705 must have a resistor tied to ground.
In general, use the same value RT resistor for all of the The RSENSE resistance must be chosen properly to achieve
synchronized LT8705s. the desired amount of output current. Too much resistance
can limit the output current below the application require-
The duty cycle of CLKOUT is proportional to the die tem-
ments. Start by determining the maximum allowed RSENSE
perature and can be used to monitor the die for thermal resistance in the boost region, RSENSE(MAX,BOOST). Follow
issues. See the Junction Temperature Measurement section this by finding the maximum allowed RSENSE resistance in
for more information. the buck region, RSENSE(MAX,BUCK). The selected RSENSE
resistance must be smaller than both.
Inductor Current Sensing and Slope Compensation
Boost Region: In the boost region, the maximum output
The LT8705 operates using inductor current mode control.
current capability is the least when VIN is at its minimum
As described previously in the Power Switch Control sec-
and VOUT is at its maximum. Therefore RSENSE must be
tion, the LT8705 measures the peak of the inductor current
chosen to meet the output current requirements under
waveform in the boost region and the valley of the inductor
these conditions.
current waveform in the buck region. The inductor current
is sensed across the RSENSE resistor with pins CSP and Start by finding the boost region duty cycle when VIN is
CSN. During any given cycle, the peak (boost region) or minimum and VOUT is maximum using:
valley (buck region) of the inductor current is controlled
 VIN(MIN) 
by the VC pin voltage. DC(MAX,M3,BOOST) ≅  1–  •100%
Slope compensation provides stability in constant-  VOUT(MAX) 
frequency current mode control architectures by prevent-
ing subharmonic oscillations at high duty cycles. This For example, an application with a VIN range of 12V to
is accomplished internally by adding a compensating 48V and VOUT set to 36V will have:
ramp to the inductor current signal in the boost region,  12V 
DC(MAX,M3,BOOST) ≅  1– •100% = 67%
or subtracting a ramp from the inductor current signal  36V 
in the buck region. At higher duty cycles, this results in

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Referring to the Maximum Inductor Current Sense Volt- After the maximum ripple current is known, the maximum
age graph in the Typical Performance Characteristics allowed RSENSE in the boost region can be calculated as
section, the maximum RSENSE voltage at 67% duty cycle follows:
is ≅93mV, or: RSENSE(MAX,BOOST) =
VRSENSE(MAX,BOOST, MAX) ≅93mV
2 • VRSENSE(MAX,BOOST,MAX) • VIN(MIN)
for VIN = 12V, VOUT = 36V. Ω
(2 •IOUT(MAX,BOOST) • VOUT(MIN) ) + ( ∆IL(MAX,BOOST) • VIN(MIN) )
Next, the inductor ripple current in the boost region must
be determined. If the main inductor L is not known, the where VRSENSE(MAX,BOOST,MAX) is the maximum inductor
maximum ripple current ∆IL(MAX,BOOST) can be estimated current sense voltage as discussed in the previous section.
by choosing ∆IL(MAX,BOOST) to be 30% to 50% of the Using values from the previous examples:
maximum inductor current in the boost region as follows:
2 • 93mV •12
VOUT(MAX) •IOUT(MAX,BOOST) RSENSE(MAX,BOOST) = = 12.4mΩ
∆IL(MAX,BOOST) ≅ A ( 2 • 2A • 36V ) + ( 3A •12V )
 100% 
VIN(MIN) •  – 0.5
 %Ripple  Buck Region: In the buck region, the maximum output cur-
rent capability is the least when operating at the minimum
where: duty cycle. This is because the slope compensation ramp
IOUT(MAX,BOOST) is the maximum output load current increases the maximum RSENSE voltage with increasing
required in the boost region duty cycle. The minimum duty cycle for buck operation
can be calculated using:
%Ripple is 30% to 50%
DC(MIN,M2,BUCK) ≅ tON(M2,MIN) • f • 100%
For example, using VOUT(MAX) = 36V, VIN(MIN) = 12V,
IOUT(MAX,BOOST) = 2A and %Ripple = 40% we can estimate: where tON(M2,MIN) is 260ns (typical value, see Electrical
Characteristics)
36V • 2A
∆IL(MAX,BOOST) ≅ = 3A
 100%  Before calculating the maximum RSENSE resistance,
12V •  – 0.5
 40%  however, the inductor ripple current must be determined.
If the main inductor L is not known, the ripple current
Otherwise, if the inductor value is already known then ∆IL(MIN,BUCK) can be estimated by choosing ∆IL(MIN,BUCK)
∆IL(MAX,BOOST) can be more accurately calculated as to be 10% of the maximum inductor current in the buck
follows: region as follows:
 DC(MAX,M3,BOOST)  IOUT(MAX,BUCK)
 100%  • VIN(MIN) ∆IL(MIN,BUCK) ≅ A
 100% 
∆IL(MAX,BOOST) = A  – 0.5
f •L 10%

where: where:
DC(MAX,M3,BOOST) is the maximum duty cycle percent- IOUT(MAX,BUCK) is the maximum output load current
age in the boost region as calculated previously. required in the buck region.
f is the switching frequency
L is the inductance of the main inductor

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If the inductor value is already known then ∆IL(MIN,BUCK) constant (frequency = 350kHz, inductance = 10μH, RSENSE =
can be calculated as follows: 10mΩ). This graph is normalized and accounts for changes
in maximum current due to the slope compensation ramps
 DC(MIN,M2,BUCK) 
  • VOUT(MIN) and the effects of changing ripple current. The curve is
100%
∆IL(MIN,BUCK ) = A theoretical, but can be used as a guide to predict relative
f •L changes in maximum output and inductor current over a
where: range of VIN/VOUT voltages.
DC(MIN,M2,BUCK) is the minimum duty cycle percentage Reverse Current Limit
in the buck region as calculated previously.
When the forced continuous mode is selected (MODE
f is the switching frequency pin low), inductor current is allowed to reverse directions
L is the inductance of the main inductor and flow from the VOUT side to the VIN side. This can lead
to current sinking from the output and being forced into
After the inductor ripple current is known, the maximum the input. The reverse current is at a maximum magni-
allowed RSENSE in the buck region can be calculated as tude when VC is lowest. The graph of Minimum Inductor
follows: Current Sense Voltage in FCM in the Typical Performance
2 • 86mV Characteristics section can help to determine the maximum
RSENSE(MAX,BUCK) =
(2 •IOUT(MAX,BUCK) ) – ∆IL(MIN,BUCK) reverse current capability.

Inductor Selection
Final RSENSE Value: The final RSENSE value should be
lower than both RSENSE(MAX,BOOST) and RSENSE(MAX,BUCK). For high efficiency, choose an inductor with low core
A margin of 30% or more is recommended. loss, such as ferrite. Also, the inductor should have low
DC resistance to reduce the I2R losses, and must be able
Figure 8 shows approximately how the maximum output
to handle the peak inductor current without saturating. To
current and maximum inductor current would vary with
minimize radiated noise, use a toroid, pot core or shielded
VIN/VOUT while all other operating parameters remain
bobbin inductor.
1.0
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
0.8
of smaller inductor and capacitor values. The following
NORMALIZED CURRENT

MAXIMUM
INDUCTOR sections discuss several criteria to consider when choosing
0.6 CURRENT MAXIMUM
OUTPUT
an inductor value. For optimal performance, choose an
0.4
CURRENT inductor that meets all of the following criteria.

0.2
Inductor Selection: Adequate Load Current in the
Boost Region
0
0.1 1 10
Small value inductors result in increased ripple currents
VIN/VOUT (V/V) and thus, due to the limited peak inductor current, decrease
8705 F08
the maximum average current that can be provided to the
Figure 8. Currents vs VIN/VOUT Ratio load (IOUT ) while operating in the boost region.

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In order to provide adequate load current at low VIN volt- In the boost region, if VOUT can be greater than twice VIN,
ages in the boost region, L should be at least: calculate L(MIN2,BOOST) as follows:
L(MIN1,BOOST) ≅ L(MIN2,BOOST) =

 DC(MAX,M3,BOOST)    VIN(MIN) • VOUT(MAX)  

VIN(MIN) •   VOUT(MAX) – 
 100%    •RSENSE
  VOUT(MAX) – VIN(MIN)  
 VRSENSE(MAX,BOOST,MAX) IOUT(MAX) • VOUT(MAX)  H
2• f • –  0.08 • f
 RSENSE VIN(MIN) 
In the buck region, if VIN can be greater than twice VOUT,
where: calculate L(MIN1,BUCK) as follows:
DC(MAX,M3,BOOST) is the maximum duty cycle per- L (MIN1,BUCK) =
centage of the M3 switch (see RSENSE Selection and
Maximum Current section).  VOUT(MAX) 
VIN(MAX) •  1–  • R SENSE
f is the switching frequency  VIN(MAX) – VOUT(MIN) 
H
VRSENSE(MAX,BOOST,MAX) is the maximum current sense 0.08 • f
voltage in the boost region at maximum duty cycle (see
RSENSE Selection and Maximum Current section) Inductor Selection: Maximum Current Rating
Negative values of L(MIN1,BOOST) indicate that the output The inductor must have a rating greater than its peak
load current IOUT can’t be delivered in the boost region operating current to prevent inductor saturation resulting
because the inductor current limit is too low. If L(MIN1,BOOST) in efficiency loss. The peak inductor current in the boost
is too large or is negative, consider reducing the RSENSE region is:
resistor value to increase the inductor current limit.
VOUT(MAX)
IL(MAX,BOOST) ≅ IOUT(MAX) •
Inductor Selection: Subharmonic Oscillations VIN(MIN)
The LT8705’s internal slope compensation circuits will
prevent subharmonic oscillations that can otherwise oc-
  DC(MAX,M3,BOOST  
 VIN(MIN) •  100%  
cur when VIN/VOUT is less than 0.5 or greater than 2. The 
+ A
slope compensation circuits will prevent these oscillations  2 •L • f 
provided that the inductance exceeds a minimum value  
 
(see the earlier section Inductor Current Sensing and Slope
Compensation for more information). Choose an induc- where DC(MAX,M3,BOOST) is the maximum duty cycle
tance greater than all of the relevant L(MIN) limits discussed percentage of the M3 switch (see RSENSE Selection and
below. Negative results can be interpreted as zero. Maximum Current section).

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The peak inductor current when operating in the buck It is very important to consider power dissipation when
region is: selecting power MOSFETs. The most efficient circuit will
IL(MAX,BUCK) ≅IOUT(MAX) use MOSFETs that dissipate the least amount of power.
Power dissipation must be limited to avoid overheating
that might damage the devices. For most buck-boost ap-
  DC(MAX,M2,BUCK  
 VOUT(MIN) •  plications the M1 and M3 switches will have the highest
100%  
+ A power dissipation where M2 will have the lowest unless
 2 •L • f  the output becomes shorted. In some cases it can be
  helpful to use two or more MOSFETs in parallel to reduce
 
power dissipation in each device. This is most helpful when
where DC(MAX,M2,BUCK) is the maximum duty cycle per- power is dominated by I2R losses while the MOSFET is
centage of the M2 switch in the buck region given by: “on”. The additional capacitance of connecting MOSFETs
in parallel can sometimes slow down switching edge rates
 VOUT(MIN)  and consequently increase total switching power losses.
DC (MAX,M2,BUCK ) ≅  1–  • 100%
 VIN(MAX)  The following sections provide guidelines for calculating
power consumption of the individual MOSFETs. From a
Note that the inductor current can be higher during load known power dissipation, the MOSFET junction tempera-
transients and if the load current exceeds the expected ture can be obtained using the following formula:
maximum IOUT(MAX). It can also be higher during start-
up if inadequate soft-start capacitance is used or during TJ = TA + P • RTH(JA)
output shorts. Consider using the output current limiting where:
to prevent the inductor current from becoming excessive.
TJ is the junction temperature of the MOSFET
Output current limiting is discussed later in the Input/
Output Current Monitoring and Limiting section. Care- TA is the ambient air temperature
ful board evaluation of the maximum inductor current P is the power dissipated in the MOSFET
is recommended.
RTH(JA) is the MOSFET’s thermal resistance from the
Power MOSFET Selection and Efficiency junction to the ambient air. Refer to the manufacturer’s
Considerations data sheet.
The LT8705 requires four external N-channel power MOS- RTH(JA) normally includes the RTH(JC) for the device plus
FETs, two for the top switches (switches M1 and M4, shown the thermal resistance from the case to the ambient tem-
in Figure 3) and two for the bottom switches (switches perature RTH(JC). Compare the calculated value of TJ to
M2 and M3, shown in Figure 3). Important parameters for the manufacturer’s data sheets to help choose MOSFETs
the power MOSFETs are the breakdown voltage, VBR,DSS, that will not overheat.
threshold voltage, VGS,TH, on-resistance, RDS(ON), reverse- Switch M1: The power dissipation in switch M1 comes
transfer capacitance, CRSS (gate-to-drain capacitance), and from two primary components: (1) I2R power when the
maximum current, IDS(MAX). The gate drive voltage is set switch is fully turned “on” and inductor current is flowing
by the 6.35V GATEVCC supply. Consequently, logic-level through the drain to source connections and (2) power
threshold MOSFETs must be used in LT8705 applications.

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dissipated while the switch is turning “on” or “off”. As the 2.0

switch turns “on” and “off” a combination of high current

ρτ NORMALIZED ON-RESISTANCE (Ω)

and high voltage causes high power dissipation in the 1.5
MOSFET. Although the switching times are short, the aver-
age power dissipation can still be significant and is often
1.0
the dominant source of power in the MOSFET. Depending
on the application, the maximum power dissipation in
the M1 switch can happen in the buck region when VIN 0.5

is highest, VOUT is highest, and switching power losses

are greatest or in the boost region when VIN is smallest, 0
VOUT is highest and M1 is always on. Switch M1 power –50 0 50 100 150
JUNCTION TEMPERATURE (°C)
consumption can be approximated as: 8705 F09

PM1 = PI2R +PSWITCHING Figure 9. Normalized MOSFET RDS(ON) vs Temperature

 V 
2 
≅ OUT
•I •RDS(ON) • ρτ  Switch M2: In most cases the switching power dissipa-
  VIN OUT   tion in the M2 switch is quite small and I2R power losses
dominate. I2R power is greatest in the buck region where
+ ( VIN •IOUT • f • tRF1) W the switch operates as the synchronous rectifier. Higher
VIN and lower VOUT causes the M2 switch to be “on” for
where: the most amount of time, leading to the highest power
consumption. The M2 switch power consumption in the
the PSWITCHING term is 0 in the boost region buck region can be approximated as:
tRF1 is the average of the SW1 pin rise and fall times.
 V –V 
Typical values are 20ns to 40ns depending on the P(M2,BUCK) ≅  IN OUT •IOUT(MAX)2 •RDS(ON) • ρτ  W
MOSFET capacitance and VIN voltage.  VIN 
ρτ is a normalization factor (unity at 25°C) accounting Switch M3: Switch M3 operates in the boost and buck-
for the significant variation in MOSFET on-resistance boost regions as a control switch. Similar to the M1
with temperature, typically about 0.4%/°C, as shown switch, the power dissipation comes from I2R power and
in Figure 9. For a maximum junction temperature of switching power. The maximum power dissipation is when
125°C, using a value ρτ = 1.5 is reasonable. VIN is the lowest and VOUT is the highest. The following
Since the switching power (PSWITCHING) often dominates,
look for MOSFETs with lower CRSS or consider operating
at a lower frequency to minimize power loss and increase
efficiency.

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expression approximates the power dissipation in the M3 and capacitance, ringing can occur on SW1 or SW2 when
switch under those conditions: low capacitance MOSFETs are turned on/off too quickly.
PM3 = PI2R + PSWITCHING ≅ The ringing can be of greatest concern when operating
the MOSFETs or the LT8705 near the rated voltage limits.
 ( VOUT – VIN ) • VOUT  Additional gate resistance slows the switching speed,
 •IOUT 2 • R DS(ON) • ρ τ  minimizing the ringing.
 VIN2 
Excessive gate resistance can have two negative side
 t  effects on performance:
+  VOUT 2 •IOUT • f • RF2  W
 VIN  1. Slowing the switch transition times can also increase
power dissipation in the switch. This is described above
where the total power is 0 in the buck region. in the Switch M1 and Switch M3 sections.
tRF2 is the average of the SW2 pin rise and fall times and, 2. Capacitive coupling from the SW1 or SW2 pin to the
similar to tRF1, is typically 20ns to 40ns. switch gate node can turn it on when it’s supposed to
As with the M1 switch, the switching power (PSWITCHING) be off, thus increasing power dissipation. With too much
often dominates. Look for MOSFETs with lower CRSS or gate resistance, this would most commonly happen to
consider operating at a lower frequency to minimize power the M2 switch when SW1 is rising.
loss and increase efficiency. Careful board evaluation should be performed when
Switch M4: In most cases the switching power dissipa- optimizing the gate resistance values. SW1 and SW2 pin
tion in the M4 switch is quite small and I2R power losses ringing can be affected by the inductor current levels,
dominate. I2R power is greatest in the boost region where therefore board evaluation should include measurements
the switch operates as the synchronous rectifier. Lower at a wide range of load currents. When performing PCB
VIN and higher VOUT increases the inductor current for a measurements of the SW1 and SW2 pins, be sure to use a
given IOUT, leading to the highest power consumption. very short ground post from the PCB ground to the scope
The M4 switch power consumption in the boost region probe ground sleeve in order to minimize false inductive
can be approximated as: voltages readings.
V 
P(M4,BOOST) ≅  OUT •IOUT 2 • ρτ •RDS(ON)  W CIN and COUT Selection
 VIN 
Input and output capacitance is necessary to suppress
Gate Resistors: In some cases it can be beneficial to add voltage ripple caused by discontinuous current moving in
1Ω to 10Ω of resistance between some of the NMOS gate and out of the regulator. A parallel combination of capaci-
pins and their respective gate driver pins on the LT8705 tors is typically used to achieve high capacitance and low
(i.e., TG1, BG1, TG2, BG2). Due to parasitic inductance ESR (equivalent series resistance). Dry tantalum, special

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polymer, aluminum electrolytic and ceramic capacitors are output ripple voltage. The steady-state output ripple due
all available in surface mount packages. Capacitors with to charging and discharging the bulk output capacitance
low ESR and high ripple current ratings, such as OS-CON is given by the following equations:
and POSCAP are also available.
IOUT • ( VOUT – VIN )
Ceramic capacitors should be placed near the regulator ∆V(BOOST,CAP ) ≅ V for VOUT > VIN
COUT • VIN • f
input and output to suppress high frequency switching
spikes. A ceramic capacitor, of at least 1µF, should also  V 
be placed from VIN to GND as close to the LT8705 pins VOUT •  1– OUT 
 VIN 
as possible. Due to their excellent low ESR characteristics ∆V(BUCK,CAP) ≅ V for VOUT < VIN
ceramic capacitors can significantly reduce input ripple 8 •L • f 2 •COUT
voltage and help reduce power loss in the higher ESR bulk
capacitors. X5R or X7R dielectrics are preferred, as these The maximum output ripple due to the voltage drop across
materials retain their capacitance over wide voltage and the ESR is approximately:
temperature ranges. Many ceramic capacitors, particularly VOUT(MAX) •IOUT(MAX)
0805 or 0603 case sizes, have greatly reduced capacitance ∆V(BOOST,ESR) ≅ •ESR
VIN(MIN)
at the desired operating voltage.
Input Capacitance: Discontinuous input current is highest As with CIN, multiple capacitors placed in parallel may
in the buck region due to the M1 switch toggling on and off. be needed to meet the ESR and RMS current handling
Make sure that the CIN capacitor network has low enough requirements.
ESR and is sized to handle the maximum RMS current.
For buck operation, the input RMS current is given by: Schottky Diode (D1, D2) Selection

V VIN The Schottky diodes, D1 and D2, shown in Figure 1, con-

IRMS ≅IOUT(MAX) • OUT • –1 duct during the dead time between the conduction of the
VIN VOUT
power MOSFET switches. They are intended to prevent
the body diodes of synchronous switches M2 and M4
This formula has a maximum at VIN = 2VOUT, where
from turning on and storing charge. For example, D2
IRMS = IOUT(MAX)/2. This simple worst-case condition
significantly reduces reverse-recovery current between
is commonly used for design because even significant
switch M4 turn-off and switch M3 turn-on, which improves
deviations do not offer much relief.
converter efficiency, reduces switch M3 power dissipation
The maximum input ripple due to the voltage drop across and reduces noise in the inductor current sense resistor
the ESR is approximately: (RSENSE) when M3 turns on. In order for the diode to be
VIN(MAX) •IOUT(MAX) effective, the inductance between it and the synchronous
∆V(BUCK,ESR) ≅ •ESR switch must be as small as possible, mandating that these
VOUT(MIN) components be placed adjacently.
Output Capacitance: The output capacitance (COUT ) is For applications with high input or output voltages (typi-
necessary to reduce the output voltage ripple caused by cally >40V) avoid Schottky diodes with excessive reverse-
discontinuities and ripple in the output and load currents. leakage currents particularly at high temperatures. Some
The effects of ESR and the bulk capacitance must be ultralow VF diodes will trade off increased high temperature
considered when choosing the right capacitor for a given leakage current for reduced forward voltage. Diode D1

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can have a reverse voltage up to VIN and D2 can have Boost Diodes DB1 and DB2: Although Schottky diodes
a reverse voltage up to VOUT. The combination of high have the benefit of low forward voltage drops, they can
reverse voltage and current can lead to self heating of exhibit high reverse current leakage and have the potential
the diode. Besides reducing efficiency, this can increase for thermal runaway under high voltage and temperature
leakage current which increases temperatures even further. conditions. Silicon diodes are thus recommended for
Choose packages with lower thermal resistance (θJA) to diodes DB1 and DB2. Make sure that DB1 and DB2 have
minimize self heating of the diodes. reverse breakdown voltage ratings higher than VIN(MAX)
and VOUT(MAX) and have less than 1mA of reverse leakage
Topside MOSFET Driver Supply (CB1, DB1, CB2, DB2) current at the maximum operating junction temperature.
The top MOSFET drivers (TG1 and TG2) are driven digitally Make sure that the reverse leakage current at high op-
between their respective SW and BOOST pin voltages. erating temperatures and voltages won’t cause thermal
The BOOST voltages are biased from floating bootstrap runaway of the diode.
capacitors CB1 and CB2, which are normally recharged In some cases it is recommended that up to 5Ω of resis-
through external silicon diodes DB1 and DB2 when the tance is placed in series with DB1 and DB2. The resistors
respective top MOSFET is turned off. The capacitors are reduce surge currents in the diodes and can reduce ringing
charged to about 6.3V (about equal to GATEVCC) forcing the at the SW and BOOST pins of the IC. Since SW pin ringing
VBOOST1-SW1 and VBOOST2-SW2 voltages to be about 6.3V. is highly dependent on PCB layout, SW pin edge rates and
The boost capacitors CB1 and CB2 need to store about 100 the type of diodes used, careful measurements directly
times the gate charge required by the top switches M1 and at the SW pins of the IC are recommended. If required, a
M4. In most applications, a 0.1μF to 0.47μF, X5R or X7R single resistor can be placed between GATEVCC and the
dielectric capacitor is adequate. The bypass capacitance common anodes of DB1 and DB2 (as in the front page
from GATEVCC to GND should be at least ten times the application) or by placing separate resistors between the
CB1 or CB2 capacitance. cathodes of each diode and the respective BOOST pins.
Boost Capacitor Charge Control Block: When the LT8705 Excessive resistance in series with DB1 and DB2 can reduce
operates exclusively in the buck or boost region, one of the BOOST-SW capacitor voltage when the M2 or M3
the top MOSFETS, M1 or M4, can be constantly on. This on-times are very short and should be avoided.
prevents the respective bootstrap capacitor, CB1 or CB2,
from being recharged through the silicon diode, DB1 or Output Voltage
DB2. The Boost Capacitor Charge Control block (see Fig- The LT8705 output voltage is set by an external feedback
ure 1) keeps the appropriate BOOST pin charged in these resistive divider carefully placed across the output capaci-
cases. When the M1 switch is always on (boost region), tor. The resultant feedback signal (FBOUT) is compared
current is automatically drawn from the CSPOUT and/or with the internal precision voltage reference (typically
BOOST2 pins to charge the BOOST1 capacitor as needed. 1.207V) by the error amplifier EA4. The output voltage is
When the M4 switch is always on (buck region) current given by the equation:
is drawn from the CSNIN and/or BOOST1 pins to charge
 R 
the BOOST2 capacitor. Because of this function, CSPIN VOUT = 1.207V •  1+ FBOUT1 
and CSNIN should be connected to a potential close to  RFBOUT2 
VIN. Tie both pins to VIN if they are not being used. Also,
where RFBOUT1 and RFBOUT2 are shown in Figure 1.
CSPOUT and CSNOUT should always be tied to a potential
close to VOUT, or be tied directly to VOUT if not being used.

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LT8705
APPLICATIONS INFORMATION
Input Voltage Regulation or Undervoltage Lockout FROM DC
RSENSE1
TO REMAINDER
POWER SUPPLY OF SYSTEM
By connecting a resistor divider between VIN, FBIN and INPUT
GND, the FBIN pin provides a means to regulate the input CURRENT

voltage or to create an undervoltage lockout function. LT8705 CSPIN CSNIN

TO BOOST CAPACITOR
Referring to error amplifier EA3 in the Block Diagram, + Ω–
CHARGE CONTROL BLOCK
gm = 1m
when FBIN is lower than the 1.205V reference VC is pulled A7
low. For example, if VIN is provided by a relatively high
impedance source (i.e., a solar panel) and the current draw
+
–
1.61V 1.208V
pulls VIN below a preset limit, VC will be reduced, thus FAULT
EA2
reducing current draw from the input supply and limiting CONTROL
–
+
the voltage drop. Note that using this function in forced
continuous mode (MODE pin low) can result in current IMON_IN VC

being drawn from the output and forced into the input.
If this behavior is not desired then use discontinuous or RIMON_IN CIMON_IN

Burst Mode operation. 8705 F10

To set the minimum or regulated input voltage use: Figure 10. Input Current Monitor and Limit
 R 
VIN(MIN) = 1.205V •  1+ FBIN1  FROM RSENSE2
 RFBIN2  CONTROLLER
VOUT
TO SYSTEM VOUT

OUTPUT
where RFBIN1 and RFBIN2 are shown in Figure 1. Make CURRENT

sure to select RFBIN1 and RFBIN2 such that FBIN doesn’t TO BOOST CAPACITOR CSPOUT CSNOUT LT8705
exceed 30V (absolute maximum rating) under maximum CHARGE CONTROL BLOCK
+ Ω–
VIN conditions. gm = 1m
A8
This same technique can be used to create an undervolt-
age lockout if the LT8705 is NOT in forced continuous –
1.61V 1.208V +
mode. When in Burst Mode operation or discontinuous FAULT
EA1
CONTROL
mode, forcing VC low will stop all switching activity. Note +
–
that this does not reset the soft-start function, therefore
IMON_OUT VC
resumption of switching activity will not be accompanied
by a soft-start.
RIMON_OUT CIMON_OUT

Input/Output Current Monitoring and Limiting 8705 F11

The LT8705 has independent input and output current

Figure 11. Output Current Monitor and Limit
monitor circuits that can be used to monitor and/or limit
the respective currents. The current monitor circuits work all four of the current sense pins can draw bias current
as shown in Figures 10 and 11. under normal operating conditions. As such, do not place
As described in the Topside MOSFET Driver Supply section, resistors in series with any of the CSxIN or CSxOUT pins.
the CSNIN and CSPOUT pins are also connected to the Also, because of their use with the Boost Capacitor Charge
Boost Capacitor Charge Control block (also see Figure 1) Control block, tie the CSPIN and CSNIN pins to VIN and
and can draw current in certain conditions. In addition, tie the IMON_IN pin to ground when the input current

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 LT8705
APPLICATIONS INFORMATION
sensing is not in use. Similarly, the CSPOUT and CSNOUT Current Limiting: As shown in Figure 10, IMON_IN voltages
pins should be tied to VOUT and IMON_OUT should be exceeding 1.208V (typical) cause the VC voltage to reduce,
grounded when not in use. thus limiting the inductor and input currents. RIMON_IN can
be selected for a desired input current limit using:
The remaining discussion refers to the input current moni-
tor circuit. All discussion and equations are applicable to  
the output current monitor circuit, substituting pin and  1.208V 
device names as appropriate.
RIMON _IN = 
A Ω
I
 RSENSE(LIMIT) •1m • R 
Current Monitoring: For input current monitoring, cur- V SENSE1
rent flowing through RSENSE1 develops a voltage across For example, if RSENSE1 is chosen to be 12.5mΩ and the
CSPIN and CSNIN which is multiplied by 1mA/V (typical), desired input current limit is 4A then:
converting it to a current that is forced out of the IMON_IN
pin and into resistor RIMON_IN (Note: Negative CSPIN to 1.208V
RIMON _IN = = 24.2kΩ
CSNIN voltages are not multiplied and no current flows A
4A •1m •12.5mΩ
out of IMON_IN in that case). The resulting IMON_IN volt- V
age is then proportional to the input current according to:
Review the Electrical Characteristics and the IMON Output
 A  Currents graph in the Typical Performance Characteris-
VIMON _IN =IRSENSE1 •  RSENSE1 •1m •RIMON _IN
 V  tics section to understand the operational limits of the
IMON_OUT and IMON_IN currents.
For accurate current monitoring, the CSPIN and CSNIN
Overcurrent Fault: If IMON_IN exceeds 1.61V (typical), a
voltages should be kept above 1.5V (CSPOUT and CSNOUT
fault will occur and switching activity will stop (see Fault
pins should be kept above 0V). Also, the differential volt-
Conditions earlier in the data sheet). The fault current is
age VCSPIN-CSNIN should be kept below 100mV due to
determined by:
the limited amount of current that can be driven out of
IMON_IN. Finally, the IMON_IN voltage must be filtered  1.61V 
IRSENSE1(FAULT) =  •IRSENSE1(LIMIT)  A
with capacitor CIMON_IN because the input current often  1.208V 
has ripple and discontinuities depending on the LT8705’s
region of operation. CIMON_IN should be chosen by the For example, an input current limit set to 4A would have
equation: a fault current limit of 5.3A.
 100  Output Overvoltage
CIMON _IN >  F
 f •RIMON _IN  If the output voltage is higher than the value set by the
FBOUT resistor divider, the LT8705 will respond according
where f is the switching frequency, to achieve adequate to the mode and region of operation. In forced continu-
filtering. Additional capacitance, bringing the CIMON_IN ous mode, the LT8705 will sink current into the input (see
total to 0.1μF to 1μF, may be necessary to maintain loop the Reverse Current Limit discussion in the Applications
stability if the IMON_IN pin is used in a constant-current Information section for more information). In discontinu-
regulation loop. ous mode and Burst Mode operation, switching will stop
and the output will be allowed to remain high.

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LT8705
APPLICATIONS INFORMATION
INTVCC Regulators and EXTVCC Connection The maximum current drawn through the INTVCC LDO
occurs under the following conditions:
The LT8705 features two PNP LDOs (low dropout regu-
lators) that regulate the 6.35V (typical) INTVCC pin from 1. Large (capacitive) MOSFETs are being driven at high
either the VIN or EXTVCC supply pin. INTVCC powers the frequencies.
MOSFET gate drivers via the required GATEVCC connec- 2. VIN and/or VOUT is high, thus requiring more charge to
tion and also powers the LDO33 pin regulator and much turn the MOSFET gates on and off.
of the LT8705’s internal control circuitry. The INTVCC
LDO selection is determined automatically by the EXTVCC 3. The LDO33 pin output current is high.
pin voltage. When EXTVCC is lower than 6.22V (typical), 4. In some applications, LDO current draw is maximum
INTVCC is regulated from the VIN LDO. After EXTVCC rises when the part is operating in the buck-boost region
above 6.4V (typical), INTVCC is regulated by the EXTVCC where VIN is close to VOUT since all four MOSFETs are
LDO instead. switching.
Overcurrent protection circuitry typically limits the To check for overheating find the operating conditions that
maximum current draw from either LDO to 127mA. When consume the most power in the LT8705 (PLT8705). This
GATEVCC and INTVCC are below 4.65V, during start-up or will often be under the same conditions just listed that
during an overload condition, the typical current limit is maximize LDO current. Under these conditions monitor
reduced to 42mA. The INTVCC pin must be bypassed to the CLKOUT pin duty cycle to measure the approximate die
ground with a minimum 4.7μF ceramic capacitor placed temperature. See the Junction Temperature Measurement
as close as possible to the INTVCC and GND pins. An ad- section for more information.
ditional ceramic capacitor should be placed as close as
possible to the GATEVCC and GND pins to provide good Powering INTVCC from VOUT/EXTVCC can also provide
bypassing to supply the high transient current required by enough gate drive when VIN drops as low as 2.8V. This
the MOSFET gate drivers. 1μF to 4.7μF is recommended. allows the part to operate with a reduced input voltage
after the output gets into regulation.
Power dissipated in the INTVCC LDOs must be minimized
to improve efficiency and prevent overheating of the The following list summarizes the three possible connec-
LT8705. Since LDO power dissipation is proportional to tions for EXTVCC:
the input voltage and VIN can be as high as 80V in some 1. EXTVCC left open (or grounded). This will cause INTVCC
applications, the EXTVCC pin is available to regulate IN- to be powered from VIN through the internal 6.35V
TVCC from a lower input voltage. The EXTVCC pin is con- regulator at the cost of a small efficiency penalty.
nected to VOUT in many applications since VOUT is often
2. EXTVCC connected directly to VOUT (VOUT > 6.4V). This
regulated to a much lower voltage than the maximum VIN.
is the normal connection for the regulator and usually
During start-up, power for the MOSFET drivers, control
provides the highest efficiency.
circuits and the LDO33 pin is derived from VIN until VOUT/
EXTVCC rises above 6.4V, after which the power is derived 3. EXTVCC connected to an external supply. If an external
from VOUT/EXTVCC. This works well, for example, in a supply is available greater than 6.4V (typical) it may be
case where VOUT is regulated to 12V and the maximum used to power EXTVCC.
VIN voltage is 40V. EXTVCC can be floated or grounded
when not in use or can also be connected to an external
power supply if available.

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APPLICATIONS INFORMATION
Loop Compensation Table 1: Voltage Lockout Conditions
The loop stability is affected by a number of factors includ- APPROXIMATE
VOLTAGE CHIP STATE
ing the inductor value, output capacitance, load current, PIN CONDITION (FIGURE 2) READ SECTION
VIN, VOUT and the VC resistor and capacitors. The LT8705 VIN <2.5V Chip Off Operation: Start-Up
uses internal transconductance error amplifiers driving VC SHDN <1.18V Chip Off
to help compensate the control loop. For most applications INTVCC and <4.65V Switcher
a 3.3nF series capacitor at VC is a good value. The parallel GATEVCC Off
capacitor (from VC to GND) is typically 1/10th the value SWEN <1.18V Switcher
of the series capacitor to filter high frequency noise. A Off
larger VC series capacitor value may be necessary if the LDO33 <3.04 Switcher
Off
output capacitance is reduced. A good starting value for
IMON_IN >1.61V Fault Operation: Fault Conditions
the VC series resistor is 20k. Lower resistance will improve
IMON_OUT >1.61V Fault
stability but will slow the loop response. Use a trim pot
FBIN <1.205V — Applications Information:
instead of a fixed resistor for initial bench evaluation to Input Voltage Regulation or
determine the optimum value. Undervoltage Lockout

LDO33 Pin Regulator Due to their accurate thresholds, configurable undervolt-

The LT8705 includes a low dropout regulator (LDO) to age lockouts (UVLOs) can be implemented using the
regulate the LDO33 pin to 3.3V. This pin can be used to SHDN, SWEN and in some cases, FBIN pin. The UVLO
power external circuitry such as a microcontroller or other function sets the turn on/off of the LT8705 at a desired
desired peripherals. The input supply for the LDO33 pin minimum input voltage. For example, a resistor divider
regulator is INTVCC. Therefore INTVCC must have sufficient can be connected between VIN, SHDN and GND as shown
voltage, typically >4.0V, to properly regulate LDO33. The in Figures 1 and 14. From the Electrical Characteristics,
LDO33 and INTVCC regulators are enabled by the SHDN pin SHDN has typical rising and falling thresholds of 1.234V
and are not affected by SWEN. The LDO33 pin regulator and 1.184V respectively. The falling threshold for turning
has overcurrent protection circuitry that typically limits off switching activity can be chosen using:
the output current to 17.25mA. An undervoltage lockout
monitoring LDO disables switching activity when LDO33 RSHDN1 =
(
RSHDN2 • V(IN,CHIP _ OFF,FALLING) – 1.184V )Ω
falls below 3.04V (typical). LDO33 should be bypassed 1.184V
locally with 0.1µF or more.
For example, choosing RSHDN2 = 20k and a falling VIN
Voltage Lockouts threshold of 5.42V results in:
The LT8705 contains several voltage detectors to make 20kΩ • ( 5.42V – 1.184V )
sure the chip is under proper operating conditions. Table 1 RSHDN1 = = 71.5kΩ
1.184V
summarizes the pins that are monitored and also indicates
the state that the LT8705 will enter if an under or overvolt- The rising threshold for enabling switching activity would
age condition is detected. be:
1.234V
The conditions are listed in order of priority from top V(IN,CHIP _ OFF,RISING) = V(IN,CHIP _ OFF,FALLING) •
to bottom. If multiple over/undervoltage conditions are 1.184V
detected, the chip will enter the state listed highest on or 5.65V in this example.
the table.

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LT8705
APPLICATIONS INFORMATION
Similar calculations can be used to select a resistor divider Junction Temperature Measurement
connected to SWEN that would stop switching activity dur- The duty cycle of the CLKOUT signal is linearly proportional
ing an undervoltage condition. Make sure that the divider to the die junction temperature, TJ. Measure the duty cycle
doesn’t cause SWEN to exceed 7V (absolute maximum of the CLKOUT signal and use the following equation to
rating) under maximum VIN conditions. Using the FBIN approximate the junction temperature:
pin as an undervoltage lockout is discussed in the Input
Voltage Regulation or Undervoltage Lockout section. DCCLKOUT – 35.9%
TJ ≅ °C
0.329%
Inductor Current Sense Filtering
where DCCLKOUT is the CLKOUT duty cycle in % and TJ
Certain applications may require filtering of the inductor
is the die junction temperature in °C. The actual die tem-
current sense signals due to excessive switching noise
perature can deviate from the above equation by ±10°C
that can appear across RSENSE. Higher operating voltages,
higher values of RSENSE, and more capacitive MOSFETs Thermal Shutdown
will all contribute additional noise across RSENSE when
the SW pins transition. The CSP/CSN sense signals can If the die junction temperature reaches approximately
be filtered by adding one of the RC networks shown in 165°C, the part will go into thermal shutdown. The power
Figures 12a and 12b. Most PC board layouts can be drawn switch will be turned off and the INTVCC and LDO33
to accommodate either network on the same board. The regulators will be turned off (see Figure 2). The part will
network should be placed as close as possible to the IC. be re-enabled when the die temperature has dropped by
The network in Figure 12b can reduce common mode ~5°C (nominal). After re-enabling, the part will start in
noise seen by the CSP and CSN pins of the LT8705 at the the switcher off state as shown in Figure 2. The part will
expense of some increased ground trace noise as current then initialize, perform a soft-start, then enter normal
passes through the capacitors. A short direct path from the operation as long as the die temperature remains below
capacitor grounds to the IC ground should be used on the approximately 165°C.
PC board. Resistors greater than 10Ω should be avoided
as this can increase offset voltages at the CSP/CSN pins. Efficiency Considerations
The RC product should be kept to less than 30ns. The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
10Ω
CSP useful to analyze individual losses to determine what is
RSENSE 1nF LT8705 limiting the efficiency and which change would produce
10Ω
CSN
the most improvement. Although all dissipative elements
8705 F12a
in the circuit produce losses, four main sources account
(12a)
for most of the losses in LT8705 circuits:
1. Switching losses. These losses arises from the brief
10Ω
CSP amount of time switch M1 or switch M3 spends in the
RSENSE 1nF LT8705 saturated region during switch node transitions. Power
10Ω
CSN loss depends upon the input voltage, load current, driver
1nF
8705 F12b
strength and MOSFET capacitance, among other fac-
tors. See the Power MOSFET Selection and Efficiency
(12b) Considerations section for more details.
Figure 12. Inductor Current Sense Filter

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 LT8705
APPLICATIONS INFORMATION
2. DC I2R losses. These arise from the resistances of the • The high di/dt path formed by switch M1, switch M2,
MOSFETs, sensing resistors, inductor and PC board D1, RSENSE and the CIN capacitor should be compact
traces and cause the efficiency to drop at high output with short leads and PC trace lengths. The high di/dt
currents. path formed by switch M3, switch M4, D2 and the COUT
3. INTVCC current. This is the sum of the MOSFET driver capacitor also should be compact with short leads and
current, LDO33 pin current and control currents. The PC trace lengths. Two layout examples are shown in
INTVCC regulator’s input voltage times the current Figures 13a and 13b.
represents lost power. This loss can be reduced by
VIN SW1 SW2 VOUT
supplying INTVCC current through the EXTVCC pin from
L
a high efficiency source, such as the output or alternate
supply if available. Also, lower capacitance MOSFETs
can reduce INTVCC current and power loss.
4. CIN and COUT loss. The input capacitor has the difficult D1 D2
job of filtering the large RMS input current to the regu-
lator in buck mode. The output capacitor has the more M1 M2 M3 M4
difficult job of filtering the large RMS output current in
boost mode. Both CIN and COUT are required to have CIN COUT

low ESR to minimize the AC I2R loss and sufficient

capacitance to prevent the RMS current from causing RSENSE
additional upstream losses in fuses or batteries.
LT8705
CKT
5. Other losses. Schottky diodes D1 and D2 are respon- GND

sible for conduction losses during dead time and light 8705 F13a

(13a)
load conduction periods. Inductor core loss occurs
predominately at light loads. VIN SW1 SW2 VOUT
L
When making adjustments to improve efficiency, the input D2

current is the best indicator of changes in efficiency. If M1 M4

one makes a change and the input current decreases, then
the efficiency has increased. If there is no change in input D1

current, then there is no change in efficiency. M2 M3

CIN COUT
Circuit Board Layout Checklist
The basic circuit board layout requires a dedicated ground RSENSE
plane layer. Also, for high current, a multilayer board LT8705
CKT
provides heat sinking for power components. GND
8705 F13b

• The ground plane layer should not have any traces and
(13b)
should be as close as possible to the layer with the
power MOSFETs. Figure 13. Switches Layout

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LT8705
APPLICATIONS INFORMATION
• Avoid running signal traces parallel to the traces that • Connect the input capacitors, CIN, and output capacitors,
carry high di/dt current because they can receive in- COUT, closely to the power MOSFETs. These capacitors
ductively coupled voltage noise. This includes the SW1, carry the MOSFET AC current in the boost and buck
SW2, TG1 and TG2 traces to the controller. regions.
• Use immediate vias to connect the components (includ- • Connect the FBOUT and FBIN pin resistor dividers to
ing the LT8705’s GND pins) to the ground plane. Use the (+) terminals of COUT and CIN respectively. Small
several vias for each power component. FBOUT/FBIN bypass capacitors may be connected
closely to the LT8705’s GND pin if needed. The resistor
• Minimize parasitic SW pin capacitance by removing
connections should not be along the high current or
GND and VIN copper from underneath the SW1 and
noise paths.
SW2 regions.
• Route current sense traces (CSP/CSN, CSPIN/CSNIN,
• Except under the SW pin regions, flood all unused
CSPOUT/CSNOUT) together with minimum PC trace
areas on all layers with copper. Flooding with copper
spacing. Avoid having sense lines pass through noisy
will reduce the temperature rise of power components.
areas, such as switch nodes. The optional filter network
Connect the copper areas to a DC net (e.g., quiet GND).
capacitor between CSP and CSN should be as close as
• Partition the power ground from the signal ground. The possible to the IC. Ensure accurate current sensing with
small-signal component grounds should not return to Kelvin connections at the RSENSE resistors.
the IC GND through the power ground path.
• Connect the VC pin compensation network closely to
• Place switch M2 and switch M3 as close to the controller the IC, between VC and the signal ground pins. The
as possible, keeping the GND, BG and SW traces short. capacitor helps to filter the effects of PCB noise and
• Minimize inductance from the sources of M2 and M3 output voltage ripple voltage from the compensation
to RSENSE by making the trace short and wide. loop.

• Keep the high dV/dT nodes SW1, SW2, BOOST1, • Connect the INTVCC and GATEVCC bypass capacitors
BOOST2, TG1 and TG2 away from sensitive small-signal close to the IC. The capacitors carry the MOSFET driv-
nodes. ers’ current peaks.

• The output capacitor (–) terminals should be connected Design Example

as closely as possible to the (–) terminals of the input
VIN = 8V to 25V
capacitor.
VOUT = 12V
• Connect the top driver boost capacitor, CB1, closely
to the BOOST1 and SW1 pins. Connect the top driver IOUT(MAX) = 5A
boost capacitor, CB2, closely to the BOOST2 and SW2 f = 350kHz
pins.
Maximum ambient temperature = 60°C

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 LT8705
APPLICATIONS INFORMATION
RT Selection: Choose the RT resistor for the free-running Now calculate the maximum RSENSE values in the boost
oscillator frequency using: and buck regions to be:
 43,750   43,750  RSENSE(MAX,BOOST) =
RT =  – 1 kΩ =  – 1 = 124kΩ
 fOSC   350 
2 • VRSENSE(MAX,BOOST,MAX) • VIN(MIN)
Ω
RSENSE Selection: Start by calculating the maximum duty (2 •IOUT(MAX,BOOST) • VOUT(MIN) ) + ( ∆IL(MAX,BOOST) • VIN(MIN) )
cycle in the boost region:
2 •107mV • 8V
= = 11.4mΩ
 VIN(MIN)  (2 • 5A •12V ) + (3.75A • 8V )
DC(MAX,M3,BOOST) ≅  1–  • 100%
 VOUT(MAX) 
2 • 86mV
RSENSE(MAX,BUCK) = Ω

=  1–
8V 
• 100% = 33%
(2 •IOUT(MAX,BUCK) ) – ∆IL(MIN,BUCK)
 12V 
2 • 86mV
= = 18.2mΩ
Next, from the Maximum Inductor Current Sense Voltage (2 • 5A ) – 0.53A
vs Duty Cycle graph in the Typical Performance Charac-
Adding an additional 30% margin, choose RSENSE to be
teristics section:
11.4mΩ/1.3 = 8.7mΩ.
VRSENSE(MAX,BOOST,MAX) ≅ 107mV
Inductor Selection: With RSENSE known, we can now
Next, estimate the maximum and minimum inductor cur- determine the minimum inductor value that will provide
rent ripple in the boost and buck regions respectively: adequate load current in the boost region using:
VOUT(MAX) •IOUT(MAX,BOOST) L(MIN1,BOOST) ≅
∆IL(MAX,BOOST) ≅ A
 100% 
VIN(MIN) •  – 0.5 DC(MAX,M3,BOOST)
 %Ripple  VIN(MIN) •
100% H
12V • 5A  VRSENSE(MAX,BOOST,MAX) IOUT(MAX) • VOUT(MAX) 
= = 3.75A 2• f • –
 100%  RSENSE VIN(MIN) 
8V •  – 0.5  
 40% 
 33% 
IOUT(MAX,BUCK) 8V • 
∆IL(MIN,BUCK) ≅ A  100% 
 100%  = = 0.8µH
 – 0.5  107mV 5A •12V 
10% 2 • 350kHz •  – 
 8.7mΩ 8V 
5A
= = 0.53A
 100% 
 – 0.5
10% 

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To avoid subharmonic oscillations in the inductor current, Since maximum I2R power dissipation in the boost region
choose the minimum inductance according to: happens when VIN is minimum, we can determine the
maximum allowable RDS(ON) for the boost region using:
  VIN(MIN) • VOUT(MAX)    V 
2 
 VOUT(MAX) –  OUT
  •RSENSE PM1 = PI2R ≅ •IOUT  •RDS(ON) • ρτ  W
  VOUT(MAX) – VIN(MIN)     VIN  
L(MIN2,BOOST) = H
0.08 • f
  12V 
2 
  8V •12V   1.3W ≅   • 5A  •RDS(ON) •1.5 W and therefore
12V –  12V – 8V   • 8.7mΩ   8V  
=  = –3.7µH
0.08 • 350kHz RDS(ON) < 15.4mΩ
 VOUT(MAX) 
VIN(MAX) •  1–  •RSENSE The Fairchild FDMS7672 meets the specifications with a
 VIN(MAX) – VOUT(MIN) 
L(MIN1,BUCK) = maximum RDS(ON) of ~6.9mΩ at VGS = 4.5V (~10mΩ at
0.08 • f 125°C). Checking the power dissipation in the buck region
 12V  with VIN maximum and VOUT minimum yields:
25V •  1– • 8.7mΩ
 25V – 12V  PM1 = PI2R +PSWITCHING
= = 0.6µH
0.08 • 350kHz
 V 
2 
The inductance must be higher than all of the minimum ≅ OUT
•IOUT  •RDS(ON) • ρτ  + ( VIN •IOUT • f • tRF1) W
values calculated above. We will choose a 10μH standard   VIN  
value inductor for improved margin.
  12V 
2 
MOSFET Selection: The MOSFETs are selected based on PM1 ≅   • 5A  • 6.9mΩ •1.5 + ( 25V • 5A • 350k • 20ns)
  25V  
voltage rating, CRSS and RDS(ON) value. It is important to
ensure that the part is specified for operation with the = 0.06W + 0.88W = 0.94W
available gate voltage amplitude. In this case, the amplitude
is 6.35V and MOSFETs with an RDS(ON) value specified at The maximum switching power of 0.88W can be reduced
VGS = 4.5V can be used. by choosing a slower switching frequency. Since this
calculation is approximate, measure the actual rise and
Select M1 and M2: With 25V maximum input voltage, fall times on the PCB to obtain a better power estimate.
MOSFETs with a rating of at least 30V are used. As we do
not yet know the actual thermal resistance (circuit board The maximum dissipation in M2 occurs at maximum input
design and airflow have a major impact) we assume that voltage when the circuit is operating in the buck region.
the MOSFET thermal resistance from junction to ambient Using the 6.9mΩ Fairchild FDMS7672 the dissipation is:
is 50°C/W.  V –V 
P(M2,BUCK) ≅  IN OUT •IOUT(MAX)2 •RDS(ON) • ρτ  W
If we design for a maximum junction temperature, TJ(MAX)  VIN 
= 125°C, the maximum allowable power dissipation can be
calculated. First, calculate the maximum power dissipation:  25V – 12V 
• ( 5A ) • 6.9mΩ •1.5 = 0.13W
2
P(M2,BUCK) ≅ 
 25V 
TJ(MAX) – TA(MAX)
PD(MAX) =
R TH(JA)

125°C – 60°C
PD(MAX) = = 1.3W
50°C/W

8705f

38 For more information www.linear.com/LT8705

 LT8705
APPLICATIONS INFORMATION
Select M3 and M4: With 12V output voltage we need Capacitors: A low ESR (5mΩ) capacitor network for CIN
MOSFETs with 20V or higher rating. is selected. In this mode, the maximum ripple is:
The highest dissipation occurs in the boost region when VIN(MAX) •IOUT(MAX)
∆V(BUCK,ESR) ≅ •ESR
input voltage is minimum and output current is highest. VOUT(MIN)
For switch M3 the dissipation is:
25V • 5A
PM3 = PI2R + PSWITCHING ≅ ∆V(BUCK,ESR) ≅ • 5mΩ = 52mV
12V
 ( VOUT – VIN ) • VOUT 
 •IOUT 2 • R DS(ON) • ρ τ  assuming ESR dominates the ripple.
 VIN2 
Having 5mΩ of ESR for the COUT network sets the maxi-
 t  mum output voltage ripple at:
+  VOUT 2 •IOUT • f • RF2  W
 VIN  VOUT(MAX) •IOUT(MAX)
∆V(BOOST,ESR) ≅ •ESR
VIN(MIN)
as described in the Power MOSFET Selection and Efficiency
Considerations section. 12V • 5A
∆V(BOOST,ESR) ≅ • 5mΩ = 37.5mV
The maximum dissipation in switch M4 is: 8V

 VOUT(MAX)  assuming ESR dominates the ripple.

P(M4,BOOST ) ≅  •IOUT 2 • ρ τ • R DS(ON)  W
 VIN(MIN) 

The Fairchild FDMS7672 can also be used for M3 and M4.

Assuming 20ns rise and fall times, the calculated power
loss at the minimum 8V input voltage is then 0.82W for
M3 and 0.39W for M4
Output Voltage: Output voltage is 12V. Select RFBOUT2 as
20k. RFBOUT1 is:
 V 
RFBOUT1 =  OUT – 1 •RFBOUT2
 1.207V 

Select RFBOUT1 as 178k. Both RFBOUT1 and RFBOUT2 should

have a tolerance of no more than 1%.

8705f

For more information www.linear.com/LT8705 39

LT8705
TYPICAL APPLICATIONS
L1
M1
22µH VOUT
VIN ×2 M4
48V
36V TO 80V + CIN1 CIN2
M3
COUT1 + COUT2 5A
220µF 4.7µF M2 4.7µF 220µF
×2 ×4 ×2 ×6 ×2
TO TO
DIODE DB1 DIODE DB2
0.22µF 1nF 10Ω 0.22µF
9mΩ
2Ω* 1nF 10Ω
2Ω** 392k

TG1 BOOST1 SW1 BG1 CSP CSN GND BG2 SW2 BOOST2 TG2
CSNIN CSPOUT
CSPIN CSNOUT
VIN EXTVCC
SHDN FBOUT
100k
SWEN INTVCC 10k
LDO33 LT8705 GATEVCC 4.7µF
MODE SRVO_FBIN
4.7µF
FBIN SRVO_FBOUT
RT SRVO_IIN 4Ω

71.5k SS SRVO_IOUT
DB1 DB2
IMON_IN
1µF TO TO
VC CLKOUT SYNC IMON_OUT BOOST1 BOOST2
20k 215k
56.2k
202kHz
4.7µF 1µF 220pF 3.3nF

8705 F14a
CIN1, COUT2: 220µF, 100V *2Ω FROM TG1 TO EACH SEPERATE M1 GATE
CIN2, COUT1: 4.7µF, 100V, TDK C453X7S2A475M **2Ω FROM BG2 TO EACH SEPERATE M3 GATE
DB1, DB2: CENTRAL SEMI CMMR1U-02-LTE
L1: 22µH, WÜRTH 74435572200 OR COILCRAFT SER2918H-223
M1, M3: FAIRCHILD FDMS86104
M2, M4: FAIRCHILD FDMS86101

Efficiency vs Output Current Efficiency vs Output Current

(Boost Region) (Buck Region)
100 100
VIN = 36V VIN = 72V
90 VOUT = 48V 90 VOUT = 48V
CCM CCM
80 80
70 70
EFFICIENCY (%)

EFFICIENCY (%)

60 60
50 50
40 40
30 30
20 20
10 COILCRAFT SER2918H-223 10 COILCRAFT SER2918H-223
WURTH 74435572200 WURTH 74435572200
0 0
10 100 1000 10000 10 100 1000 10000
LOAD CURRENT (mA) 8705 F14b LOAD CURRENT (mA) 8705 F14c

Note: See the front page and the Typical Performance Characteristics section for more curves from this application
circuit using the Coilcraft inductor. The smaller Würth inductor is also suitable in place of the Coilcraft inductor with
some loss in efficiency.
Figure 14. Telecom Voltage Stabilizer
8705f

40 For more information www.linear.com/LT8705

 LT8705
APPLICATIONS INFORMATION
Supercapacitor Backup Supply
TO
LOADS L1
DIN
VINP 25mΩ 2.2µH M4 25mΩ
VIN M1 VOUT
12V + CIN1 CIN2 COUT1
+ COUT2
15V
M2 M3
×2 ×3 ×3 ×2
TO TO
DIODE DB1 DIODE DB2
CSC 1.2k
0.22µF 0.22µF ×6 ×6
3mΩ
2Ω 2Ω
115k

TG1 BOOST1 SW1 BG1 CSP CSN GND BG2 SW2 BOOST2 TG2
CSNIN CSPOUT
CSPIN CSNOUT
VIN EXTVCC
SHDN FBOUT
SWEN INTVCC 10k
100k 4.7µF
LDO33 LT8705 GATEVCC
MODE SRVO_FBIN 4Ω 4.7µF

FBIN SRVO_FBOUT
DB1 DB2
RT SRVO_IIN
15V 113k 1µF 71.5k SS SRVO_IOUT TO TO
BOOST1 BOOST2
IMON_IN
2N3904*
VC CLKOUT SYNC IMON_OUT
1k 20k 20k 124k 24k
14.3k
350kHz 47.5k 100nF 100nF
4.7µF 1µF 220pF 15nF

8705 TA02a

CIN1, COUT2: 100µF, 20V SANYO OS-CON 205A100M DIN: APPROPRIATE 2A SCHOTTKY DIODE OR IDEAL *INPUT SIDE OVERVOLTAGE PROTECTION WHEN CONVERTER
CIN2, COUT1: 22µF, 25V, TDK C4532X741E226M DIODE SUCH AS LTC4358, LTC4412, LTC4352, ETC. IS DRAWING CURRENT FROM THE SUPER CAPACITORS
CSC: 60F, 2.5V COOPER BUSSMAN HB1840-2R5606-R DB1, DB2: CENTRAL SEMI CMMR1U-02-LTE
L1: 2.2µH, VISHAY IHLP-5050CE-01-2R2-M-01
M1-M4: FAIRCHILD FDMS7698

12V LOADS LOADS

POWER FLOW POWER FLOW
DIN DIN
25mΩ 25mΩ 0V 25mΩ 25mΩ
12V
INPUT INPUT
CSC 1.2k CSC 1.2k
INPUT CURRENT LIMIT
113k CAPACITOR 113k 115k
IN EXCESS OF 2A
CHARGING REGULATE LOADS
WILL DRAW FROM 1.2k CSC 1.2k
CURRENT CSC TO 8V
SUPER CAPS 20k 10k
20k TO 1A
115k 1.2k CSC 1.2k
CSC
REGULATE CAPACITORS
TO 15V
10k 1.2k CSC 1.2k
CSC

1.2k CSC 1.2k

CSC

CSC 1.2k CSC 1.2k

8705 TA02c

Charging VOUT to 15V Remove VIN. Loads (4A Draw)

8705 TA02b

with 1A Current Regulated to 8V from Supercaps

VOUT
15V
5V/DIV
VIN
5V/DIV VINP 8V
VOUT 5V/DIV
5V/DIV

IL IL
5A/DIV 5A/DIV

8705 TA02d 8705 TA02e

20SEC/DIV 3SEC/DIV
8705f

For more information www.linear.com/LT8705 41

LT8705
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)

0.70 ±0.05

5.50 ±0.05
5.15 ±0.05

4.10 ±0.05

3.00 REF 3.15 ±0.05

PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
5.5 REF
6.10 ±0.05
7.50 ±0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH
R = 0.30 TYP OR
0.75 ±0.05 3.00 REF 0.35 × 45° CHAMFER
5.00 ±0.10
0.00 – 0.05 37 38

0.40 ±0.10
PIN 1
TOP MARK 1
(SEE NOTE 6)
2

5.15 ±0.10
7.00 ±0.10 5.50 REF

3.15 ±0.10

(UH) QFN REF C 1107

0.200 REF 0.25 ±0.05 R = 0.125 R = 0.10

0.50 BSC TYP TYP
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
OUTLINE M0-220 VARIATION WHKD MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
8705f

42 For more information www.linear.com/LT8705

 LT8705
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package
Package Variation: FE38 (31)
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1665 Rev B)
Exposed Pad Variation AB

4.75 REF 9.60 – 9.80*

(.378 – .386)
4.75 REF
(.187)
38 20

6.60 ±0.10
2.74 REF
4.50 REF
SEE NOTE 4 6.40
2.74
0.315 ±0.05 REF (.252)
(.108)
BSC
1.05 ±0.10

0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 19
PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED

1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.50
0.09 – 0.20 0.50 – 0.75 (.0196) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.17 – 0.27
FE38 (AB) TSSOP REV B 0910
(.0067 – .0106)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN MILLIMETERS FOR EXPOSED PAD ATTACHMENT
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

8705f

43
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LT8705
as described herein will not infringe on existing patent rights.
LT8705
TYPICAL APPLICATION
12V Output Converter Accepts 4V to 80V Input (5.5V Minimum to Start)
M1
×2 15µH M4 7mΩ VOUT
VIN
12V
4V TO 80V + CIN2 M3 COUT1B
+ COUT3 5.0A (VIN ≥ 5.5V)
(INCREASED CIN1 M2 4.5A (VIN ≥ 5.0V)
×6 ×2 COUT1A ×3 ×2
VOUT RIPPLE TO DIODE TO DIODE 4.0A (VIN ≥ 4.5V)
×2
FOR VIN > 60V) DB1 DB2 + COUT2 3.5A (VIN ≥ 4.0V)
0.22µF 1nF 10Ω 0.22µF ×3
4mΩ
2Ω* 1nF 10Ω
102k

TG1 BOOST1 SW1 BG1 CSP CSN GND BG2 SW2 BOOST2 TG2
CSNIN CSPOUT
4.7µF
CSPIN CSNOUT
VIN EXTVCC
SHDN FBOUT
100k
SWEN INTVCC 11.3k
LDO33 LT8705 GATEVCC 4.7µF
MODE SRVO_FBIN
4.7µF
FBIN SRVO_FBOUT
RT SRVO_IIN 4Ω
CIN1: 220µF, 100V
38.3k SS SRVO_IOUT CIN2: 4.7µF, 100V, TDK C4532X7S2A475M
DB1 DB2 COUT1A, COUT1B: 22µF, 25V, TDK C4532X7R1E226M
IMON_IN
1µF COUT2: 100µF, 16V, SANYO OS-CON 16SA100M
TO TO
VC IMON_OUT COUT3: 470µF, 16V
CLKOUT SYNC BOOST1 BOOST2
20k 215k DB1, DB2: CENTRAL SEMI CMMR1U-02-LTE
16.5k L1: 15µH, WURTH 7443631500
202kHz 22nF 26.1k M1, M2: FAIRCHILD FDMS86101
4.7µF 1µF 220pF 10nF M3, M4: FAIRCHILD FDMS7692
*2Ω FROM TG1 TO EACH SEPARATE M1 GATE
8705 TA03a

Efficiency vs Output Current Input Transient (4V to 80V)

100

VOUT
200mV/DIV
95
EFFICIENCY (%)

90
VIN
20V/DIV
VIN = 60V
85 VIN = 40V
VIN = 20V
VIN = 12V
VIN = 5V
80 8705 TA03c
0 1 2 3 4 5 ILOAD = 2A 10ms/DIV
LOAD CURRENT (A) 8705 TA03c

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT3791-1 60V High Efficiency (Up to 98%) Synchronous 4-Switch 4.7V ≤ VIN ≤ 60V, 1.2V ≤ 60V, Regulates VOUT, IOUT or IIN, TSSOP-38
Buck-Boost DC/DC Controller
LTC3789 High Efficiency (Up to 98%) Synchronous 4-Switch 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, SSOP-28, 4mm × 5mm QFN-28
Buck-Boost DC/DC Controller
LT3758 High Input Voltage, Boost, Flyback, SEPIC and Inverting 5.5V ≤ VIN ≤ 100V, Positive or Negative VOUT, 3mm × 3mm DFN-10
Controller or MSOP-10E
LTC3115-1 40V, 2A Synchronous Buck-Boost DC/DC Converter 2.7V ≤ VIN ≤ 40V, 2.7V ≤ VOUT ≤ 40V, 4mm × 5mm DFN-16, TSSOP-20
LTM4609 High Efficiency Buck-Boost DC/DC µModule Regulator 4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 34V, 15mm × 15mm × 2.8mm

8705f

Linear Technology Corporation

44
LT 0513 • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LT8705
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT8705  LINEAR TECHNOLOGY CORPORATION 2013