Bias Circuits: Kanazawa University Microelectronics Research Lab. Akio Kitagawa

4.
Bias circuits
Kanazawa University
Microelectronics Research Lab.
Akio Kitagawa
2
4.1 Current Mirror
3
Notation of power line (Rail)
Voltage [V]
VDD
VSS
VDD
GND
(or V
CM
)
VSS
VDD(+2.5V)
VSS(-2.5V)
Analog Digital
5V
V
IL
V
IH
1
0
X
=
4
Constant voltage circuit
Tn GS DS
GS DS
V V V
V V
>
=
Therefore, M1 is driven in the saturation
region. This circuit can output the voltage
V
GS
controlled by I
ref
.
OV Tn
n
ref
Tn ref GS
Tn GS ref D
V
I
V I V
V V I I
A + = + =
= =
|
|
2
) (
) (
2
2
1
I
D
= const. V
GS
= const.
V
GS
= const. I
D
= const.
In the saturation region
(A
OV
: Overdrive voltage)
5
Current mirror
ref ref out
Tn GS ref
Tn GS out
I
L
W
L
W
I I
V V I
V V I
1
2
1
2
2
1
2
2
) (
) (
) (
2
) (
2
= =
=
=
|
|
|
|
6
Sink and source of the current mirror
ref
GS
out
ref out
I
L
W
L
W
I
1
2
) (
) (
=
Current Sink Current Source
50/2
50/2
150/2 150/2
7
M1 M2
Layout sample of the current mirror
Connect at
the center.
Dummy
poly strip
M1 M1 M2 M2
Center of the sources of M1 and M2
Short G and D of M1
8
Deviation from the ideal characteristics
2 ds
out
out
r
v
i =
Small-signal
equivalent circuit
The channel resistance of M2 is not infinite, therefore, M2 cannot
work an ideal current source. The higher drain resistance of M2 is
preferable to improve the characteristic of the current source.
ds2 m2
gs
out
potential difference
9
Cascaded Triode (Cascode circuit)
out m r
r out m
r gs m out
i R g i
i i R g
i v g i
+ =
+ =
+ =
) 1 (
) (
Gate-common MOSFET acts as a trans-impedance amplifier.
Small-signal
equivalent circuit
out ds m
out out m ds
out r ds out
i R r g
i R i R g r
i R i r v
~
+ + =
+ =
) 1 (
The output resistance is amplified to 10~1000times.
ds
m
gs
out
out
out
r
10
Cascode current mirror
3 4 4
) (
ds ds m
out
out
r r g
v
i
=
i
out
, that is, the variation of I
out
is
reduced by the large output
resistance.
ref
GS1
out
out
GS2
50/2
50/2
50/2
50/2
11
Bias condition of MOSFET in
current mirror circuits
) (
,
2
DS OV Tn DS
DS GS
n
DS
Tn GS OV
I V V
V V If
I
V V
A + =
=
= = A
|
VGS
VDS
V
GS
V
DS
I
D
S
Saturation region
V
DS
=V
GS
-V
Tn
Linear region
(Triode region)
OV
) (
) (
DS OV DS
DS OV Tn DS
I V
I V V
A >
A + =
Diode connection
of MOSFET
For diode connection:
For constant V
GS
(M1)
(M2)
12
Output voltage range of the current
mirror
I
ref
M1
M2
I
out
V
out
VSS
M3
M4
V
Tn
+
OV
(I
ref
)
V
Tn
+
OV
(I
ref
) V
DS3
V
DS4
OV
(I
out
)
V
GS4
= V
Tn
+
OV
(I
out
)
V
GS4
VSS
VDD
Output voltage range
V
T n
~0.45V
OV1
~0.2V
OV2
~0.2V
0.85V
) ( 2
) ( ) ( 2
)) ( ( )) ( ( 2
4 3
3
3
4 3 2 1
ref OV Tn DS DS out
out OV ref OV Tn DS
out OV Tn DS ref OV Tn
GS DS GS GS
I V V V V
I I V V
I V V I V
V V V V
A + > + =
A A + =
A + + = A +
+ = +
VDD - VSS > 0.85V
approximately the
same potential
13
I
out
V
out
M3
M4

OV
(I
out
)
2
OV
(I
ref
) -
OV
(I
out
)
~
OV
(I
ref
)
V
Tn
+
OV
(I
ref
)
V
Tn
+ 2
OV
(I
ref
)
V
Tn
+
OV
(I
out
)
Wide-swing cascode current mirror -1
The gate voltage of M4 can be
lowered to V
Tn
+2
OV
.
The gate voltage of M4 (= 2V
Tn
+2
OV
)
is over-biased to drive M3 in the
saturation region.
When the MOSFET M3 can work in the saturation region: V
DS
>
OV
,
the lower limit of output voltage can be reduced to 2
OV
.
VSS
VSS
14
Wide-swing cascode current mirror -2
4
2
2
2
2
2
) ( 2
2
1
5
1 5
1
5
5
|
|
| |
|
|
=
=
+ =
A + =
+ =
ref ref
ref
Tn
ref OV Tn
ref
Tn GS
I I
I
V
I V
I
V V
In consideration of a bias margin for the M3
saturation, the size of M5 is practically set by W/5L.
50/2
50/2
50/2
50/10
(Do not use this circuit)
15
Layout method of long channel
MOSFETs
5L
W
The short channel effect is avoided by the
series connection of W/L MOSFETs.
L
W
L
W
L
W
L
W
L
W
16
Current error of the wide swing
cascode current mirror
VDS
I
D
V
DS
=V
GS
-V
T
V
T
= V
DS1
V
DS3
I
out
The current error AI
out
occurs by
the difference of V
DS1
and V
DS3
.
The problem is remarkable
in the short channel MOSFETs.
I
out
V
out
VSS
M3
M4
I
ref
I
ref
OV
OV
M5
M1
V
Tn
+
OV
W/L
W/5L
Potential
difference
The large L of M1 and M3 can
improve the saturation
characteristic of the MOSFETs,
but the improvement is
insufficient.
17
Practical cascode current mirror
V
DS1
= V
GS5
- V
GS2
= V
Tn
+ 2
OV
(I
ref
) - (V
Tn
+
OV
(I
ref
))
=
OV
(I
ref
)
OV
(I
out
) =V
DS3
When I
ref
= I
out
, V
DS1
V
DS3
.
50/10
50/2
50/2
50/2
50/2
150/2 150/2
M1 and M2 are biased in
the saturation region.
150/2
I
ref
18
Drain regulated current mirror
The highly precise circuit with the NFB(Negative
Feedback) loop. The drain of M1 and M3 is regulated
to the same potential.
If A = , V
DS1
= V
DS3
A
I
DS4
is kept a constant
value by the NFB
control of M4. The
output resistance is
~(A
d
+ 1)(g
m4
/g
ds4
g
ds3
).
19
Design sample of the practical
regulated drain current mirror
n-ch 50/2
p-ch 150/2
Amplifier pair
(The differential amplifier is displaced by an amplifier pair.)
40/2
NFB
20
4.2 Bias circuits
21
Cascode current mirror with a
voltage reference
out
ref
ref ref
22
Bias circuit based on the cascode
current mirror
VSS
VDD
V
Tn
OV
OV
OV
|V
Tp
|
OV
V
Bias1 V
Bias2
V
Bias3 V
Bias4
Voltage
Reference
VSS
VDD
V
Bias1
V
ref
W
p
/4L
p
W
n
/L
n
W
p
/L
p
I
ref
I
ref
V
Bias2
V
Bias3
V
Bias4
I
ref
I
ref
W
n
/4L
n
W
n
/L
n
W
p
/L
p

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