What is a DMA Controller?

Direct Memory Access uses hardware for accessing the memory, that hardware is called a DMA Controller. It has the
work of transferring the data between Input Output devices and main memory with very less interaction with the
processor. The direct Memory Access Controller is a control unit, which has the work of transferring data.

DMA Controller Diagram in Computer Architecture

DMA Controller is a type of control unit that works as an interface for the data bus and the I/O Devices. As mentioned,
DMA Controller has the work of transferring the data without the intervention of the processors, processors can control
the data transfer. DMA Controller also contains an address unit, which generates the address and selects an I/O device for
the transfer of data. Here we are showing the block diagram of the DMA Controller.

Types of Direct Memory Access (DMA)

There are four popular types of DMA.
•Single-Ended DMA
•Dual-Ended DMA
•Arbitrated-Ended DMA
•Interleaved DMA
Single-Ended DMA: Single-Ended DMA Controllers operate by reading and writing from a single memory address.
They are the simplest DMA.
Dual-Ended DMA: Dual-Ended DMA controllers can read and write from two memory addresses. Dual-ended DMA is
more advanced than single-ended DMA.
Arbitrated-Ended DMA: Arbitrated-Ended DMA works by reading and writing to several memory addresses. It is more
advanced than Dual-Ended DMA.
Interleaved DMA: Interleaved DMA are those DMA that read from one memory address and write from another memory
address.

Working of DMA Controller

The DMA controller registers have three registers as follows.
•Address register – It contains the address to specify the desired location in memory.
 •Word count register – It contains the number of words to be transferred.
•Control register – It specifies the transfer mode.

The figure below

shows the block
diagram of the
DMA controller.
The unit
communicates
with the CPU
through the data
bus and control
lines. Through
the use of the
address bus and
allowing the
DMA and RS register to select inputs, the register within the DMA is chosen by the CPU. RD and WR are two-way
inputs. When BG (bus grant) input is 0, the CPU can communicate with DMA registers. When BG (bus grant) input is 1,
the CPU has relinquished the buses and DMA can communicate directly with the memory.
Explanation: The CPU initializes the DMA by sending the given information through the data bus.
•The starting address of the memory block where the data is available (to read) or where data are to be stored (to
write).
•It also sends word count which is the number of words in the memory block to be read or written.
•Control to define the mode of transfer such as read or write.
•A control to begin the DMA transfer

Modes of Data Transfer in DMA

There are 3 modes of data transfer in DMA that are described below.
•Burst Mode: In Burst Mode, buses are handed over to the CPU by the DMA if the whole data is completely
transferred, not before that.
•Cycle Stealing Mode: In Cycle Stealing Mode, buses are handed over to the CPU by the DMA after the transfer of
each byte. Continuous request for bus control is generated by this Data Transfer Mode. It works more easily for
higher-priority tasks.
•Transparent Mode: Transparent Mode in DMA does not require any bus in the transfer of the data as it works when
the CPU is executing the transaction.

8237 DMA Controller

8237 DMA Controller is a type of DMA Controller which has a flexible number of channels but generally works on 4
Input-Output channels. In these present channels, the channel has to be given the highest priority to be decided by the
Priority Encoder. Each channel in the 8237 DMA Controller has to be programmed separately.
8257 DMA Controller
8257 DMA Controller is a type of DMA Controller, that when a single Intel 8212 I/O device is paired with it, becomes 4
channel DMA Controller. In 8257 DMA Controller, the highest priority channel is acknowledged. It contains two 16-bit
registers, one is DMA Address Register and the other one is Terminal Count Register.

Advantages of DMA Controller

•Data Memory Access speeds up memory operations and data transfer.
•CPU is not involved while transferring data.
•DMA requires very few clock cycles while transferring data.
•DMA distributes workload very appropriately.
•DMA helps the CPU in decreasing its load.

Disadvantages of DMA Controller

•Direct Memory Access is a costly operation because of additional operations.
•DMA suffers from Cache-Coherence Problems.
•DMA Controller increases the overall cost of the system.
•DMA Controller increases the complexity of the software.

Interrupts in 8085 microprocessor

In the 8085 microprocessor, an interrupt is a signal that temporarily suspends the normal execution of a program and
redirects the control to a specific interrupt service routine (ISR). Interrupts allow the microprocessor to respond to
external events, such as user input, system events, or hardware signals, without the need for constant polling.
There are five interrupt signals in the 8085 microprocessor:

1. TRAP: The TRAP interrupt is a non-maskable interrupt that is generated by an external device, such as a power
failure or a hardware malfunction. The TRAP interrupt has the highest priority and cannot be disabled.
2. RST 7.5: The RST 7.5 interrupt is a maskable interrupt that is generated by a software instruction. It has the second
highest priority.
3. RST 6.5: The RST 6.5 interrupt is a maskable interrupt that is generated by a software instruction. It has the third
highest priority.
4. RST 5.5: The RST 5.5 interrupt is a maskable interrupt that is generated by a software instruction. It has the fourth
highest priority.
5. INTR: The INTR interrupt is a maskable interrupt that is generated by an external device, such as a keyboard or a
mouse. It has the lowest priority and can be disabled.
When microprocessor receives any interrupt signal from peripheral(s) which are requesting its services, it stops its current
execution and program control is transferred to a sub-routine by generating CALL signal and after executing sub-routine
by generating RET signal again program control is transferred to main program from where it had stopped. When
microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the peripheral which is requesting for
its service. Interrupts can be classified into various categories based on different parameters:

8259 PIC Microcontroller:

Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5 hardware interrupts and 2 hardware interrupts in
Intel 8085 and Intel 8086 microprocessors respectively. But by connecting Intel 8259 with these microprocessors, we can
increase their interrupt handling capability. Intel 8259 combines the multi-interrupt input sources into a single interrupt
output. Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7. For example, Interfacing of 8085 and 8259
increases the interrupt handling capability of 8085 microprocessor from 5 to 8 interrupt levels.
Features of Intel 8259 PIC are as follows:
1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading further 8259 PICs.
5. Clock cycle is not required.
Pin Diagram of
8259 – We can
see through
above diagram
that there are
total 28 pins in
Intel 8259 PIC
where Vcc : 5V
Power supply
and Gnd :
ground. Other
pins use are
explained below.
Block Diagram of 8259 PIC microprocessor –

Data bus buffer – This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as a buffer.
It takes the control word from the 8085 (let say) microprocessor and transfer it to the control logic of 8259
microprocessor. After selection of Interrupt by 8259 microprocessor (based on priority of the interrupt), it transfer the
opcode of the selected Interrupt and address of the Interrupt service sub routine to the other connected microprocessor.
The data bus buffer consists of 8 bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits
data can be transferred at a time.
 1.Read/Write logic – This block works only when the value of pin CS is low (as this pin is active low). This block is responsible
for the flow of data depending upon the inputs of RD and WR. These two pins are active low pins used for read and write
operations.
2.Control logic – It is the center of the PIC and controls the functioning of every block. It has pin INTR which is connected with
other microprocessor for taking interrupt request and pin INT for giving the output. If 8259 is enabled, and the other
microprocessor Interrupt flag is high then this causes the value of the output INT pin high and in this way 8259 responds to the
request made by other microprocessor.
3.Interrupt request register (IRR) – It stores all the interrupt level which are requesting for Interrupt services.
4.Interrupt service register (ISR) – It stores the interrupt level which are currently being executed.
5.Interrupt mask register (IMR) – It stores the interrupt level which have to be masked by storing the masking bits of the
interrupt level.
6.Priority resolver – It examines all the three registers and set the priority of interrupts and according to the priority of the
interrupts, interrupt with highest priority is set in ISR register. Also, it reset the interrupt level which is already been serviced in
IRR.
7.Cascade buffer – To increase the Interrupt handling capability, we can further cascade more number of pins by using cascade
buffer. So, during increment of interrupt capability, CSA lines are used to control multiple interrupt structure.

Advantages:
Interrupt Management: The 8259 PIC is designed to handle interrupts efficiently and effectively, allowing for faster and more
reliable processing of interrupts in a system.

Flexibility: The 8259 PIC is programmable, meaning that it can be customized to suit the specific needs of a given system, including
the number and type of interrupts that need to be managed.

Compatibility: The 8259 PIC is compatible with a wide range of microprocessors, making it a popular choice for managing interrupts
in many different systems.

Multiple Interrupt Inputs: The 8259 PIC can manage up to 8 interrupt inputs, allowing for the management of complex systems
with multiple devices.

Ease of Use: The 8259 PIC includes simple interface pins and registers, making it relatively easy to use and program.

Disadvantages:
Cost: While the 8259 PIC is relatively affordable, it does add cost to a system, particularly if multiple PICs are required.

Limited Number of Interrupts: The 8259 PIC can manage up to 8 interrupt inputs, which may be insufficient for some applications.

Complex Programming: Although the interface pins and registers of the 8259 PIC are relatively simple, programming the 8259 can
be complex, requiring careful attention to interrupt prioritization and other parameters.

Limited Functionality: While the 8259 PIC is a useful peripheral for interrupt management, it does not include more advanced
features, such as DMA (direct memory access) or advanced error correction.