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Digital Logic Design Lab 7

This document outlines the objectives and procedures for Lab 7 of the Digital Logic Design course at the International University, focusing on Counter Integrated Circuits (ICs). Students will design and implement synchronous counters using D Flip Flops and investigate decade counters like the 74XX90 and 74HC390, including their operations and configurations. The lab emphasizes simulation results and practical applications of counting mechanisms in digital circuits.

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Lý Khải Minh
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29 views

Digital Logic Design Lab 7

This document outlines the objectives and procedures for Lab 7 of the Digital Logic Design course at the International University, focusing on Counter Integrated Circuits (ICs). Students will design and implement synchronous counters using D Flip Flops and investigate decade counters like the 74XX90 and 74HC390, including their operations and configurations. The lab emphasizes simulation results and practical applications of counting mechanisms in digital circuits.

Uploaded by

Lý Khải Minh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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lOMoARcPSD|33450594

Digital Logic Design Lab 7

Digital Logic Design (International University - VNU-HCM)

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lOMoARcPSD|33450594

INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Digital Logic Design Laboratory

Lab 7

Counter ICs

Full name: …………………………………………….


Student number: ………………………………….
Class: ……………………………………………….......
Date: …………………………………………………....

Digital Logic Design Laboratory 1-7

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lOMoARcPSD|33450594

INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

I. Objectives
In this laboratory, students will study:
- Understand the operation of Counter of IC
- Use a Counter of IC and design/implement a circuit.
II. Procedure
1. Design and implement a synchronous counter by the given state diagram
Design and implement a synchronous 3-bit counter shown in the given diagram as
shown in Figure 1 using D Flip Flops

Figure 1. State diagram


Transition Table
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 Q0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0
The expressions of D2, D1, D0:
D0 = Q 2 Q 0 D1 = Q2 Q1Q0 + Q2Q1 Q0 D2 = Q 2Q1Q0

Digital Logic Design Laboratory 2-7

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lOMoARcPSD|33450594

INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Implement the circuit via simulation software and paste the result in here

Make comment on the results:


− The transition table shown accurately represents the expected state transitions for
the 3-bit synchronous counter using D flip-flops. For each present state (Q2, Q1,
Q0), the table correctly lists the next state and the corresponding inputs to the D
flip-flops (D2, D1, D0).
− The simulation confirms that the counter transitions through all eight states (000
to 111) in the correct sequence. The counter resets to 000 after reaching 111,
demonstrating the loop-back nature of the design.
2. Decade counter 74XX90
a. Investigate decade counter 74XX90
IC 74XX90 contains a divide-by-two counter and a divide-by-five counter as shown in
Figure 2. The truth table for the counter 74XX90 is shown in Table 1.
• Connect Clock signal to 𝐂𝐏𝐎
• Connect Q0 to 𝐂𝐏𝟏
• Connect MS1, MS2, MR1, MR2 to switches for controlling operations
• Connect outputs (Q0, Q1, Q2, Q3) to BCD to 7-segment display block

Figure 2. IC 74XX90
Table 1. Truth table for 74XX90

Digital Logic Design Laboratory 3-7

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lOMoARcPSD|33450594

INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Implement the circuit (Figure 2) via simulation software and paste the result in here

Make comment on the results: The decade counter 74XX90 counts BCD numbers,
which counts from 0 to 9. The MS1 and MS2 are two modes, which set the IC started to
count. The MR1 and MR2 are two modes, which reset the IC to 0. CP0 and CP1 are two
clock pulses, which are active-low inputs.
b. Adjust the circuit to make a MOD-7 counter (counting from 0 to 6)
Implement the circuit via simulation software and paste the result in here

Digital Logic Design Laboratory 4-7

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lOMoARcPSD|33450594

INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Make comment on the results (show the way to implement): This is a MOD – 7 –
counter, which counts from 0 to 6 and reset to 0 when it reaches 7. We use an AND gate
to detect the count of 7. When Q0, Q1, and Q2 are 1, and Q3 is 0, the AND gate will
output a high signal, which will reset the counter to 0 when it reaches 7.
3. Decade counter 74HC390
a. Investigate Dual 4-Bit Decade Counter
▪ IC 74HC390 includes 2 decimal counters
▪ Ra, Rb: Clear (high level active)
▪ QA, QB, QC and QD: outputs of the MOD-10 counter

Figure 3. 74HC390 Counter having M=100


- The outputs QA, QB, QC and QD are connected to BCD TO 7-SEGMENT DISPLAY
- The Ra, Rb inputs are connected to switches to control the circuit operation.
Implement the circuit (Figure 3) via simulation software and paste the result in here

Digital Logic Design Laboratory 5-7

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lOMoARcPSD|33450594

INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

Make comment on the results:


− The Ra, and Rb in 74HC390 are two modes, which reset two BCD to 7-segment
display. The Ra resets the first display, and Rb resets the second display.
− When the clock is turned on, the circuit will start to count from 0 to 9 on the first
display. After it counts to 9 and returns to 0, the second BCD to 7-segment
display will be displayed as a cycle of the first display.
4. 4-Bit Binary Up/Down Counter 74HC193
▪ IC 74HC390 includes 2 decimal counters
▪ The outputs Q0, Q1, Q2, Q3 and TCu, TCd are connected to 7 Seg BCD and LEDs
▪ The inputs are connected to switches. Set D3D2D1D0 are equal to 0000
▪ 1Hz clock is used for COUNT UP (CPu) and COUNT DOWN (CPd)

Implement the circuit via simulation software and paste the result in here

Based on the circuit in the simulation software, fill in and answer the following table
and question.

Digital Logic Design Laboratory 6-7

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lOMoARcPSD|33450594

INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

R PL UP DOWN FUNCTION
0 1 CLK 1 Count up when clock pulses
0 1 1 CLK Count down when clock pules
0 1→0 X X Load the value from D0 – D3
0→1 1 X X Reset the counter
0 1 1 1 Counter stops
What is the function of TCu and TCd?
− TCu (Terminal Count up): This output goes high when the counter reaches its
maximum count and then wraps around to 0. It indicates that an overflow has occurred
while counting up.
− TCd (Terminal Count down): This output goes high when the counter reaches 0 and
then wraps around to its maximum count. It indicates that an underflow has occurred
while counting down.

Digital Logic Design Laboratory 7-7

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