Introduction to Electrical
Engineering
Course Code: EE 103
Department: Electrical Engineering
Instructor Name: B. G. Fernandes
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 1
Digital Electronics
• Two ways of representing the numerical values of any quantity
• Analog → most of the physical quantities
→ vary over a continuous range of values
• Digital → Discrete → digital clock
→ reliability is more
→ easier to design S
• Output is 0 or 1
‘S’ closed 𝑉𝑉𝑖𝑖𝑖𝑖 ≈ 𝑉𝑉𝑜𝑜 We need only the ``range’’ and Vo
‘S’ open 𝑉𝑉𝑜𝑜 = 0 not the ``exact’’ value of V or I Vin
Number Base Characters
System
Binary 2 0 and 1
Octal 8 0–7
Decimal 10 0–9
Hexadecimal 16 0 – 9, A – F
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 2
Boolean Algebra and Identities
• AND, OR and NOT are the basic functions Binary addition
a b sum carry
OR AND NOT
𝐴𝐴 + 0 = 𝐴𝐴 𝐴𝐴𝐴 = 0 𝐴𝐴 + 𝐴𝐴̅ = 1 0 0 0 0
𝐴𝐴 + 1 = 1 𝐴𝐴𝐴 = 𝐴𝐴 𝐴𝐴𝐴𝐴̅ = 0 0 1 1 0
𝐴𝐴 + 𝐴𝐴 = 𝐴𝐴 𝐴𝐴𝐴𝐴 = 𝐴𝐴 𝐴𝐴̅ = 𝐴𝐴 1 0 1 0
𝐴𝐴 + 𝐴𝐴̅ = 1 𝐴𝐴𝐴𝐴̅ = 0 1 1 0 1
Realization of Logic Function using Logic Gates
• AB + AC can be realized using 2 AND & 1 OR gate 3 gates
• Alternatively, AB + AC A(B + C) 1 OR and 1 AND gate 2 gates
• Reduce following logic expression using Boolean Algebra
𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶̅ 𝐴𝐴 + 𝐵𝐵� + 𝐶𝐶 = 𝐴𝐴 1 + 𝐵𝐵� + 𝐶𝐶 + 𝐵𝐵� + 𝐶𝐶̅ + 𝐵𝐵� 1 + 𝐶𝐶 + 𝐶𝐶̅
= 𝐴𝐴 + 𝐵𝐵�
• Many a times, it is not convenient to use Boolean Algebra
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 3
Karnaugh Map (K – Map )
• Means of showing a relationship between logic input and desired output
• Squares are labelled so that horizontally adjacent squares differ only in one variable. Similarly,
vertically adjacent squares differ only in one variable.
𝐴𝐴 𝐵𝐵 𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂 𝐵𝐵� 𝐵𝐵
0 0 1 𝐴𝐴̅𝐵𝐵� + 𝐴𝐴𝐵𝐵
̅
𝐴𝐴̅
0 1 1
1 1
= 𝐴𝐴̅ 𝐵𝐵� + 𝐵𝐵
(00) (01)
1 0 0
= 𝐴𝐴̅
𝐴𝐴 0 0
1 1 0 (10) (11)
• Different from K-map: as B changes and 𝐴𝐴̅ does not change Drop the variable which has changed
𝐴𝐴̅𝐵𝐵� ̅
𝐴𝐴𝐵𝐵 𝐴𝐴𝐴𝐴 𝐴𝐴𝐵𝐵�
𝐶𝐶̅ 1 0 0 1 𝑋𝑋 = 𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴𝐵𝐵𝐵𝐵
̅
C 0 1 0 0
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 4
�𝑫𝑫
𝑪𝑪 � �𝑫𝑫
𝑪𝑪 𝑪𝑪𝑪𝑪 �
𝑪𝑪𝑫𝑫 �𝑫𝑫
𝑪𝑪 � �𝑫𝑫
𝑪𝑪 𝑪𝑪𝑪𝑪 �
𝑪𝑪𝑫𝑫 �𝑫𝑫
𝑪𝑪 � �𝑫𝑫
𝑪𝑪 𝑪𝑪𝑪𝑪 �
𝑪𝑪𝑫𝑫
� 𝑩𝑩
𝑨𝑨 � 1 1 � 𝑩𝑩
𝑨𝑨 � � 𝑩𝑩
𝑨𝑨 �
Instead
� 𝑩𝑩
𝑨𝑨 1 1 � 𝑩𝑩
𝑨𝑨 1 1 � 𝑩𝑩
𝑨𝑨 1 1
𝑨𝑨𝑨𝑨 1 1 𝑨𝑨𝑨𝑨 1 1 1 𝑨𝑨𝑨𝑨 1 1 1
�
𝑨𝑨𝑩𝑩 1 1 �
𝑨𝑨𝑩𝑩 1 �
𝑨𝑨𝑩𝑩 1
𝑋𝑋 = 𝐴𝐴̅𝐵𝐵𝐶𝐶
� + 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐵𝐵� 𝐷𝐷
� 𝑋𝑋 = 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴𝐵𝐵𝐵𝐵
̅ + 𝐴𝐴𝐴𝐴𝐴𝐴 𝑋𝑋 = 𝐵𝐵𝐵𝐵 + 𝐴𝐴𝐴𝐴𝐶𝐶̅ + 𝐴𝐴𝐴𝐴𝐴𝐴
Suppose in 3rd row all are 1s → 𝑋𝑋 = 𝐴𝐴𝐴𝐴
2nd row and 3rd row are all 1s → 𝑋𝑋 = 𝐵𝐵
Suppose 2nd and 3rd rows are all 1s and 1st row 2nd
column is also 1 → 𝑋𝑋 = 𝐵𝐵 + 𝐴𝐴̅𝐵𝐵� 𝐶𝐶𝐷𝐷
̅
Instead loop the isolated 1 with 2nd row 2nd column → 𝑋𝑋 = 𝐵𝐵 + 𝐴𝐴̅𝐶𝐶𝐷𝐷
̅
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 5
Minterms
• It is convenient to express a Boolean Truth Table
function in its sum-of-minterms
𝐴𝐴 𝐵𝐵 𝐶𝐶 Decimal F
• � + A𝐵𝐵� 𝐶𝐶̅ + A𝐵𝐵𝐶𝐶
F = Ā 𝐵𝐵𝐶𝐶 � + A𝐵𝐵𝐶𝐶̅ +ABC
equivalent
0 0 0 0 0
• It is sometimes convenient to express 0 0 1 1 1
the function in the following brief 0 1 0 2 0
notation: 0 1 1 3 0
F(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑(1, 4, 5, 6, 7) 1 0 0 4 1
where the numerals correspond to the minterms 1 0 1 5 1
(with ‘1’ for true and ‘0’ for complement) 1 1 0 6 1
• ∑ stands for OR-ing of the terms 1 1 1 7 1
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 6
Boolean Function Notation/Representations
Consider the function:
F(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑(1, 4, 5, 6, 7)
𝐴𝐴 𝐵𝐵 𝐶𝐶 Decimal F
equivalent
0 0 0 0 0 𝐹𝐹 𝐵𝐵� 𝐶𝐶̅ �
𝐵𝐵𝐶𝐶 𝐵𝐵𝐵𝐵 𝐵𝐵𝐶𝐶̅
0 0 1 1 1 (000) 0 (001) 1 (011) 3 (010) 2
𝐴𝐴̅ 0 1 0 0
0 1 0 2 0
0 1 1 3 0 (100) 4 (101) 5 (111) 7 (110) 6
𝐴𝐴
1 0 0 4 1 1 1 1 1
1 0 1 5 1
1 1 0 6 1 �
F = 𝐴𝐴 + 𝐵𝐵𝐶𝐶
1 1 1 7 1
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 7
K-map Minimization
𝐹𝐹 𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐷𝐷 = ∑(1, 3, 4, 11, 12, 13, 14, 15)
CD
𝟎𝟎𝟎𝟎 𝟎𝟎𝟎𝟎 𝟏𝟏𝟏𝟏 𝟏𝟏𝟏𝟏
AB
𝟎𝟎𝟎𝟎 0 1 1 0
𝟎𝟎𝟎𝟎 1 0 0 0
𝟏𝟏𝟏𝟏 1 1 1 1
𝟏𝟏𝟏𝟏 0 0 1 0
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 8
Steps to be followed
• Construct the K map and place 1s in that square corresponding to the 1s in truth table. Place
0s in other squares.
• Loop those 1s which are not adjacent to any other 1s. These are isolated 1s. Next, look for
those 1s which are adjacent to only one other 1. Loop any pair containing such a 1.
• Loop any octet even if some of 1s have already been looped.
• Loop any quad that contain one or more 1s which have not yet been looped.
• Loop any pairs necessary to include any 1s that have not yet been looped. Make sure to use
the minimum number of loops.
• Form the OR sum of all terms.
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 9
Half Adder
Computers perform addition operation on 2 binary numbers at a time, each binary number can have
several binary digits.
• Process starts by adding LSBs.
• Adds 2 bits (A & B), generate ‘sum’ and carry.
• Half adder
A B S C
0 0 0 0 ̅
𝑆𝑆 = 𝐴𝐴𝐵𝐵� + 𝐴𝐴𝐵𝐵
0 1 1 0
𝐶𝐶 = 𝐴𝐴𝐴𝐴
1 0 1 0
Half adder
1 1 0 1
• While adding the next bit, carry generated (Ci) in the previous stage has to be added.
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 10
Full Adder
Sum = A + B + Ci
A B Ci Sum Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 11
𝐴𝐴̅𝐵𝐵� ̅
𝐴𝐴𝐵𝐵 𝐴𝐴𝐴𝐴 𝐴𝐴𝐵𝐵�
𝐴𝐴̅𝐵𝐵� ̅
𝐴𝐴𝐵𝐵 𝐴𝐴𝐴𝐴 𝐴𝐴𝐵𝐵�
0 1 0 1
𝐶𝐶�𝑖𝑖 𝐶𝐶�𝑖𝑖 1
(000) (001) (011) (010)
1 0 1 0 𝐶𝐶𝑖𝑖 1 1 1
𝐶𝐶𝑖𝑖
(100) (101) (111) (110)
̅ 𝐶𝐶�𝑖𝑖 + A𝐵𝐵� 𝐶𝐶�𝑖𝑖 + 𝐴𝐴𝐴𝐴𝐶𝐶𝑖𝑖 + 𝐴𝐴̅𝐵𝐵𝐶𝐶
𝑆𝑆𝑢𝑢𝑢𝑢 = 𝐴𝐴𝐵𝐵 � 𝑖𝑖 𝐶𝐶𝑜𝑜 = 𝐴𝐴𝐴𝐴 + 𝐶𝐶𝑖𝑖 𝐵𝐵 + 𝐶𝐶𝑖𝑖 𝐴𝐴
Instead
̅ + 𝐴𝐴𝐵𝐵� + 𝐶𝐶𝑖𝑖 𝐴𝐴𝐴𝐴 + 𝐴𝐴̅𝐵𝐵�
= 𝐶𝐶�𝑖𝑖 𝐴𝐴𝐵𝐵
̅ + 𝐴𝐴𝐵𝐵�
𝐶𝐶𝑜𝑜 = 𝐴𝐴𝐴𝐴 + 𝐶𝐶𝑖𝑖 𝐴𝐴𝐵𝐵
= 𝐶𝐶�𝑖𝑖 𝑍𝑍 + 𝐶𝐶𝑖𝑖 𝑍𝑍̅
Z
Where, Z = o/p of half adder with A & B as inputs.
Sum → o/p of another half adder with Ci & Z as inputs.
Ci → Carry of previous stage
= AB
𝐶𝐶𝑜𝑜 = 𝐶𝐶𝑖𝑖 𝑍𝑍 + 𝐴𝐴𝐴𝐴
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 12
Don't care condition M 𝐹𝐹1 𝐹𝐹2 𝐹𝐹3
Door
(open)
Some logic circuits can be designed so that there are certain 0 0 0 0 0
input conditions for which there are no specified output levels.
0 0 0 1 1
0 0 1 0 1
• Because their input conditions will never
0 0 1 1 X
occur
0 1 0 0 1
• Certain combinations of input, where we
‘don’t care’ whether the o/p is high or low 0 1 0 1 X
0 1 1 0 X
• Example: Logic circuit that control an elevator door of a 3 story
0 1 1 1 X
building
• 4 Inputs 1 0 0 0 0
• M ⇒ 0 when stopped 1 0 0 1 0
⇒ 1 when moving 1 0 1 0 0
• F1, F2, F3 ⇒ Generally low 1 0 1 1 X
⇒ Go high only when the elevator is positioned at a 1 1 0 0 0
level of that particular floor. 1 1 0 1 X
1 1 1 0 X
∴ only one of them can be high 1 1 1 1 X
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 13
F2 F3 F2 F3
00 01 11 10 00 01 11 10
M F1 M F1
00 0 1 X 1 00 0 1 1 1
01 1 X X X 01 1 1 1 1
11 0 X X X 11 0 0 0 0
10 0 0 X 0 10 0 0 0 0
What’s best for minimizing the output expression? � 1 + 𝑀𝑀𝐹𝐹
Open=𝑀𝑀𝐹𝐹 � 3 + 𝑀𝑀𝐹𝐹
� 2 = 𝑀𝑀(𝐹𝐹
� 1 + 𝐹𝐹2 + 𝐹𝐹3 )
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 14
Don't care Example:
Advantage of using
Don’t cares:
simpler expressions
Source: Morris Mano & M.
Ciletti: Digital Design, 5 Ed.,
Pearson
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 15
Multiplexer (MUX)
• Logic circuit accepts several data inputs. But allows only one of them at a time to get
through the o/p.
• Routing of the desired input to the o/p is done by ‘select’ inputs or ‘address’ inputs.
Two-to-one-line multiplexer
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 16
Multiplexer: Four-to-one-line multiplexer
𝑆𝑆1 𝑆𝑆0 𝑌𝑌
0 0 𝐼𝐼0
0 1 𝐼𝐼1
1 0 𝐼𝐼2
1 1 𝐼𝐼3
Function table
Logic diagram
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 17
8-1 Multiplexer
8-1 Mux: IC 74151
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 18
8-1 Multiplexer vs Discrete Gates for Logic Realization: Footprint comparison
NOT Gate: IC 7404
8-1 Mux: IC 74151
3 input NAND Gate: IC 7410
TG: Transmission Gate
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 19
Implementation of Boolean expressions using
Multiplexers (MUX)
• In a practical circuit, the number of ICs should be minimized; K-map solution requires a
combination of gates, with differing number of inputs - which in most cases will not
result in the minimum number of ICs.
Another Solution:
• A 4-to-1 MUX can directly implement the Truth Table of a TWO variable function using
its TWO selection inputs and Input lines.
• Similarly, an 8-to-1 MUX can directly implement the Truth Table of a THREE variable
function using its THREE selection inputs;
• A 16-to-1 MUX can implement the Truth table of a FOUR variable function using its FOUR
selection inputs.
• It is more efficient to implement a Boolean function of n variables using a MUX that has
(n-1) selection inputs.
EE 103: Introduction to Electrical Engineering Prof. B. G. Fernandes 20
