UNIT - III

I/O INTERFACING

Title Contents

Unit – III Contents Memory Interfacing and I/O

interfacing Parallel
communication interface Serial
communication interface
D/A and A/D Interface
Timer
Keyboard /display controller
Interrupt controller
DMA controller
Programming and applications
Case studies:
Traffic Light control,
LED display LCD display,
Keyboard display interface and Alarm Controller.
Text books: 1. Yu-Cheng Liu, Glenn A.Gibson, ―Microcomputer
Systems: The 8086 / 8088 Family- Architecture,
Programming and Design‖, Second Edition,
Prentice Hall of India, 2007.

2. Mohamed Ali Mazidi, Janice Gillispie Mazidi,

Rolin McKinlay, ―The 8051 Microcontroller
and Embedded Systems: Using Assembly and
C‖, Second Edition, Pearson Education, 2011
Reference books: 1. Doughlas V.Hall, ―Microprocessors and
Interfacing, Programming and Hardware‖,
TMH,2012

Prepared By Verified By

Dr.Venkatesh kanna T./ Asst prof / ECE

Mrs.C.Rajani Assit.Prof/ ECE

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3.1 MEMORY INTERFACING AND I/O INTERFACING

3.1.1 MEMORY INTERFACING

We have four common types of memory

Read only memory (ROM)
Flash memory (EEPROM)
Static Random access memory (SARAM)
Dynamic Random access memory (DRAM)

Pin connections
Common to all memory devices are: The address input, data output or
input/outputs, selection input and control input used to select a read or
write operation.

Address connections
All memory devices have address inputs that select a memory location
within the memory device.
Address inputs are labeled from A0 to An.

Data connections
All memory devices have a set of data outputs or
input/outputs. Today many of them have bi-directional
common I/O pins.

Selection connections
Each memory device has an input that selects or enables the memory
device.
This kind of input is most often called a chip select (CS), chip enable (CE) or
simply select (S) input.

Fig 3.1: Memory component illustrating the address, data and control connections

3.1.1.1 ROM
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 It read only memory permanently stores programs and data and data
was always present, even when power is disconnected. It is also called as
nonvolatile memory.

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RAM

RAM memory device has either one or two control inputs. If there is one
control input it is often called R/W.
This pin selects a read operation or a write operation only if the device is
selected by the selection input (CS).
If the RAM has two control inputs, they are usually labeled WE or W and
OE or G. (WE) write enable must be active to perform a memory write
operation and OE must be active to perform a memory read operation.
When these two controls WE and OE are present, they must never be
active at the same time.

3.1.1.2 EPROM

Erasable Programmable Read Only Memory is also erasable if exposed to

high intensity ultraviolet light for about 20 minutes or less, depending
upon the type of EPROM as shown in figure 3.2.
We have PROM (Programmable Read Only Memory)

RMM

Read Mostly Memory is also called the flash memory.

The flash memory is also called as an EEPROM (Electrically Erasable
Programmable ROM), EAROM (Electrically Alterable ROM), or a NOVROM
(Nonvolatile ROM).
These memory devices are electrically erasable in the system, but require
more time to erase than a normal RAM.

Fig 3.2: Pin configuration of 2716 EPROM

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 A0 –A10 ADDRESSES
PD/PGM POWER DOWN PROGRAM/
CS CHIP SELECT
O0-O7 OUT PUTS
Table 3.1
3.1.1.3 Static Random access memory (SARAM)

Static RAM memory device retain data for as long as DC power is applied.
Because no special action is required to retain stored data, these devices
are called as static memory.
They are also called volatile memory because they will not retain data
without power. The main difference between a ROM and RAM is that a
RAM is written under normal operation, while ROM is programmed outside
the computer and is only normally read.
The SRAM stores temporary data and is used when the size of read/write
memory is relatively small.
The control inputs of this RAM are slightly different from those presented
earlier.
The OE pin is labeled G, the CS pin S and the WE pin W. This 4016 SRAM
device has 11 address inputs and 8 data input/output connections

Block Diagram
Block diagram and pin diagram are shown in figure 3.3 and 3.4.

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 Fig 3.3: Block diagram
Pin Diagram

Fig 3.4: Pin configuration of 4016 SRAM

A 0 –A 10 ADDRESSES
_
WRITE ENABLE
W
_
CHIP SELECT
S

DQ 0 - DQ 8 DATA IN / DATA OUT

_
OUT PUT ENABLE
G
Vss GROUND
Vcc + 5 V SUPPLY
Table 3.2
3.1.1.4 Dynamic RAM

Whenever a large capacity memory is required in a microcomputer system,

the memory subsystem is generally designed using dynamic RAM because
there are various advantages of dynamic RAM is shown in figure 3.5.
The basic dynamic RAM cell uses a capacitor to store the charge as a
representation of data.
This capacitor is manufactured as a diode that is reverse biased so that the
storage capacitance comes into the picture.
This storage capacitance is utilized for storing the charge representation of
data but the reverse-biased diode has leakage current that tends to
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discharge the capacitor

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 giving rise to the possibility of data loss. To avoid this possible data loss,
the data stored in a dynamic RAM cell must be refreshed after a fixed time
interval regularly.
The process of refreshing the data in RAM is called as Refresh cycle.
The refresh activity is similar to reading the data from each and every cell
of memory, independent of the requirement of microprocessor.
During this refresh period all other operations related to the memory
subsystem are suspended.
Hence the refresh activity causes loss of time, resulting in reduces system
performance.
However keeping in view the advantages of dynamic RAM, like low power
consumption, high packaging density and low cost, most of the advanced
computing system are designed using dynamic RAM, at the cost of
operating speed.
A dedicated hardware chip called as dynamic RAM controller is the most
important part of the interfacing circuit. The Refresh cycle is different from
the memory read cycle in the following aspects.
The memory address is not provided by the CPU address bus; rather it is
generated by a refresh mechanism counter called as refresh counter.
Unlike memory read cycle, more than one memory chip may be enabled at
a time so as to reduce the number of total memory refresh cycles.
The data enable control of the selected memory chip is deactivated, and
data is not allowed to appear on the system data bus during refresh, as
more than one memory units are refreshed simultaneously. This is to
avoid the data from the different chips to appear on the bus
simultaneously.
Memory read is either a processor initiated or an external bus master
initiated and carried out by the refresh mechanism.

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Fig 3.5: Dynamic RAM controller

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3.2 I/O Interfacing
Input and output ports are shown in figure 3.6 and 6.7
3.2.1 I/O port

Fig 3.6: I/O

port
3.2.2 O/P port

Fig 3.7: O/P port

3.2.3 I/O Interfacing Techniques

I/O devices can be interfaced in two ways

Memory mapped I/O device.
Standard I/O mapped I/O of device or isolated I/O mapping.

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 Table 3.3

3.2 PARALLEL INTERFACING 8255-PPI

8255 - Programmable Peripheral Input-Output port.

The parallel input-output port chip 8255 is also called as programmable

peripheral input-output port. The Intel‘s 8255 is designed for use with Intel‘s 8-
bit, 16-bit and higher capability microprocessors. It has 24 input/output lines
which may be individually programmed in two groups of twelve lines each, or
three groups of eight lines. The two groups of I/O pins are named as Group A and
Group B. Each of these two groups contains a subgroup of eight I/O lines called
as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A
contains an 8-bit port A along with a 4-bit port. C upper. The port A lines are
identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7.
Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit
port C with lower bits PC0- PC3. The port C upper and port C lower can be used in
combination as an 8-bit port C. Both the port C are assigned the same address.
Thus one may have either three 8- bit I/O ports or two 8-bit and two 4-bit ports
from 8255. All of these ports can function independently either as input or as
output ports. This can be achieved by programming the bits of an internal
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register of 8255 called as control word register ( CWR ).

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 The internal block diagram and the pin configuration of 8255 are shown in
Figure 1. The 8-bit data bus buffer is controlled by the read/write control logic.
The read/write control logic manages all of the internal and external transfers of
both data and control words. RD, WR, A1, A0 and RESET are the inputs provided
by the microprocessor to the READ/ WRITE control logic of 8255. The 8-bit, 3-
state bidirectional buffer is used to interface the 8255 internal data bus with the
external system data bus. This buffer receives or transmits data upon the
execution of input or output instructions by the microprocessor. The control
words or status information is also transferred through the buffer.

Signal description of 8255

PA7-PA0: These are eight port A lines that acts as either latched output or
buffered input lines depending upon the control word loaded into the control
word register.

PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or
input buffers lines. This port also can be used for generation of handshake lines
in mode 1 or mode 2.

PC3-PC0 : These are the lower port C lines, other details are the same as PC7-
PC4 lines.

PB0-PB7 : These are the eight port B lines which are used as latched output lines
or buffered input lines in the same way as port A.

RD : This is the input line driven by the microprocessor and should be low to
indicate read operation to 8255.

WR : This is an input line driven by the microprocessor. A low on this line

indicates write operation.

CS : This is a chip select line. If this line goes low, it enables the 8255 to respond
to RD and WR signals, otherwise RD and WR signal are neglected.

A1-A0 : These are the address input lines and are driven by the microprocessor.
These lines A1-A0 with RD, WR and CS from the following operations for 8255.
These address lines are used for addressing any one of the four registers, i.e.
three ports and a control word register as given in table below.

In case of 8086 systems, if the 8255 is to be interfaced with lower order data
bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.

D0-D7 : These are the data bus lines those carry data or control word to/from the
microprocessor.

RESET : A logic high on this line clears the control word register of 8255. All
ports are set as input ports by default after reset.
A1 A0 Input (Read) cycle
RD WR CS
0 1 0 0 0 Port A to Data bus
0 1 0 0 1 Port B to Data bus
0 1 0 1 0 Port C to Data bus
1
0 1 0 1 CWR to Data bus

RD WR CS A1 A0 Output (Write) cycle

1 0 0 0 0 Data bus to Port A
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1 0 0 0 1 Data bus to Port B
1 0 0 1 0 Data bus to Port C
1 0 0 1 1 Data bus to CWR

CS A1 A0 Function
RD WR
X X 1 X X Data bus tristated

1 1 0 X X Data bus tristated

Figure 1: 8255A Pin Configuration Fig 2 : Signals of 8255

3.1.3 Block Diagram of 8255 (Architecture)

It has

1. Data bus buffer

2. Read Write control logic

3. Group A and Group B controls

4. Port A, B and C

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Block Diagram of 8255 (Architecture)

Figure 4 : Block Diagram of 8255 (Architecture)

3.1.3.1 Data bus buffer: This is a tristate bidirectional buffer used to interface the
8255 to system data bus. Data is transmitted or received by the buffer on
execution of input or output instruction by the CPU. Control word and status
information are also transferred through this unit.

3.1.3.2 Read/Write control logic: This unit accepts control signals ( RD, WR ) and
also inputs from address bus and issues commands to individual group of control
blocks ( Group A, Group B).

It has the following pins.

 CS – Chip select : A low on this PIN enables the communication between

CPU and 8255.
 RD (Read) – A low on this pin enables the CPU to read the data in the
ports or the status word through data bus buffer.
 WR ( Write ) : A low on this pin, the CPU can write data on to the ports or
on to the control register through the data bus buffer.
 RESET: A high on this pin clears the control register and all ports are set
to the input mode
 A0 and A1 ( Address pins ): These pins in conjunction with RD and WR pins
control the selection of one of the 3 ports.
3.1.3.3 Group A and Group B controls : These block receive control from the CPU
and issues commands to their respective ports. Group A - PA and PCU ( PC7 –
PC4) Group B - PCL ( PC3 – PC0) Control word register can only be written into
no read operation of the CW register is allowed.
 Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It
can be programmed in 3 modes – mode 0, mode 1, mode 2.
 Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch.
It can be programmed in mode 0, mode1.
 Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer.
This port can be divided into two 4 bit ports and can be used as control
signals for port A and port
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B. it can be programmed in mode 0.

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 Figure 3 : Control Word Format of 8255

Modes of Operation of 8255

These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset
mode (BSR).

In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode
only port C (PC0-PC7) can be used to set or reset its individual port bits.

Under the I/O mode of operation, further there are three modes of operation of
8255, so as to support different types of applications, mode 0, mode 1 and
mode 2.

BSR Mode:

In this mode any of the 8-bits of port C can be set or reset depending on
D0 of the control word. The bit to be set or reset is selected by bit select flags
D3, D2 and D1 of the CWR as given in table.

Figure 5 : BSR Mode Control Word Register Format

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D3 D2 D1 Selected bits of port C

0 0 0 D0
1 0 0 D1
0 1 1 D2
0 1 1 D3
0 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

I/O Modes :

a) Mode 0 ( Basic I/O mode ):

This mode is also called as basic input/output mode. This mode provides simple
input and output capabilities using each of the three ports. Data can be simply
read from and written to the input and output ports respectively, after
appropriate initialization.

The salient features of this mode are as listed below:

1. Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upper and
lower ) are available. The two 4-bit ports can be combinedly used as a third 8-
bit port. 2. Any port can be used as an input or output port.
2. Output ports are latched. Input ports are not latched.
3. A maximum of four ports are available so that overall 16 I/O configuration are
possible. All these modes can be selected by programming a register internal
to 8255 known as CWR. The control word register has two formats. The first
format is valid for I/O modes of operation, i.e. modes 0, mode 1 and mode 2
while the second format is valid for bit set/reset (BSR) mode of operation.

Mode 0 Control Word Register Format

 Port A and Port C acting as O/P.

 Port B acting as I/P
D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 1 0

D7 – set Mode set flag , 1–

I/O Mode D6,D5 -

set either Mode 0 , Mode 1 , Mode

0 0 – Mode

0 if D4 is 0 - PA as

output

if D3 is 0 - PCU as output

if D2 is 0 - set mode 0 of PB
154
if D1 is 1 - PB as input

if D0 is 0 - PCL as output

Figure 6 : Mode 0

b) Mode 1: ( Strobed input/output mode )

In this mode the handshaking control the input and output action of the
specified port. Port C lines PC0-PC2, provide strobe or handshake lines for port B.
This group which includes port B and PC0-PC2 is called as group B for Strobed
data input/output. Port C lines PC3-PC5 provide strobe lines for port A. This group
including port A and PC3-PC5 from group A. Thus port C is utilized for generating
handshake signals. The Salient Features Of Mode 1:

1. Two groups – group A and group B are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
3. The 8-bit data port can be either used as input and output port. The inputs
and outputs both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port
B and PC3-PC5 are used to generate control signals for port A. the lines
PC6, PC7 may be used as independent data lines.
Input control signal definitions (mode 1 ):

STB( Strobe input ) – If this lines falls to logic low level, the data available at
8- bit input port is loaded into input latches.

IBF ( Input buffer full ) – If this signal rises to logic 1, it indicates that data has
been loaded into latches, i.e. it works as an acknowledgement. IBF is set by a low
on STB and is reset by the rising edge of RD input.

INTR ( Interrupt request ) – This active high output signal can be used to
interrupt the CPU whenever an input device requests the service. INTR is set by a
high STB pin and a high at IBF pin. INTE is an internal flag that can be controlled
by the bit set/reset mode of either PC4(INTEA) or PC2(INTEB) as shown in Figure
7. INTR is reset by a falling edge of RD input. Thus an external input device can
be request the service of the processor by putting the data on the bus and
sending the strobe signal.

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 Figure7 : Input control signal definitions in Mode 1

Figure 8 : Mode 1 Strobed Input Data Transfer

Output control signal definitions (mode 1) :

OBF (Output buffer full ) – This status signal, whenever falls to low, indicates
that CPU has written data to the specified output port. The OBF flip-flop will be
set by a rising edge of WR signal and reset by a low going edge at the ACK input.

ACK ( Acknowledge input ) – ACK signal acts as an acknowledgement to be

given by an output device. ACK signal, whenever low, informs the CPU that the
data transferred by the CPU to the output device through the port is received by
the output device.

INTR ( Interrupt request ) – Thus an output signal that can be used to interrupt
the CPU when an output device acknowledges the data received from the CPU.
INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR
input. The INTEA and INTEB flags are controlled by the bit set-reset mode of PC6
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and PC2 respectively.

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 Figure 9 : Output control signal definitions Mode 1

Figure 10 : Mode 1 Strobed Data Output

C) Mode 2 ( Strobed bidirectional I/O ):

This mode of operation of 8255 is also called as strobed bidirectional I/O.

This mode of operation provides 8255 with an additional features for
communicating with a peripheral device on an 8-bit data bus. Handshaking
signals are provided to maintain proper data flow and synchronization between
the data transmitter and receiver. The interrupt generation and other functions
are similar to mode 1.

In this mode, 8255 is a bidirectional 8-bit port with handshake signals.

The Rd and WR signals decide whether the 8255 is going to operate as an input
port or output port.

The Salient features of Mode 2 of 8255 are listed as follows:

1. The single 8-bit port in group A is available.

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2. The 8-bit port is bidirectional and additionally a 5-bit control port is
available.
3. Three I/O lines are available at port C.( PC2 – PC0 )

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 4. Inputs and outputs are both latched.
5. The 5-bit control port C (PC3-PC7) is used for generating / accepting
handshake signals for the 8-bit data transfer on port A.
Control signal definitions in mode 2:

INTR – (Interrupt request) As in mode 1, this control signal is active high and is
used to interrupt the microprocessor to ask for transfer of the next data byte
to/from it. This signal is used for input ( read ) as well as output ( write )
operations.

Control Signals for Output operations:

OBF ( Output buffer full ) – This signal, when falls to low level, indicates that the
CPU has written data to port A.

ACK ( Acknowledge ) This control input, when falls to logic low level, acknowledges
that the previous data byte is received by the destination and next byte may be
sent by the processor. This signal enables the internal tristate buffers to send
the next data byte on port A.

INTE1 ( A flag associated with OBF ) This can be controlled by bit set/reset mode with
PC6.

Control signals for input operations :

STB (Strobe input ) A low on this line is used to strobe in the data into the input
latches of 8255.

IBF ( Input buffer full ) When the data is loaded into input buffer, this signal rises to
logic ‗1‘. This can be used as an acknowledge that the data has been received
by the receiver. The waveforms in Figure 12 show the operation in Mode 2 for
output as well as input port.

Note: WR must occur before ACK and STB must be activated before RD. The
following Figure 12 shows a schematic diagram containing an 8-bit bidirectional
port, 5-bit control port and the relation of INTR with the control pins. Port B can
either be set to Mode 0 or 1 with port A( Group A ) is in Mode 2. Mode 2 is not
available for port B. The INTR goes high only if either IBF, INTE2, STB and RD go
high or OBF, INTE1, ACK and WR go high. The port C can be read to know the
status of the peripheral device, in terms of the control signals, using the normal
I/O instructions.

Figure 11 : Mode 2 control word

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 Figure 12 : Mode 2

Figure 13 : Mode 2 Bidirectional Data Transfer

Registers Address

Control Register C6

Port – A C0

Port – B C2

Port – C C4

Example 1: Display the Given number

MVI A, 80H : Initialize Port – A as I / P ,Port – B as O/P

in Mode 1 OUT C6 : Store content of Acc into control
register
MVI A,32H :Store data into Accumulator
OUT C2 ; Write content of Acc into Port – B
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HLT : Stop

Example 2 : Read Switches of Port – A ,Display in Port – B

MVI A,90 H ; Initialize Port – A as I / P Port – B as O/P

in Mode 0 OUT C6 : Store content of Acc into
control register
IN C0 : Read Port – A store into
Acc. OUT C2 ; Write content of
Acc into Port – B HLT : Stop

3.3 SERIAL COMMUNICATION INTERFACE

A serial communications interface (SCI) is a device that enables the serial

(one bit at a time) exchange of data between a microprocessor and
peripherals such as printers, external drives, scanners, or mice.
In this respect, it is similar to a serial peripheral interface ( SPI ). But in
addition, the SCI enables serial communications with another
microprocessor or with an external network.

3.3.1 8251A- Universal Synchronous Asynchronous Receiver Transmitter

(USART)

8251Ais a USART (Universal Synchronous Asynchronous Receiver

Transmitter)for serial data communication.

As a peripheral device of a microcomputer system, the 8251Areceives
parallel data from the CPU and transmits serial data after conversion.
This device also receives serial data from the outside and transmits
parallel data to the CPU after conversion.
The 8251A configures a fully static circuit using silicon gate CMOS
technology. Therefore, it operates on extremely low power at 100 mA
(max) of standby current by suspending all operations.

3.3.2 Features
Wide power supply voltage range from 3 V to
6 V Wide temperature range from –40°C to
85°C Synchronous communication up to 64
Kbaud Asynchronous communication up to
38.4 Kbaud
Transmitting/receiving operations under double buffered
configuration. Error detection (parity, overrun and framing)

3.3.3 Block diagram of 8251A

8251A Block diagram is shown in figure 3.11

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 Fig 3.11: Block diagram of 8251A
Data buffer
Interface the internal bus of 8251 with the system bus
Control word and status information are also transferred through this unit.

Read/write control logic

To control the operations of the peripherals operations initiated by CPU.

This unit select one of the internal address either control address and data
address using C/D signal

The CPU interface shares common interface signals with the CPU: Data
Bus, Read, Write, Chip selects, Reset and Master CLK.

Transmit control

To transmit the data bytes received by data buffer from the CPU
It decides transmission rate which is controlled by TXC input frequency
It drive the two transmitter status signals TXRDY,TXEMPTY for CPU
handshaking

Transmitter Buffer
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The Transmitter Buffer and Control logic accept parallel data from the
Data Bus Buffer, convert it to serial, inserting required characters or
bits depending on

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 communication protocol, and output the formatted serial stream to the
TxD output pin.

Modem Control Logic

The Modem Control Logic consists of a set of inputs and outputs that can be
used to interface to almost any modem.

It handles the modem handshake signals to coordinate the communication

between modem and 8251

Receiver control
To Receive the data bytes from the Serial device
It decides Receiver rate which is controlled by RXC input frequency
It also drive the two Receiver status signals RXRDY for CPU
handshaking It also detect the a break in data string in
Asynchronous mode
In synchronous mode it detect SYNC characters using SYNDET/BD

Receiver Buffer
The Receiver Buffer and Control accept serial data, convert it to parallel
format, check for parity, framing, overrun, and break.

3.3.4 Pin diagram of 8251A

8251A pin diagram is shown in below fig 3.12

Fig 3.12: Pin

Configuration of
8251A
D0 to D7 (l/O terminal)
This is bidirectional data bus which receives control words and transmits
data from the CPU and sends status words and received data to CPU.

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RESET (Input terminal)

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 A ―High‖ on this input forces the 8251Ainto ―reset status.‖ The device
waits for the writing of ―mode instruction.‖ The min. reset width is six
clock inputs during the operating status of CLK.

CLK (Input terminal)

CLK signal is used to generate internal device timing. CLK signal is

independent of RXC or TXC.
However, the frequency of CLK must be greater than 30 times the RXC and
TXC at Synchronous mode and Asynchronous ―x1‖ mode, and must be
greater than 5 times at Asynchronous ―x16‖and ―x64‖ mode.

WR (Input terminal)

This is the ―active low‖ input terminal which receives a signal for writing
transmit data and control words from the CPU into the 8251A.

RD (Input terminal)

This is the ―active low‖ input terminal which receives a signal for reading
receive data and status words from the 8251A.

C/D(Input terminal)

This is an input terminal which receives a signal for selecting data or

command words and status words when the 8251Ais accessed by the
CPU .If C/D = low, data will be accessed. If C/D = high, command word or
status word will be accessed.

CS (Input terminal)
This is the ―active low‖ input terminal which selects the 8251Aat low
level when the CPU accesses.

TXD (output terminal)

This is an output terminal for transmitting data from which serial-
converted data is sent out. The device is in ―mark status‖ (high level)
after resetting or during a status when transmit is disabled.
It is also possible to set the device in ―break status‖ (low level) by a
command.

TXRDY (output terminal)

This is an output terminal which indicates that the 8251Ais ready to
accept a transmitted data character.
But the terminal is always at low level if CTS = high or the device was
set in ―TX disable status‖ by a command.

TXEMPTY (Output terminal)

This is an output terminal which indicates that the 8251Ahas transmitted
all the characters and had no data character.
In ―synchronous mode,‖ the terminal is at high level, if transmit data
characters are no longer remaining and sync characters are

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automatically transmitted.
If the CPU writes a data character, TXEMPTY will be reset by the leading
edge of WR signal.

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TXC (Input terminal)
This is a clock input signal which determines the transfer speed of
transmitted data. In ―synchronous mode,‖ the baud rate will be the same
as the frequency of TxC.
In ―asynchronous mode‖, it is possible to select the baud rate factor
by mode instruction.
It can be 1, 1/16 or 1/64 the TxC. The falling edge of TXC sifts the serial
data out of the 8251A.

RXD (input terminal)

This is a terminal which receives serial data. RXRDY (Output terminal) this
is a terminal which indicates that the 8251Acontains a character that is
ready to READ.
If the CPU reads a data character, RXRDY will be reset by the leading edge
of RD signal. Unless the CPU reads a data character before the next one is
received completely.
The preceding data will be lost. In such a case, an overrun error flag status
word will be set.

RXC (Input terminal)

This is a clock input signal which determines the transfer speed of

received data. In
―synchronous mode,‖ the baud rate is the same as the frequency of RxC.
In ―asynchronous mode,‖ it is possible to select the baud rate factor
by mode instruction. It can be 1, 1/16, 1/64 the RXC.

SYNDET/BD (Input or output terminal)

This is a terminal whose function changes according to mode. In ―internal

synchronous mode.‖ this terminal is at high level, if sync characters are
received and synchronized.
If a status word is read, the terminal will be reset. In ―external
synchronous mode,
―this is an input terminal.

DSR (Input terminal)

This is an input port for MODEM interface.
The input status of the terminal can be recognized by the CPU reading
status words.

DTR (Output terminal)

This is an output port for MODEM interface. It is possible to set the status
of DTR by a command.

CTS (Input terminal)

This is an input terminal for MODEM interface which is used for controlling
a transmit circuit. The terminal controls data transmission if the device is
set in ―TX Enable‖ status by a command. Data is transmittable if the
terminal is at low level.

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RTS (Output terminal)

This is an output port for MODEM interface. It is possible to set the status
RTS by a command.

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 3.4 Keyboard / Display Controller

8279 – Keyboard / Display Controller

While studying 8255, we have explained the use of 8255 in interfacing

keyboards and displays with 8086. The disadvantages of this method of
interfacing keyboard and display with 8086 is that the processor has to refresh
the display and check the status of the keyboard periodically using polling
technique. Thus a considerable amount of CPU time is wasted, reducing the
system operating speed. Intel‘s 8279 is a general purpose keyboard display
controller that simultaneously drives the display of a system and interfaces a
keyboard with the CPU, leaving it free for its routine task.

Architecture of 8279

The keyboard display controller chip 8279 provides:

a) a set of four scan lines and eight return lines for interfacing keyboards
b) A set of eight output lines for interfacing display.
I/O Control and Data Buffers : The I/O control section controls the flow of data
to/from the 8279. The data buffers interface the external bus of the system with
internal bus of 8279. The I/O section is enabled only if CS is low. The pins A0, RD
and WR select the command, status or data read/write operations carried out by
the CPU with 8279.

Control and Timing Register and Timing Control : These registers store the
keyboard and display modes and other operating conditions programmed by
CPU. The registers are written with A0=1 and WR=0. The Timing and control unit
controls the basic timings for the operation of the circuit. Scan counter divide
down the operating frequency of 8279 to derive scan keyboard and scan display
frequencies.

Scan Counter : The scan counter has two modes to scan the key matrix and
refresh the display. In the encoded mode, the counter provides binary count that
is to be externally decoded to provide the scan lines for keyboard and display
(Four externally decoded scan lines may drive up to 16 displays). In the decode
scan mode, the counter internally decodes the least significant 2 bits and

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provides a decoded 1 out of 4 scan on SL0-SL3( Four internally decoded scan
lines may drive up to 4 displays). The keyboard and display both are in the same
mode at a time.

172
Return Buffers and Keyboard Debounce and Control: This section for a key closure
row wise. If a key closer is detected, the keyboard debounce unit debounces the
key entry (i.e. wait for 10 ms). After the debounce period, if the key continues to
be detected. The code of key is directly transferred to the sensor RAM along with
SHIFT and CONTROL key status.

FIFO/Sensor RAM and Status Logic: In keyboard or strobed input mode, this block
acts as 8-byte first-in-first-out (FIFO) RAM. Each key code of the pressed key is
entered in the order of the entry and in the mean time read by the CPU, till the
RAM become empty. • The status logic generates an interrupt after each FIFO
read operation till the

FIFO is empty. In scanned sensor matrix mode, this unit acts as sensor RAM.
Each row of the sensor RAM is loaded with the status of the corresponding row of
sensors in the matrix. If a sensor changes its state, the IRQ line goes high to
interrupt the CPU.

Display Address Registers and Display RAM : The display address register holds
the address of the word currently being written or read by the CPU to or from the
display RAM. The contents of the registers are automatically updated by 8279 to
accept the next data entry by CPU.

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 Figure 1: 8279 Internal Architecture

Signal description of of 8279

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DB0-DB7 : These are bidirectional data bus lines. The data and command words
to and from the CPU are transferred on these lines.

CLK : This is a clock input used to generate internal timing required by 8279.

RESET : This pin is used to reset 8279. A high on this line reset 8279. After
resetting 8279, its in sixteen 8-bit display, left entry encoded scan, 2-key lock
out mode. The clock prescaler is set to 31.

CS : Chip Select – A low on this line enables 8279 for normal read or write
operations. Other wise, this pin should remain high.

A0 : A high on this line indicates the transfer of a command or status

information. A low on this line indicates the transfer of data. This is used to
select one of the internal registers of 8279.

RD, WR ( Input/Output ) READ/WRITE – These input pins enable the data

buffers to receive or send data over the data bus.

IRQ : This interrupt output lines goes high when there is a data in the FIFO sensor
RAM. The interrupt lines goes low with each FIFO RAM read operation but if the
FIFO RAM further contains any key-code entry to be read by the CPU, this pin
again goes high to generate an interrupt to the CPU.

Vss, Vcc : These are the ground and power supply lines for the circuit.

SL0-SL3-Scan Lines : These lines are used to scan the key board matrix and
display digits. These lines can be programmed as encoded or decoded, using the
mode control register.

RL0 - RL7 - Return Lines : These are the input lines which are connected to one
terminal of keys, while the other terminal of the keys are connected to the
decoded scan lines. These are normally high, but pulled low when a key is
pressed.

SHIFT : The status of the shift input lines is stored along with each key code in
FIFO, in scanned keyboard mode. It is pulled up internally to keep it high, till it is
pulled low with a key closure.

BD – Blank Display : This output pin is used to blank the display during digit
switching or by a blanking closure.

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OUT A0 – OUT A3 and OUT B0 – OUT B3 – These are the output ports for two 16*4
or 16*8 internal display refresh registers. The data from these lines is
synchronized with the scan lines to scan the display and keyboard. The two 4-bit
ports may also as one 8-bit port.

CNTL/STB- CONTROL/STROBED I/P Mode : In keyboard mode, this lines is used as

a control input and stored in FIFO on a key closure. The line is a strobed lines
that enters the data into FIFO RAM, in strobed input mode. It has an interrupt pull
up. The lines is pulled down with a key closer.

Figure 3 : 8279 Signal

Figure 2 : 8279 Pin Configuration
group

Modes of Operation of 8279

The modes of operation of 8279 are as follows :

1. Input (Keyboard) modes.

2. Output (Display) modes.

Input ( Keyboard ) Modes :

8279 provides three input modes. These modes are as follows:

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1. Scanned Keyboard Mode : This mode allows a key matrix to be interfaced
using either encoded or decoded scans. In encoded scan, an 8*8 keyboard or
in decoded scan, a 4*8 keyboard can be interfaced. The code of key pressed
with SHIFT and CONTROL status is stored into the FIFO RAM.
2. Scanned Sensor Matrix : In this mode, a sensor array can be interfaced with
8279 using either encoded or decoded scans. With encoded scan 8*8 sensor
matrix or with decoded scan 4*8 sensor matrix can be interfaced. The sensor
codes are stored in the CPU addressable sensor RAM.
3. Strobed input: In this mode, if the control lines goes low, the data on return
lines, is stored in the FIFO byte by byte.
3.3.4.2 Output (Display) Modes : 8279 provides two output modes for selecting the
display options. These are discussed briefly.

1. Display Scan : In this mode 8279 provides 8 or 16 character multiplexed

displays those can be organized as dual 4- bit or single 8-bit display units.
2. Display Entry : ( right entry or left entry mode ) 8279 allows options for data
entry on the displays. The display data is entered for display either from the
right side or from the left side.
Keyboard Modes

i. Scanned Keyboard mode with 2 Key Lockout : In this mode of operation, when a
key is pressed, a debounce logic comes into operation. During the next two
scans, other keys are checked for closure and if no other key is pressed the first
pressed key is identified. The key code of the identified key is entered into the
FIFO with SHIFT and CNTL status, provided the FIFO is not full, i.e. it has at least
one byte free. If the FIFO does not have any free byte, naturally the key data will
not be entered and the error flag is set. If FIFO has at least one byte free, the
above code is entered into it and the 8279 generates an interrupt on IRQ line to
the CPU to inform about the previous key closures. If another key is found closed
during the first key, the key code is entered in FIFO. If the first pressed key is
released before the others, the first will be ignored. A key code is entered to FIFO
only once for each valid depression, independent of other keys pressed along
with it, or released before it. If two keys are pressed within a debounce cycle
(simultaneously ), no key is recognized till one of them remains closed and the
other is released. The last key, that remains depressed is considered as single
valid key depression.

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ii. Scanned Keyboard with N-Key Rollover : In this mode, each key depression is
treated independently. When a key is pressed, the debounce circuit waits for 2
keyboards scans and then checks whether the key is still depressed. If it is still
depressed, the code is entered in

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FIFO RAM. Any number of keys can be pressed simultaneously and recognized in the
order, the keyboard scan recorded them. All the codes of such keys are entered
into FIFO. In this mode, the first pressed key need not be released before the
second is pressed. All the keys are sensed in the order of their depression, rather
in the order the keyboard scan senses them, and independent of the order of
their release.

iii. Scanned Keyboard Special Error Mode : This mode is valid only under the NKey
rollover mode. This mode is programmed using end interrupt / error mode set
command. If during a single debounce period ( two keyboard scans ) two keys
are found pressed , this is considered a simultaneous depression and an error
flag is set. This flag, if set, prevents further writing in FIFO but allows the
generation of further interrupts to the CPU for FIFO read. The error flag can be
read by reading the FIFO status word. The error Flag is set by sending normal
clear command with CF = 1.

iv. Sensor Matrix Mode : In the sensor matrix mode, the debounce logic is
inhibited. The 8- byte FIFO RAM now acts as 8 * 8 bit memory matrix. The status
of the sensor switch matrix is fed directly to sensor RAM matrix. Thus the sensor
RAM bits contains the row-wise and column wise status of the sensors in the
sensor matrix. The IRQ line goes high, if any change in sensor value is detected
at the end of a sensor matrix scan or the sensor RAM has a previous entry to be
read by the CPU. The IRQ line is reset by the first data read operation, if AI = 0,
otherwise, by issuing the end interrupt command. AI is a bit in read sensor RAM
word.

Display Modes

There are various options of data display. For example, the command
number of characters can be 8 or 16, with each character organized as single 8-
bit or dual 4- bit codes. Similarly there are two display formats. The first one is
known as left entry mode or type writer mode, since in a type writer the first
character typed appears at the left-most position, while the subsequent
characters appear successively to the right of the first one. The other display
format is known as right entry mode, or calculator mode, since in a calculator the
first character entered appears at the rightmost position and this character is
shifted one position left when the next characters is entered. Thus all the
previously entered characters are shifted left by one position when a new
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characters is entered.

i. Left Entry Mode : In the left entry mode, the data is entered from left side of the
display unit. Address 0 of the display RAM contains the leftmost display
characters and address 15 of the RAM contains the right most display characters.
It is just like writing in our address is automatically updated with successive
reads or writes. The first entry is displayed on the

172
leftmost display and the sixteenth entry on the rightmost display. The seventeenth
entry is again displayed at the leftmost display position.

ii. Right Entry Mode : In this right entry mode, the first entry to be displayed is
entered on the rightmost display. The next entry is also placed in the right most
display but after the previous display is shifted left by one display position. The
leftmost characters is shifted out of that display at the seventeenth entry and is
lost, i.e. it is pushed out of the display RAM.

Command Words of 8279

All the command words or status words are written or read with A0 = 1 and
CS = 0 to or from 8279. This section describes the various command available in
8279.

a) Keyboard Display Mode Set – The format of the command word to select
different modes of operation of 8279 is given below with its bit definitions.

Figure 4 : Command word

D D Display mode

0 Eight 8-bit character Left entry

1 Sixteen 8-bit character left entry

0 Eight 8-bit character Right entry

1 Sixteen 8-bit character Right entry

K K Keyboard mode

0 0 Encoded Scan , 2 key lockout ( Default after reset )

0 1 Decoded Scan, 2 key lockout

1 0 Encoded Scan, N-key Roll over

1 1 Decoded Scan, N-key Roll over

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 0 0 Encode Scan, N-key Roll over

0 1 Decoded Scan, N-key Roll over

1 0 Strobed Input Encoded Scan

1 1 Strobed Input Decoded Scan

b) Programmable clock : The clock for operation of 8279 is obtained by dividing

the external clock input signal by a programmable constant called prescaler.
PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal
constant ranging from 2 to 31, decided by the bits of an internal prescaler,
PPPPP.

Figure 5 : Programmable clock :

c) Read FIFO / Sensor RAM : The format of this command is given below. This
word is written to set up 8279 for reading FIFO/ sensor RAM. In scanned
keyboard mode, AI and AAA bits are of no use. The 8279 will automatically drive
data bus for each subsequent read, in the same sequence, in which the data was
entered. In sensor matrix mode, the bits AAA select one of the 8 rows of RAM. If
AI flag is set, each successive read will be from the subsequent RAM location.

Figure 6 : Read FIFO / Sensor RAM

X – don‘t care

AI – Auto Increment Flag

AAA – Address pointer to 8 bit FIFO RAM

d) Read Display RAM : This command enables a programmer to read the display RAM
data. The CPU writes this command word to 8279 to prepare it for display RAM
read operation. AI is auto increment flag and AAAA, the 4-bit address points
to the 16-byte

172
display RAM that is to be read. If AI=1, the address will be automatically,
incremented after each read or write to the Display RAM. The same address
counter is used for reading and writing.

Figure 7 :Read Display RAM :

e) Write Display RAM :

AI – Auto increment Flag.

AAAA – 4 bit address for 16-bit display RAM to be written.

Figure 8 : Write Display RAM :

f) Display Write Inhibit/Blanking : The IW ( inhibit write flag ) bits are used to mask
the individual nibble as shown in the below command word. The output lines are
divided into two nibbles ( OUTA0 – OUTA3 ) and ( OUTB0 – OUTB3 ), those can
be masked by setting the corresponding IW bit to 1.Once a nibble is masked by
setting the corresponding IW bit to 1, the entry to display RAM does not affect
the nibble even though it may change the unmasked nibble. The blank display
bit flags (BL) are used for blanking A and B nibbles. Here D0, D2 corresponds to
OUTB0 – OUTB3 while D1 and D3 corresponds to OUTA0- OUTA3 for blanking
and masking.

If the user wants to clear the display, blank (BL) bits are available for each
nibble as shown in format. Both BL bits will have to be cleared for blanking both
the nibbles

Figure 9 : Display Write Inhibit/Blanking

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g) Clear Display RAM : The CD2, CD1, CD0 is a selectable blanking code to clear
all the rows of the display RAM as given below. The characters A and B
represents the output

174
nibbles. CD2 must be 1 for enabling the clear display command. If CD2 = 0, the
clear display command is invoked by setting CA=1 and maintaining CD1, CD0
bits exactly same as above. If CF=1, FIFO status is cleared and IRQ line is pulled
down. Also the sensor RAM pointer is set to row 0. if CA=1, this combines the
effect of CD and CF bits. Here, CA represents Clear All and CF as Clear FIFO RAM.

Figure 10: Clear Display RAM :

CD2 1 CD1 0 CD0

1 0 X
1 1 0
1 1 1

All zeros ( x don‘t care ) AB=00

A3-A0 =2 (0010) and B3-B0=00 (0000)

All ones (AB =FF), i.e. clear RAM

h) End Interrupt / Error mode Set : For the sensor matrix mode, this command
lowers the IRQ line and enables further writing into the RAM. Otherwise, if a
change in sensor value is detected, IRQ goes high that inhibits writing in the
sensor RAM. For N-Key roll over mode, if the E bit is programmed to be ‗1‘, the
8279 operates in special Error mode. Details of this mode are described in
scanned keyboard special error mode. X- don‘t care.

Figure 11 : End Interrupt / Error mode Set

175
 Figure 12 : Interfacing 8086 with 8279

3.5 PROGRAMMABLE INTERVAL TIMER

Intel 8253

The Intel 8253 is a programmable counter / timer chip designed for use as
an Intel microcomputer peripheral. It uses nMOS technology with a single +5V
supply and is packaged in a 24-pin plastic DIP. It is organized as 3 independent
16-bit counters, each with a counter rate up to 2 MHz. All modes of operation are
software programmable. The 82C54 is pin compatible with the HMOS
8254, and is a superset of the 8253. Six programmable timer modes
allow the 82C54 / 8253 to be used as an event counter, elapsed time indicator,
programmable one-shot, and in many other applications.

3.6. Features

The timer has three counters, called channels. Each channel can be programmed
to operate in one of six modes. Once programmed, the channels can perform
their tasks independently. The timer is usually assigned to IRQ-0 (highest priority
hardware interrupt) because of the critical function it performs and because so
176
many devices depend on it.

177
Block diagram 3.6.1.3.1
Counter
There are 3 Counters (or timers), which are labelled as Counter 0, Counter
1 and Counter 2. Each counter has 2 input pins - CLK (clock input) and GATE -
and 1 pin, OUT, for data output. The 3 counters are 16-bit down counters
independent of each other, and can be easily read by the CPU. The timer has
three independent, programmable counters and they are all identical. The first
counter (selected by setting A1=A0=0, see Control Word Register below) helps
generate an 18.2 Hz clock signal. The second counter (A1=0, A0=1) assists in
generating timing, which will be used to refresh the DRAM memory. The last
counter 4.9.1.3.2 Data Bus Buffer contains the logic to buffer the data bus to /
from the microprocessor, and to the internal registers.

Read / write logic controls the reading and the writing of the counter registers.

/RD: read signal

/WR: write signal
/CS: chip select signal A0,
A1: address lines

Control Word Register, This register contains the programmed information which
will be sent to the device from the microprocessorTo initialise the counters, the
microprocessor must write a control word (CW) in this register. This can be done
by setting proper values for the pins of the Read/Write Logic block and then by
sending the control word to the Data/Bus Buffer block.Each counter in the block
diagram has 3 logical lines connected to it. Two of these lines, clock and gate,
are inputs. The third, labeled OUT is an output. The function of these lines
changes and depends on how the device is initialized or programmed.
The control
word
contains 8 bits, labeled D7..D0 (D7 is the MSB).

Bit# D7 D6 D5 D4 D3 D2 D1 D0
Name SC1 SC0 RW1 RW0 M2 M1 M0
BCD

Func. Select Read/Write Select =0, 16-b binary

counter Counter Mode =1, 4-
178
 decade BCD counter

The following table describes how to use the Read/Write bits (RW1, RW0).

RW1 RW0 Description

179
0 0 Counter Latch Command
0 1 Read/Write the least significant byte (LSB) only
1 0 Read/Write the most significant byte (MSB) only
1 1 Read/Write LSB first, followed by MSB

Block diagram of an 8253 programmable interval timer and pin description

Figure : Block diagram of an 8253 programmable interval timer and pin description

PIN configuration The

following picture shows the pin configuration of the 8253 and a general definition
of the lines follows:

Clock : This is the clock input for the counter. The counter is 16 bits. The
maximum clock frequency is 1 / 380 nanoseconds or 2.6 megahertz. The
minimum clock frequency is DC or static operation.

177
 Out : This single output line is the signal that is the final programmed output of
the device. Actual operation of the out line depends on how the device has been
programmed

Gate : This input can act as a gate for the clock input line, or it can act as a
start pulse, depending on the programmed mode of the counter.

Internal 8253 registers

Here is a list of the internal 8253 registers that will program the internal
counters of the 8253:

RD WR A0 A1 function

1 0 0 0 Load counter 0
COUNTER 0
0 1 0 0 Read counter 0

1 0 0 1 Load counter 1
COUNTER 1
0 1 0 1 Read counter 1

1 0 1 0 Load counter 2
COUNTER 2
0 1 1 0 Read counter 2

MODE WORD 1 0 1 1 Write mode word

or
CONTROL WORD

-- 0 1 1 1 No-operation

Counter #0, #1, #2 Each counter is identical, and each consists of a 16-bit, pre-
settable,
down counter. Each is fully independent and can be easily read by the CPU.
When the
counter is read, the data within the counter will not be disturbed. This allows the
system or your own program to monitor the counter's value at any time, without
disrupting the overall function of the 8253.

Control Word Register This internal register is used to write information to, prior
to using the device. This register is addressed when A0 and A1 inputs are logical
1's. The data in the register controls the operation mode and the selection of
either binary or BCD ( binary coded decimal ) counting format. The register can
only be written to. You can't read information from the register.

Control Word Register

CONTROL BYTE D7 - D0

D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC0 RL1 RL0 M2 M1 M0 BCP

All of the operating modes for the counters are selected by writing bytes to
the control register. This is the control word format.

D7 D6
Counter Select
SC1 SC0

0 0 counter 0

0 1 counter 1

1 0 counter 2

1 1 illegal value

Bits D7 and D6 are labeled SC1 and SC0. These bits select the counter to be
programmed,
it is necessary to define, using the control bits D7 and D6, which counter is
being set
up.Once a counter is set up, it will remain that way until it is changed by
another control word.

D5 D4
R / L Definition
RL1 RL0

0 0 Counter value is latched. This means that the selected counter has
its contents transferred into a temporary latch, which can then be
read by the CPU.

0 1 Read / load least-significant byte only.

1 0 Read / load most-significant byte only.

1 1 Read / load least-significant byte first, then most-significant byte.

Bits D5 and D4 ( RL1 / RL0 ) of the control word shown above are defined as the
read / load mode for the register that is selected by bits D7 and D6. Bits D5 and
D4 define how the particular counter is to have data read from or written to it by
the CPU. The next 3 bits of the control word are D3, D2, and D1. These bits
determine the basic mode of operation for the selected counter. The mode
descriptions follows:

Operation Modes The D3,

D2, and D1 bits of the Control Word set the operating mode of the timer. There are 6 modes
in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases
for modes 2 and 3. Notice that, for modes 0, 2, 3 and 4, GATE must be set to HIGH to
enable counting. For modes 1 and 5, the rising edge of GATE starts the count. For details on
each mode, see the reference links.

D3 D2 D1
Mode value
M2 M1 M0

0 0 0 mode 0: interrupt on terminal count

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0 0 1 mode 1: programmable one-shot

x 1 0 mode 2: rate generator

x 1 1 mode 3: square wave generator

1 0 0 mode 4: software triggered strobe

1 0 1 mode 5: hardware triggered strobe

The final bit D0 of the control register determines how the register will count:

The maximum values for the count in each count mode are 10 4 ( 10,000 decimal )
in BCD, and 216 ( 65,536 decimal ) in binary.

D0 counts down in

0 binary

1 BCD

Modes The
following text describes all possible modes. The modes used in the MZ-700 and
set by the monitor's startup are mode 0, mode 2, and mode 3.

3.6..6.1 Mode 0 : Interrupt on Terminal Count

In this mode, the counter will start counting from the initial COUNT value
loaded into it, down to 0. Counting rate is equal to the input clock frequency.The
OUT pin is set low after the Control Word is written, and counting starts one clock
cycle after the COUNT programmed. OUT remains low until the counter reaches
0, at which point OUT will be set high until the counter is reloaded or the Control
Word is written.Once the counter starts counting down, the GATE input can
disable the internal counting by setting the GATE to a logical 0.

181
Mode 1 : Programmable One-Shot
This is similar to mode 0, but counting is started by a rising edge on the
GATE input instead of immediately after programming. The GATE input is ignored
while counting.The output is set high as soon as the Control Word is written. After
COUNT is written, the device will wait until the rising edge of the GATE input.
One clock cycle after this rising edge is detected, OUT will become and remain
low until the counter reaches 0. OUT will then go high, waiting for the next
trigger. The one-shot is triggered on the rising edge of the GATE input. If the
trigger occurs during the pulse output, the 8253 will be retriggered again.

Mode 2 : Rate Generator In

this mode, the device acts as a divide-by-n counter, which is commonly used to
generate a real-time clock interrupt.Like other modes, counting process will start
the next clock cycle after COUNT is sent. OUT will then remain high until the
counter reaches 1, and will go low for one clock pulse. OUT will then go high
again, and the whole process repeats itself.

182
The time between the high pulses depends on the preset count in the counter's
register, and is calculated using the following formula:

183
Value to be loaded into counter =

Note that the values in the COUNT register range from n to 1; the register
never reaches

zero.

Mode 3 : Square Wave Generator

This mode is similar to mode 2. However, the duration of the high and low
clock pulses of the output will be different. Suppose n is the number loaded into
the counter (the COUNT message), a square wave is generated

high for counts, and low for counts, if n is even.

high for counts, and low for counts, if n is odd.

Mode 4 : Software Triggered Strobe

After Control Word and COUNT is loaded, the output will remain high until
the counter reaches zero. The counter will then generate a low pulse for 1 clock
cyle (a strobe) - after that the output will become high again. . A low in the gate
disables count and a high enables it .In this mode the programmer can set up the
counter to give an output timeout starting when the register is loaded. On the
terminal count, when the counter equals to 0, the output will go to a logical 0 for
one clock period and then returns to a logical 1. First the mode is set, the output
will be a logical 1.

184
Mode 5 : Hardware Triggered Strobe
This mode is similar to mode 4. Count is enabled with rising edge of gate
However, the counting process is triggered by the GATE input.After receiving the
Control Word and COUNT, the output will be set high. Once the device detects a
rising edge on the GATE input, it will start counting. When the counter reaches 0,
the output will go low for one clock cycle - after that it will become high again, to
repeat the cycle on the next rising edge of GATE.

3.6 A/D AND D/A INTERFACE

3.6.1 Interfacing Analog to Digital Data Converters

In most of the cases, the PIO 8255 is used for interfacing the analog to
digital converters with microprocessor. We have already studied 8255
interfacing with 8086 as an I/O port, in previous section. This section we
will only emphasize the interfacing techniques of analog to digital
converters with 8255.
The analog to digital converters is treaded as an input device by the
microprocessor that sends an initializing signal to the ADC to start the
analogy to digital data conversation process.
The start of conversation signal is a pulse of a specific duration. The
process of analog to digital conversion is a slow process, and the
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microprocessor has to wait for the digital data till the conversion is over.

186
 After the conversion is over, the ADC sends end of conversion EOC signal
to inform the microprocessor that the conversion is over and the result is
ready at the output buffer of the ADC. These tasks of issuing an SOC pulse
to ADC, reading EOC signal from the ADC and reading the digital output of
the ADC are carried out by the CPU using 8255 I/O ports.
The time taken by the ADC from the active edge of SOC pulse till the
active edge of EOC signal is called as the conversion delay of the ADC. It
may range any where from a few microseconds in case of fast ADC to
even a few hundred milliseconds in case of slow ADCs.
The available ADC in the market use different conversion techniques for
conversion of analog signal to digitals. Successive approximation
techniques and dual slope integration techniques are the most popular
techniques used in the integrated ADC chip.

General algorithm for ADC interfacing contains the following steps:

Ensure the stability of analog input, applied to

the ADC. Issue start of conversion pulse to ADC
Read end of conversion signal to mark the end of conversion
processes. Read digital data output of the ADC as equivalent
digital output.
Analog input voltage must be constant at the input of the ADC right from
the start of conversion till the end of the conversion to get correct results.
This may be ensured by a sample and hold circuit which samples the
analog signal and holds it constant for specific time duration. The
microprocessor may issue a hold signal to the sample and hold circuit.
If the applied input changes before the complete conversion process is
over, the digital equivalent of the analog input calculated by the ADC may
not be correct.

ADC 0808/0809
The analog to digital converter chips 0808 and 0809 are 8-bit CMOS,
successive approximation converters.
This technique is one of the fast techniques for analog to digital conversion.
The conversion delay is 100μs at a clock frequency of 640 KHz, which is
quite low as compared to other converters. These converters do not need
any external zero or full scale adjustments as they are already taken care
of by internal circuits.
These converters internally have a 3:8 analog multiplexer so that at a time
eight different analog conversion by using address lines - ADD A, ADD B,
ADD C.
Using these address inputs, multi channel data acquisition system can be
designed using a single ADC.
The CPU may drive these lines using output port lines in case of multi
channel applications.
In case of single input applications, these may be hardwired to select
the proper input.
There are unipolar analog to digital converters, i.e. they are able to convert
only positive analog input voltage to their digital equivalent. These chips
do no contain any internal sample and hold circuit.

187
Analog / Address lines
select
C B A
I/P0 0 0 0
I/P1 0 0 1

188
 I/P2 0 1 0
I/P3 0 1 1

I/P4 1 0 0
I/P5 1 0 1
I/P6 1 1 0

I/P7 1 1 1
Table 3.5

Block Diagram of ADC 0808/0809

Fig 3.13: Block Diagram of ADC 0808/0809

186
Timing Diagram of ADC 0808

Fig 3.14: Timing Diagram of ADC 0808

Pin Diagram of ADC 0808/0809

Fig 3.15: Pin diagram of ADC 0808/0809

187
Vcc : Supply pins +5V
GND : GND
Vref+ : Reference voltage positive +5 Volts
maximum. Vref_ : Reference voltage negative
0Volts minimum. I/P0 –I/P7 : Analog inputs
ADD A,B,C : Address lines for selecting analog inputs.
O7-00 : Digital 8-bit output with O7 MSB and O0 LSB
SOC : Start of conversion signal pin
EOC : End of conversion signal pin
OE : Output latch enable pin, if high enables output
CLK : Clock input for ADC

3.6.2 Interfacing Digital to Analog Converters

The digital to analog converters convert binary number into their equivalent
voltages. The DAC find applications in areas like digitally controlled
gains, motors speed controls, programmable gain amplifiers etc.AD 7523 8-
bit Multiplying DAC:
This is a 16 pin DIP, multiplying digital to analog converter, containing R-
2R ladder for D-A conversion along with single pole double thrown NMOS
switches to connect the digital inputs to the ladder.

Pin Diagram

Fig 3.16: Pin diagram of AD7523

The pin diagram of AD7523 is shown in Fig, the supply range is from +5V
to +15V, while Vref may be any where between -10V to +10V.
The maximum analog output voltage will be any where between -10V to
+10V, when all the digital inputs are at logic high state.
188
Usually a zener is connected between OUT1 and OUT2 to save the DAC
from negative transients.

189
 An operational amplifier is used as a current to voltage converter at the
output of AD to convert the current out put of AD to a proportional output
voltage. It also offers additional drive capability to the DAC output.
An external feedback resistor acts to control the gain. One may not
connect any external feedback resistor, if no gain control is required.

Example:

Interfacing DAC AD7523 with an 8086 CPU running at 8MHZ and write an
assembly language program to generate a saw tooth waveform of period
1ms with Vmax 5V. Solution: Figure 3.17 shows the interfacing circuit of AD
74523 with 8086 using 8255. Program gives an ALP to generate a saw tooth
waveform using circuit.

ASSUME CS:CODE
CODE SEGMENT
START: MOV AL,80h ;make all ports
output OUT CW, AL
AGAIN: MOV AL, 00h ;start voltage for
ramp BACK: OUT PA, AL
INC AL
CMP AL,
0FFh JB
BACK
JMP AGAIN
CODE ENDS
END START

190
Fig 3.17: Interfacing of AD7523

191
 In the above program, port A is initialized as the output port for sending
the digital data as input to DAC. The ramp starts from the 0V (analog),
hence AL starts with 00H.
To increment the ramp, the content of AL is increased during each
execution of loop till it reaches F2H. After that the saw tooth wave again
starts from 00H, i.e. 0V(analog) and the procedure is repeated.
The ramp period given by this program is precisely 1.000625 ms. Here the
count F2H has been calculated by dividing the required delay of 1ms by
the time required for the execution of the loop once.
The ramp slope can be controlled by calling a controllable delay after the
OUT instruction.

3.7 INTERRUPT CONTROLLER

8259 A - Priority Interrupt Controller

The processor 8085 had five hardware interrupt pins. Out of these five interrupt
pins four pins were allotted fixed vector address but the pin INTR was not
allotted any vector address, rather than external device was supposed to
hand over the type of interrupt
i.e (Type 0 Type 7 for RST0 to RST 7) to the CPU.

The processor then gets this type and derives the interrupt vector address
from that. Consider an application, where a number of IO devices are connected
with CPU desire to transfer data using interrupt driven mode.

In these case, more number of interrupt pins are required than available in
a CPU. Moreover, in these multiple interrupt systems, the processor will have to
take care of priorities for the interrupt, simultaneously occurring at the interrupt
request pins. The 8086 has only two interrupt inputs, NMI and INTR.

To overcome all these difficulties, we require a programmable interrupt

controller which is able to handle a number of interrupt at a time. This relieves
the processor from this entire task. The 8259 was designed to operate only with
8 bits microprocessors like 8085.A modified version; 8259A is compatible with 8
bit as well as 16 bits processors

Block diagram of 8259 A

190
 Fig 3.22: Block diagram of 8259 A
Interrupt Request Register (RR)

The interrupts at IRQ input lines are handled by Interrupt Request internally.
IRR stores the entire interrupt request in it in order to serve them one by
one on the priority basis.

In-Service Register (ISR)

This stores all the interrupt requests those are being served, i.e. ISR keeps a
track of the requests being served.
Priority Resolver

This unit determines the priorities of the interrupt requests appearing

simultaneously. The highest priority is selected and stored into the
corresponding bit of ISR during INTA pulse.
The IR0 has the highest priority while the IR7 has the lowest one,
normally in fixed priority mode.
The priorities however may be altered by programming the 8259A in
rotating priority mode.

3.7.1.4 Interrupt Mask Register (IMR)

This register stores the bits required to mask the
interrupt inputs. IMR operates on IRR at the direction of
the Priority Resolver.

3.7.1.5 Interrupt Control Logic

This block manages the interrupt and interrupt acknowledge signals to be
sent to the CPU for serving one of the eight interrupt requests.
This also accepts the interrupt acknowledge (INTA) signal from CPU that
causes the 8259A to release vector address on to the data bus.

Data Bus Buffer

This tristate bidirectional buffer interfaces internal 8259A bus to the
microprocessor system data bus.
Control words, status and vector information pass through data buffer
during read or write operations.

Read/Write Control Logic

This circuit accepts and decodes commands from the CPU.

This block also allows the status of the 8259A to be transferred on to the
data bus.

Cascade Buffer/Comparator

This block stores and compares the ID‘s all the 8259A used in system.
The three I/O pins CASO-2 are outputs when the 8259A is used as a
master. The same pins act as inputs when the 8259A is in slave
mode.

191
 The 8259A in master mode sends the ID of the interrupting slave device
on these lines. The slave thus selected, will send its preprogrammed
vector address on the data bus during the next INTA pulse.

INT:

192
 This pin goes high whenever a valid interrupt request is asserted. This
is used to interrupt the CPU and is connected to the interrupt input of
CPU.

IR0 – IR7 (Interrupt requests):

These pins act as inputs to accept interrupt request to the CPU. In edge
triggered mode.
An interrupt service is requested by raising an IR pin from a low to a high
state and holding it high until it is acknowledged, and just by latching it to
high level, if used in level triggered mode.

INTA (Interrupt acknowledge):

This pin is an input used to strobe-in 8259A interrupt vector data on to the
data bus. In conjunction with CS, WR and RD pins, this selects the
different operations like, writing command words, reading status word,
etc.

Interrupt Sequence in an 8086-8259A system

One or more IR lines are raised high that set corresponding

IRR bits. 8259A resolves priority and sends an INT signal to

CPU.

The CPU acknowledge with INTA pulse.

Upon receiving an INTA signal from the CPU, the highest priority ISR bit is
set and the corresponding IRR bit is reset. The 8259A does not drive data
during this period.

The 8086 will initiate a second INTA pulse. During this period 8259A
releases an 8- bit pointer on to a data bus from where it is read by the
CPU.

This completes the interrupt cycle. The ISR bit is reset at the end of the
second INTA pulse if automatic end of interrupt (AEOI) mode is
programmed. Otherwise ISR bit remains set until an appropriate EOI
command is issued at the end of interrupt subroutine.

Command Words of 8259A

The command words of 8259A are classified in two

groups Initialization command words (ICW) and
Operation command words (OCW).

Initialization Command Words (ICW)

Before it starts functioning, the 8259A must be initialized by writing two to

four command words into the respective command word registers.
193
 These are called as initialized command words. ICW1 and ICW2 are
compulsory command words in initialization sequence of 8259A while
ICW3 and ICW4 are optional.
Operation Command Words:

Once 8259A is initialized it is ready for its normal function, i.e. for
accepting the interrupts but 8259A has its own way of handling the
received interrupts called as

194
 modes of operation. These modes of operations can be selected by
programming,
i.e. writing three internal registers called as operation command
words registers. The data written into them is called as operational
command words.

There are three operation command

words OCW1
OCW2
OCW3

Every bit corresponds to some operational feature of the mode selected,

except for a few bits those are either 1 or 0.

Operating Modes of 8259

The different modes of operation of 8259A can be programmed by setting

or resting the appropriate bits of the ICW or OCW

The different modes of operation of

8259A Fully Nested Mode

End of Interrupt (EOI)
Automatic Rotation
Automatic EOI Mode
Specific Rotation
Specific Mask Mode
Edge and Level Triggered
Mode Reading 8259 Status
Poll Command
Special Fully Nested Mode
Buffered Mode
Cascade Mode
Fully Nested
Mode

3.8 DMA CONTROLLER

It is a device to transfer the data directly between IO device and memory without
through the CPU. So it performs a high-speed data transfer between memory and
I/O device.

Features: -

It is a 4-channel DMA.So 4 I/O devices can be interfaced to

DMAC It is designed by Intel
Each channel have 16-bit address and 14 bit counter
It provides chip priority resolver that resolves priority of channels in
fixed or rotating mode.

195
 It generates a TC signal to indicate the peripheral that the
programmed number of data bytes has been transferred.

It is operate in two modes.

i. Master Mode ii. Slave Mode

196
 Channel Each can be independently programmable to transfer up to
64kbytes of data by DMA.
Each channel can be independently perform read transfer, write transfer
and verify transfer.

Architecture of DMAC: -It contains four main Blocks.

Data bus buffer

Read/Control

logic Control
logic block
Priority resolver & DMA channels.
Data Bus Buffer: - It contain tri-state, 8-bit bi-directional buffer.). It provides the
link between the internal structure of 8257 and the system bus. In Slave mode, it
transfers data between microprocessor and internal data bus.Master mode,
these lines are used to carry address information A8-A15 bits of memory address
(Unidirectional).

Read/Control Logic: - It controls all internal Read/Write operation of DMAC.

InSlave mode, it accepts address bits and control signals from microprocessor.
But in Master mode, it generates address bits and control signals to the Slave
DMACs.

197
Control Logic: - In Master mode, It control the sequence of DMA operation during
all DMA cycles. It generates address and control signals which are necessary for
the operation. It increments 16 bit address and decrement 14 bit counter
registers values. It activates a HRQ signal on DMA channel Request when it
receives any DREQ signal from external devices. But in Slave mode it is disabled.

DMA Channels: - DMAC has four DMA channels (CH3-CH0). Each channel has two
16-bit registers. External devices are connected to this channels the external
devices send their DMA requests to DMAC through DRQ inputs and they get the
acknowledgements through DACK outputs.

Priority Resolver: - This block assign the priorities to the DMA channels of DMAC
based on mode of operation.

First/Last Flip Flop (FF): - 8257 have 8bit data line and 16 bit address line.8086 it
is getting 8-bit data in simultaneously.8086 cannot access 16-bit address in
simultaneously.A0-A3 lines are used to distinguish between registers, but they
are not distinguishing lower and higher address.It is reset by external RESET
signal.It is also reset by whenever mode set register is loaded.So program
initialization with a dummy (00 H).

i. FF=1=Higher byte of address

ii. FF=0=Lower byte of address.
Pin Diagram of 8257 DMAC: -

Description of pin diagram: -

D0-D7 (Data Lines): - These lines carry Command words from the processor and
the Status information from the 8257 in Slave Mode of operation. But in Master
mode of operation these lines carry the higher order byte address to the latch.
198
These lines also used for data transmissions.

199
DRQ0 – DRQ3 (DMA Request) Signals: - These lines are used by peripheral devices
for requesting DMA services. The DRQ0 has the highest priority while DRQ3 has
the lowest priority in Fixed Priority mode.

DACK0 – DACK3 (DMA Acknowledge) Signals: - These four lines are active low
signals. These lines are used to inform the requesting peripheral that the request
has been honored and the bus is relinquished by the CPU.

IOR (IO Read) Signal: -It is an input signal in Slave Mode of operation of 8257 in
that mode this signal is used by CPU to read the information from the internal
registers of 8257. It is acts as an output signal in Master Mode of operation it is
used to read data from a peripheral during a memory write operation. This signal
is an active low signal.

IOW (IO Write) Signal: -It is an input signal in Slave Mode of operation of
8257 .this signal is used by CPU to write the information to the internal registers
of 8257. It acts as an output signal in Master Mode of operation and it is used to
write data to a peripheral during a memory read operation. This signal is an
active low signal.

A0-A3 (Address Lines): - These are the tri-statebidirectional address lines.In slave
mode,these lines are used as address inputs lines and internally decoded to
access the internal registers.In master mode, these lines are used as address
outputs lines,A0-A3 bits of memory address on the lines. The addresses for
internal registers of 8257are assigned by using A0, A1, A2, & A3are as follows.
Register Byte A3 A2 A1 A0 F/L

CH-0 DMA Address Register LSB 0 0 0 0 0

CH-0 DMA Address Register MSB 0 0 0 0 1

CH-0 DMA Terminal Count Register LSB 0 0 0 1 0

CH-0 DMA Terminal Count Register MSB 0 0 0 1 1

CH-1 DMA Address Register LSB 0 0 1 0 0

CH-1 DMA Address Register MSB 0 0 1 0 1

CH-1 DMA Terminal Count Register LSB 0 0 1 1 0

CH-1 DMA Terminal Count Register MSB 0 0 1 1 1

CH-2 DMA Address Register LSB 0 1 0 0 0

CH-2 DMA Address Register MSB 0 1 0 0 1

CH-2 DMA Terminal Count Register LSB 0 1 0 1 0

CH-2 DMA Terminal Count Register MSB 0 1 0 1 1

196
 CH-3 DMA Address Register LSB 0 1 1 0 0

CH-3 DMA Address Register MSB 0 1 1 0 1

CH-3 DMA Terminal Count Register LSB 0 1 1 1 0

CH-3 DMA Terminal Count Register MSB 0 1 1 1 1

Mode Set Register 1 0 0 0 0

Status Register 1 0 0 0 0

**Where F/L indicates First/Last Flip-Flop.

CS (Chip Select) Signal: - It is active low, Chip select input line. In the slave mode,
it is used to select the chip. In the master mode, it is ignored.

A4-A7 (Address Lines):- These are the tri-stateoutput address lines. In slave
mode,these lines are used as address outputs lines.In master mode, these lines
are used as address outputs lines,of memory address on the lines.

READY Signal: - It is anasynchronous input line. In master mode, When ready is

high it is received the signal from the selected peripheral. When ready is low, it
adds wait state to the operation.

HRQ (HOLD Request): - It is used to send a DMA request signal to the processor
from DMA controller8257 to take the control over the system bus. This signal is
directly connected to the HOLD signal of the processor.

HLDA (HOLD Acknowledge) Signal: - It is acknowledgment signal from

microprocessor. If the DMA request is accepted by the processor and it is ready
to release the control over system bus the processor issues this signal. HLDA
signal of the processor is directly connected to HLDA signal of DMAC.

MEMR (Memory Read) Signal:- It is active low output line.This is used to read
data from the peripheral during DMA read cycle.

MEMW (Memory Write) Signal:- It is active low output line.This is used to write on
to the selected memory location in the DMA Write operation.

AEN (Address enable) Signal: - It is a control output line. In master mode, it is

high. In slave mode, it is low. It is used it isolate the system address, data, and
control lines. During DMA mode, the AEN signal is also used to disable the buffers
and latches used for address, data and control signals of the processor.

ADSTB (Address Strobe): - It is a control output line.Used to split data and

address line.It is working in master mode only.In slave mode it is ignore.

TC (Terminal Count) Signal: - It is a status of output line.This output notifies the

currently selected peripheral that the present DMA cycle is the last DMA cycle
for this data block. TC

197
STOP bit in the Mode Set register is set then the selected channel is
automatically disabled at the end of the DMA cycle.

MARK Signal: -It is a Modulo 128 MARK output line. This output notifies the
selected peripheral that the current DMA cycle is 128 th cycle since the previous
MARK. This signal always occurred at 128 cycles from the end of the data block.

CLK (Clock) Signal: - It is the input line; it is connected to the clock generator
8284 in the system.

RESET Signal: -It disables all channels of DMA controller and it isused to clear
mode set register, status register and internal registers of DMAC.

Register Organization of 8257 DMAC: -Each channel of DMA controller has a pair of
16-bit registers. Those are Address Register, and Terminal Count Register.

There are common registers of all channels those are Mode Set Register and
Status Register both are 8-bit registers.

DMA Address Register: - The function of this register in any channel is it can store
the address of starting memory location, which will be accessed by the DMA
channel. It is a 16- bit register.

Terminal Count Register: - This 16-bit register is used for ascertaining that the
data transfer through DMA channel ceases or stops after the required number of
DMA cycles. The lower order 14-bits of terminal count register are initialized
with the binary equivalent of the number of required DMA cycles minus one.
After each DMA cycle, The Terminal Count Register content will be decremented
by one and finally it becomes zero after the required number of DMA cycles are
over.The higher order two bits of this register indicate the type of the DMA
operation.

In read DMA cycle the data is transferred from memory to I/O device. In write DMA
cycle the data is transferred from I/O device to memory.Verification operations
generate the DMA addresses without generating the DMA memory and I/O control
signals.

Mode Set Register: - It is a write only registers.It is used to set the operating
198
modes.This registers is programmed after initialization of DMA channel.

199
Status Register: - It is read only register.It tells about the status of DMA channels.
TC status bits are set when TC signal is activated for that channel.Update flag is
not affected during read operation.The UP bit is set during update cycle. It is
cleared after completion of update cycle.

200
Modes of Operation: -

1. Rotating priority Mode: -The priority of the channels has a circular sequence.
After each DMA cycle the priorities of channels are changed. The channel which
had just been serviced will have the lowest priority.

2. Fixed Priority Rotating Mode: - The priority is fixed. Every time CH-0 has highest
priority and CH-3 has lowest priority.

3. Auto Load Mode Operation: -This mode of operation permits the Channel –
2(CH-2) for repeat block or block chaining operation, without immediate software
intervention between blocks. Channel- 2 registers are initialized as usual for first
data block transfer. The Channel- 3 registers are used to store the block re-
initialization parameters. After the first block of DMA operation is performed by
Channel- 2 the parameters stored in the Channel- 3 registers are transferred to
Channel- 2 registers during Update cycle.

3.9 PROGRAMMING AND APPLICATIONS CASE STUDIES (Traffic Light control, LED
Display, LCD Display, Keyboard Display Interface & Alarm
Controller)
3.9.1 Traffic Light Control
Design a microprocessor system to control traffic lights. The
traffic light arrangement is as shown in Fig. 3.25.
The traffic should be controlled in the following manner.
1) Allow traffic from W to E and E to W transition for 20 seconds.
2) Give transition period of 5 seconds (Yellow bulbs ON)
3) Allow traffic from N to S and S to N for 20 seconds
4) Give transition period of 5 seconds (Yellow bulbs ON)
5) Repeat the process

Fig 3.25. Traffic light control

Hardware:
Fig. 3.26 shows the interfacing diagram to control 12 electric bulbs.
Port A is used to control lights on N-S road and Port B is used to control
lights on W-E road. Actual pin connections are listed in Table 3.9.

201
 Table. 3.9 TLC pin connections
The electric bulbs are controlled by relays.
The 8255 pins are used to control relay on off action with the help of relay
driver circuits.
The driver circuit includes 12 transistors to drive 12
relays. Fig. 3.26 also shows the interfacing of 8255
to the system.

Fig. 3.26 The interfacing diagram for traffic light control system

I/O Map

202
 Fig. 3.10 Ports/Control Register and address lines
Software:

Control word: For initialization of 8255.

Fig. 3.11 (a) Control word

Table 3.11(b) Combinations data bytes

Source program:
MVI A, 80H ; Initialize 8255, port A and
port B OUT 83!! (CR) ; in output mode
START: MVI A, 09H ;
OUT 80H (PA) ; Send data on PA to glow R1
and R3 MVI A. 24H
OUT 81H (PB) ; Send data on PB to glow G3
and G4 MVI C. 28H ; Load multiplier count
(40) for delay CALL DELAY ; Call delay
subroutine
MVI A, 12H
OUT (8 1H) PA ; Send data on Port A to glow Y1
and Y OUT (81H) PB ; Send data on port B to glow
Y3 and Y4 MVI C, OAH ; Load multiplier count (10)
for delay CALL DELAY ; Call delay subroutine
MVI A, 24H
OUT (80H) PA ; Send data on port A to glow G1
and G2 MVI A.09H
OUT (81H) PB ; Send data on port B to glow R3
and R0 MVI C. 28H ; Load multiplier count (40)
for delay CALL DELAY ; Call delay subroutine
MVI A.12H
OUT PA ; send data on port A to glow Y1

203
and Y2 OUT PB ; Send data on port B to glow Y3
and Y4 MVI C.OAH ; Load multiplier count (1O)
for delay

204
 CALL DELAY ; Call delay
subroutine JMP START

3.9.2 LED DISPLAY

LED displays are available in two very common formats.

1. 7 segment displays
2. 5 by 7 dot-matrix displays.

Seven-Segment display
Seven segment displays are generally used as numerical indicators
It consists of a number of LEDs arranged in seven segments shown in
the Fig. 3.27.

Figure 3.27 seven segments Display

Any number between O and 9 can be indicated by lighting the Segments. Fig. 3.27

3.9.2.1 Seven segment display

Figure 3.28 Seven segment display

The seven segments are labeled a biasing different LED
segments. To display O, we need to light up a, segments a,
f, g. c and d.
These 7 Segment displays are of two types:
1. Common Anode Type
2. Common Cathode Type
In common a node, all anodes of LEDs are connected together as in
common cathode Fig. 3.29 (a) Common anode type,
All cathodes are connected together, Fig. 3.29 (b) Common cathode type

205
 Fig. 3.29 (a) Common anode type

Fig. 3.29 (b) Common cathode type

3.9.2.2 5 by 7 DOT matrix LED

Fig. 3.30 (a) and (b) show the 5 by 7 dot matrix LED display and its circuit

connections.
Figure 3.30(a) 5 X 7 dot matrix LED display

Figure 3.30(b) 5 X 7 dot matrix Circuit Connections

This display can be used to display number as well as
alphabets. Keyboard and Display Interfacing 329

Interfacing LED Displays

Static Display Fig. 3.31 shows a circuit to drive a single, seven segment,
common a node LED Display.
206
 For common anode, when anode is connected to positive supply, a low
voltage is applied to a cathode to turn it on.
BCO to seven segment decoder, IC 7447 is used to apply low voltages at
cathodes according to BCD input applied to 7447.
This circuit connection is referred to as a static display.

Fig. 3.31 Circuit for driving single seven segment LED display
The value of the resistor in series with the segment can be calculated
as follows: Vcc — drop across LED segment — IR = O.
Drop across LED segment is nearly
1.5 V. IR = Vcc. - 1.5 V
= 5 — 1.5 V
= 3.5 V
Each LED segment requires a current of between 5 and 30 mA to light.
Let‘s assume that current through LED segment is 15 mA and R=35V/15mA =
233ohm
The voltage drop across the LED and the output of 7447 are
not exactly predictable.
A standard value 220 Q can be used.
The static display circuits work well for driving just one or two LED
digits. When there is more number of digits, the first problem is
power consumption.
For worst-case calculations, assume that all eight digits with all segments
are lit. Therefore, worst case current required is
I = 8 (digits) x 7 (segment) x 15 mA (current per segment)
=84OmA

A second problem of the static approach is that each display digit requires a
separate BCD to 7 segment decoder.

Multiplexed Display
To solve the problems of the static display approach, multiplexed display
method is used.
Fig. 3.32 shows the 4 seven segment displays connected using
multiplexed method.
Here, common anode seven segment LEDs are used.

207
 Fig 3.32 Seven segment display in multiplexed connection

Anodes are connected to +5V through transistor, Cathodes of all seven

segments are connected in parallel and then to the output of 7447 IC
through resistors.
The same number only if all the digits are turned on at the same time.
The PNP transistors connected in series with the common anode of each
digit act as an ON and OFF switch for that digit. Here‘s how the
multiplexing process works.
The BCD code for digit 1 is first output from port A, to the 7447.
The 7447, B to seven segment decoder outputs the corresponding seven
segment code on the segment bus lines.
The transistor Q connected to digit 1 is then turned on by outputting a
low to that bit of port B.
All of the rest of the bits of port B are made high.
The BCD code for digit 2 is then output to the port A, and bit pattern to
turn on digit 2 is output on port B.
After 2ms, digit 2 is turned off and the process is repeated for digit 3 and
digit 4.
After completion of turn for each digit, the entire digits arc lit again in
turn In multiplexed display, the segment current is kept in between 40 mA
to 60 mA.

Example: Interface an 8-digit 7 segment LED display using 8255 to the 8086 is
shown in figure 3.33

208
 Figure 3.33 Digit 7-segment display interface using 8255
Software:
The control word to program 8255 according to hardware
connections. For 8255 Port A and B are used as output ports.
Control word format for 8255

3.9.3 LCD DISPLAY

The liquid crystals are one of the most fascinating material systems
in nature, having properties of liquids as well as of a solid crystal.
The terms liquid crystal refers to the fact that these compounds have a
crystalline arrangement of molecules, yet they flow like a liquid.
Liquid crystal displays do not emit or generate light, but rather alter
externally generated illumination.
Their ability to modulate light when electrical signal is applied has made
them very useful in flat panel display technology.
There are two types of liquid crystal displays (LCDs) according to the
theory of operation:
1. Dynamic scattering
2. Field effect.
Fig. 3.34 shows the construction of a typical liquid crystal display. It
consists of two glass plates with a liquid crystal fluid in between.
The back plate is coated with thin transparent layer of conductive
material.
Whereas front plate has a photo etched conductive coating with seven segment
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pattern as shown in Fig. 3.34.
Orientation order is maintained in the crystal allowing light to transmit.
This makes LCD display clear.

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 The current through the liquid crystal causes orientation order to collapse.
The random orientation results scattering of light which lights display
segment on a dark background.

Fig. 3.34 Liquid crystal display construction

Fig. 3.35 shows the circuit for driving LCD seven segment display using IC 4543B.

Figure 3.35 LCD seven segment display using IC 4543B

Fig.3.35 Circuit for driving LCD seven segment display using 4543B
The 45438 BCD-to-7 segment latch/decoder/driver is designed for
liquid crystal displays.
Pins A, 8, C and D represent BCD inputs with A as a least significant bit
(LSB) and D as a most significant bit (MSB).
Pins a through g are the seven segment outputs.
The 4543B has three control terminals: LD (Latch Disable), PH (Phase),
and BL (Blank).
The state of the PH terminal depends on the type of display that is
being driven. For driving LCD displays, a square wave (about 60Hz
swinging fully between the
GND and Vcc values) must be applied to the phase terminal.
The display can be blanked by simply driving the BL terminal to the logic
high state.
When the LD terminal is in its normal high state, BCD inputs are decoded
and fed directly to the seven segment output terminals of the IC.
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 When the LD terminal is pulled low, the BCD input signals that are
present at the moment of transition are latched into memory and fed to
the seven segment outputs.

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 Fig. 3.36 4-7 segment LCD display driving circuit
The Fig. 4.16 shows how above circuit can be used to drive a 4-
digit no multiplexed, 7-segment LCD display.
BCO input for each display is latched in the corresponding latch.
The latch enable signals are activated using 2: 4 decoder in
synchronization with the BCO inputs.
LCD Modules allow display of characters as well as numbers. They are
available in 16 x 2, 20 x 1, 20 x 2, 20 x 4 and 40 x 2 sizes.
The first figure represents number of character in each line and
second figure represents number of lines the display has.
In this section, we see the interfacing of 20 x 2 LCD display
module to microprocessor/microcontroller system through 8255.
In this module the display is organized as two lines, each of 20
characters. The module has 14-pins.The function of each pin is
given in the table 8.9.

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 Table 3.12 Pin description for LCD module

The Fig. 3.37 shows the interfacing of a 20 character x 2-line LCD module with the
8051.
As shown in the Fig. 3.37, the data lines are connected to the port I of 8051 and
control lines RS, R/V and E are driven by 3.2, 3.3 and 3.1 lines of port 3,
respectively.
The voltage at VEE pin is adjusted by a potentiometer to adjust the contrast of the
LCD.

Fig. 3.37 Interfacing LCD module with 8051

The display can be controlled by issuing proper commands to the LCD module,
The table 3.13 lists the command available for LCD module.

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 Figure 3.13 (a) LCD module Commands

Figure 3.13 (b) LCD module Commands

3.9.4 KEYBOARD INTERFACING

For interfacing keyboard to the microprocessor based systems, usually push

button keys are used. These push button keys when pressed. Bounces a few
times, closing and opening the contacts before providing a steady reading, as
shown in the Fig. 3.38 Reading taken during bouncing period may be faulty.
Therefore, microprocessor must wait until the key reach to a steady state; this is
known as key de bounce.

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 Figure 3.38 Bouncing of Key Switch
3.9.4.1 Key Debounce using Hardware

Fig. 3.39 shows the circuit diagram of key debounce. It consists of flip flop.
The output of flip-flop shown in Fig. 3.39 is logic t when key is at position. A
(unpressed) and it is logic 0 when key is t position B

Figure 3.39 Circuit diagram of key debounce

3.9.4.2 Key Debouncing using Software

In the software technique, when a key press is found, the

microprocessor waits for at Least.
10ms before it accepts the key as an input.
This 10 ms period is sufficient to settle key at
steady state. Fig. 3.40 shows the flowchart with key
debounce technique.

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 Figure 3.40 Flowchart with key debounce technique
3.9.4.3 Simple keyboard interface
Fig 3.41 shows simple keyboard interface

Figure 3.41 Simple keyboard interface

Here eight keys are individually connected to specific pins of input port. Each
port pin gives the status of key connected to that pin. When port pin is logic 1,
key is open. Otherwise key s closed is shown in below.

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3.9.4.4 Matrix Keyboard Interface
In simple keyboard interface one input line is required to interface one
key and pins number will increase with number of keys.
Therefore, such technique is not suitable when it is necessary to
interface large number of keys. To reduce number of connections keys are
arranged in the mat form as shown in the Fig. 4.23

Fig. 3.42 Matrix keyboard

Fig. 4.23 shows sixteen keys arranged in four rows and four columns.
When keys are open row and column do not have any connection, when a
key is pressed.
It shorts corresponding one row and one column.
This matrix keyboard requires eight lines to make all the connections
instead of the sixteen hours required if the keys are connected individually,
as shown in Fig. 4.23
Fig. 4.23 shows the interfacing of matrix keyboard.

It requires two ports:

1. an input port
2. An output port.
Rows are connected to the input port referred to as returned lines, and
columns are connected to the output port referred to as scan lines.
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 When all keys are open row and column do not have any connection.
When any key is pressed it shorts corresponding row and column.

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 If the output line of this column is low, it makes corresponding row line
low; otherwise the status of row line is high.
The key is identified by data sent on the output port and input code
received from the input port. The following section explains the steps
required to identify pressed key.

Fig 3.43 Matrix keyboard connections

Check 1: Whether any key is pressed or not

1. Make all column lines zero by sending low on all output lines. This activates all
keys in the keyboard matrix
2. Read the status of return Lines. If the status of all lines is logic high, key is
not pressed; otherwise key is pressed.
Check 2:
1. Activate keys from any one column by making any one column line zero.
2. Read the status of return lines. The zero on any return line indicates key is
pressed from the corresponding row and selected column
3. Activate the keys from the next column and repeat 2 and 3 for all columns.
In Fig. 4.25 the scan lines are connected to the port C,. of 8255 and returns lines
are connected to the port C1, of 8255.

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Figure 3.44 Interfacing of 4 X 4 keyboard with 8086

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 Part-A (2 Marks Questions and Answers)
1. What are the modes of operation used in 8253?
1. Mode 0 (Interrupt on terminal count)
2. Mode 1 (Programmable mono shot)
3. Mode 2 (Rate generator)
4. Mode 3 (Square wave generator)
5. Mode 4 (Software triggered strobe)
6. Mode 5 (Hardware triggered strobe)

2. What are the different types of write operations used in 8253?

There are two types of write operations in 8253
(1)Writing a control word register
(2)Writing a count value into a count
register The control word register
contents are used for
(a)Initializing the operating modes (mode 0-mode4)
(b)Selection of counters (counter 0- counter 2)
(c) Choosing binary /BCD counters
(d)Loading of the counter registers.
The mode control register is a write only register and the CPU cannot read its
contents.

3. Give the different types of command words used in 8259a?

The command words of 8259A are classified in two groups
1. Initialization command words (ICWs)
2. Operation command words (OCWs)

4. Give the operating modes of 8259?

(a) Fully Nested Mode
(b)End of Interrupt (EOI)
(c) Automatic Rotation
(d)Automatic EOI Mode
(e) Specific Rotation
(f)Special Mask Mode
(g)Edge and level Triggered Mode
(h)Reading 8259 Status
(i) Poll command
(j) Special Fully Nested Mode
(k)Buffered mode
(l) Cascade mode

5. Define scan counter? (Nov/Dec 2011)

The scan counter has two modes to scan the key matrix and refresh the
display. In the encoded mode, the counter provides binary count that is to be
externally decoded to provide the scan lines for keyboard and display. In the
decoded scan mode, the counter internally decodes the least significant 2 bits
and pro vides a decoded 1 out of scan on SL0- SL3.

6. What is the output modes used in 8279?

8279 provides two output modes for selecting the display options.
1. Display Scan In this mode, 8279 provides 8 or 16 character-multiplexed
displays those can be organized as dual 4-bit or single 8-bit display units.
2. Display Entry 8279 allows options for data entry on the displays. The
display data is entered for display from the right side or from the left side.
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7. What are the modes used in keyboard modes?
1. Scanned Keyboard mode with 2 Key Lockout.

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2. Scanned Keyboard with N-key Rollover.
3. Scanned Keyboard special Error Mode.
4. Sensor Matrix Mode.

8. What are the modes used in display modes?

1. Left Entry mode In the left entry mode, the data is entered from the left
side of the display unit.
2. Right Entry Mode In the right entry mode, the first entry to be displayed is
entered on the rightmost display.

9. What is the use of modem control unit in 8251?

The modem control unit handles the modem handshake signals to
coordinate the communication between the modem and the USART.

10. Give the register organization of 8257?

The 8257 perform the DMA operation over four independent DMA
channels. Each of the four channels of 8257 has a pair of two 16-bit registers.
DMA address register and terminal count register. Also, there are two common
registers for all the channels; namely, mode set registers and status register.
Thus there are a total of ten registers. The CPU selects one of these ten registers
using address lines A - 0 A -3.

11. What is the function of DMA address register?

Each DMA channel has one DMA address register. The function of this
register is to store the address of the starting memory location, which will be
accessed by the DMA channel. Thus the starting address of the memory block
that will be accessed by the device is first loaded in the DMA address register of
the channel. Naturally, the device that wants to transfer data over a DMA
channel, will access the block of memory with the starting address stored in the
DMA Address

12. What is the use of terminal count register?

Each of the four DMA channels of 8257 has one terminal count register.
This 16-bit register is used for ascertaining that the data transfer through a DMA
channel ceases or stops after the required number of DMA cycles.

13. What is the function of mode set register in 8257?

The mode set register is used for programming the 8257 as per the
requirements of the system. The function of the mode set register is to enable
the DMA channels individually and also to set the various modes of operation.

14. Distinguish between the memories mapped I/O peripheral I/O.

memories mapped I/O Peripheral I/O

16-bit device address 8-bit device address

More hardware is required Less hardware is required to

to decode 16-bit address decode 8-bit address

Arithmetic or logic operation can be

Arithmetic or logical operation
directly performed with I/O data cannot be directly performed
with data I/O data

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15. List the operation modes of 8255
a) I.O Mode
i. Mode 0-Simple Input/Output.
ii. Mode 1-Strobed Input/output (Handshake mode)
iii.Mode 2-Strobed bidirectional mode
b) Bit Set/Reset Mode

16. What is a control word?

It is a word stored in a register (control register) used to control the
operation of a program digital device.

17. What is the purpose of control word written to control register in 8255? (April/May
2011)
The control words written to control register specify an I/O function for
each I.O port.
The bit D7 of the control word determines either the I/O function of the BSR
function.

18. What is the size of ports in 8255?

Port-A: 8-bits
Port-B: 8-bits
Port-CU: 4-
bits Port-CL:
4-bits

19. What is memory mapping? (Nov/Dec 2007)

The assignment of memory addresses to various registers in a memory
chip is called as memory mapping.

20. What is I/O mapping? (Nov/Dec 2007)

The assignment of addresses to various I/O devices in the memory chip is
called as I/O mapping.

21. What is an USART? (Nov/Dec 2007)

USART stands for universal synchronous/Asynchronous Receiver/
Transmitter. It is a programmable communication interface that can
communicate by using either synchronous or asynchronous serial data.

22. What is the use of 8251 chip?

8251 chip is mainly used as the asynchronous serial interface between the
processor and the external equipment.

23. List the major components of the keyboard/Display interface.

a. Keyboard section b. Scan section c. Display section d. CPU interface section

24. What is Key bouncing?

Mechanical switches are used as keys in most of the keyboards. When a
key is pressed the contact bounce back and forth and settle down only after a
small time delay (about 20ms). Even though a key is actuated once, it will
appear to have been actuated several times. This problem is called Key
Bouncing.

25. Define HRQ?

The hold request output requests the access of the system bus. In non-
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cascaded 8257 systems, this is connected with HOLD pin of CPU. In cascade
mode, this pin of a slave is connected with a DRQ input line of the master 8257,
while that of the master is connected with HOLD input of the CPU.

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26. What is the use of stepper motor?
A stepper motor is a device used to obtain an accurate position control of
rotating shafts. A stepper motor employs rotation of its shaft in terms of steps,
rather than continuous rotation as in case of AC or DC motor.

27. What is TXD?

TXD- Transmitter Data Output This output pin carries serial stream of the
transmitted data bits along with other information like start bit, stop bits and
priority bit.

28. What is RXD?

RXD- Receive Data Input This input pin of 8251A receives a composite
stream of the data to be received by 8251A.

29. What are the basic modes of operation of 8255? (April/May 2008)
There are two basic modes of operation of 8255, viz.
1. I/O mode.
2. BSR mode.
In I/O mode, the 8255 ports work as programmable I/O ports, while In BSR mode
only port C (PC0-PC7) can be used to set or reset its individual port bits. Under
the IO mode of operation, further there are three modes of operation of 8 255,
So as to support different types of applications, viz. mode 0, mode 1 and mode 2.
Mode 0 - Basic I/O mode
Mode 1 - Strobed I/O mode
Mode 2 - Strobed bi-directional I/O

30. Write the features of mode 0 in 8255?

1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and
lower) are available. The two 4-bit ports can be combined used as a third 8-bit
port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched
.4. A maximum of four ports are available so that overall 16 I/O configurations are
possible.

31. What are the features used mode 1 in 8255?

Two groups – group A and group B are available for strobed data transfer.
1. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
2. The 8-bit data port can be either used as input or output port. The inputs and
outputs both are latched.
3. Out of 8-bit port C, PC0-PC2 is used to generate control signals for port B and
PC3=PC5 are used to generate control signals for port A. The lines PC6, PC7 may
be used as independent data lines.

Part-B (16 Marks Questions)

1. Draw the block diagram of 8279 keyboard/ Display controller and explain
how to interface the Hex Key pad and 7- segment LEDs using 8279. (Ref
Sec 3.4) (May/June 2010, Nov/Dec 2012, May/June 2013)
2. Draw the functional block diagram of 8254 timer and explain the different
modes of operation. (Ref Sec 3.5) (May/June 2010)
3. Draw the block diagram of 8259A and explain how to program 8259A. (Ref
Sec 3.7.1) (May/June 2010)
4. Explain the data transfer on a parallel printer interface using a timing
diagram(Ref Sec 3.2) (Nov/Dec 2010)
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5. Explain the interfacing of 4 X 4 matrix keyboard to the 8051
microcontroller with neat diagram(Ref Sec 3.9.4) (Nov/Dec 2011)

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6. What are the signals a microprocessor should have to support DMA? List
and explain the sequence of operations carried out during a DMA transfer.
(Ref Sec 3.8.1)(Nov/Dec 2010,Apr/May 2011, May/June 2014)
7. Explain the four modes of keyboard operation in 8279. (Ref Sec 3.4) (Nov/Dec
2010)
8. Draw the architectural block diagram of 8259 Programmable interrupt
controller and Explain. (Ref Sec 3.7.1) (Nov/Dec 2012)
9. Explain the parallel communication interface with microprocessor
(Ref Sec 3.2.3)(Nov/Dec 2012)
10.Explain the (i)modes of operation of timer and (ii)operation of interrupt
controller
(Ref Sec 3.7) (May/June 2013, Nov/Dec 2012, May/June 2014)
11.Describe about serial port interface of 8051(Ref Sec 3.3) (May/June 2013)
12.Draw the circuit diagram to interface an LCD with microcontroller and
explain how to Display the data using LCD. (Ref Sec 3.9.3) (May/June 2012,
Nov/Dec 2012)

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