S V ENGINEERING COLLEGE

KARAKAMBADI ROAD, TIRUPATI-517507

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

LECTURE NOTES

20A02602T DIGITAL COMPUTING PLATFORMS

Regulation –R20
Academic Year (2023 – 24)
Year / Semester : III / II

Prepared by
K.V.L.KEERTHI,
Assistant professor
Department of ECE
UNIT IV:
Introduction to the TMS320LF2407 DSP Controller Basic architectural features - Physical Memory -
Software Tools. Introduction to Interrupts - Interrupt Hierarchy - Interrupt Control Registers. C2xx DSP
CPU and Instruction Set: Introduction & code Generation - Components of the C2xx DSP core - Mapping
External Devices to the C2xx core - peripheral interface - system configuration registers - Memory -
Memory Addressing Modes - Assembly Programming Using the C2xx DSP Instruction set.
Learning Outcomes:-
After completion of this unit student will
 To know about features of DSP controller C2xx as one of the DCPs
 To know about various instruction sets, control registers of C2xx DSP core
 To know about mapping of external devices to the DSP core
To know about assembly programming using the instruction sets of TMS320LF2407 DSP controller
 CONTENTS
IV 2
UNIT-IV: TMS320LF2407 DSP Controller
Introduction 2
Unit-III notes 11
Solved Problems
Part A Questions (2 marks) 68
Part B Questions (10 marks) 70
 UNIT –IV

Introduction to the TMS320 Controller

Introduction

Embedded Systems Architecture Types

The 8051 microcontrollers work with 8bit data bus. So they can support external data
memory up to 64K and external program memory of 64k at best. Collectively, 8051
microcontrollers can address 128k of external memory.
When data and code lie in different memory blocks, then the architecture is referred
as Harvard architecture. In case data and code lie in the same memory block, then the
architecture is referred as Von Neumann architecture.
Von Neumann Architecture
The Von Neumann architecture was first proposed by a computer scientist John von
Neumann. In this architecture, one data path or bus exists for both instruction and data. As a
result, the CPU does one operation at a time. It either fetches an instruction from memory, or
performs read/write operation on data. So an instruction fetch and a data operation cannot occur
simultaneously, sharing a common bus.

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Von-Neumann architecture supports simple hardware. It allows the use of a single, sequential
memory. Today's processing speeds vastly outpace memory access times, and we employ a very
fast but small amount of memory cache local to the processor.
Harvard Architecture
The Harvard architecture offers separate storage and signal buses for instructions
and data. This architecture has data storage entirely contained within the CPU, and there is no
access to the instruction storage as data. Computers have separate memory areas for program
instructions and data using internal data buses, allowing simultaneous access to both instructions
and data. Programs needed to be loaded by an operator; the processor could not boot itself. In a
Harvard architecture, there is no need to make the two memories share properties.

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Figure. Harvard Architecture

Von Neumann Architecture vs Harvard Architecture

The following points distinguish the Von Neumann Architecture from the Harvard Architecture.

Von-Neumann Architecture Harvard Architecture

 Single memory to be shared by both code  Separate memories for code and data.
and data  Single clock cycle is sufficient, as
 Processor needs to fetch code in a separate buses are used to access code
separate clock cycle and data in another and data.
clock cycle. So it requires two clock  Complex instruction decoding, Slower
cycles. in speed, thus more time consuming
 Easier instruction decoding, Higher  Complex in design.
speed, thus less time consuming
 Simple in design.

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CISC and RISC
CISC is a Complex Instruction Set Computer. It is a computer that can address a large
number of instructions. In the early 1980s, computer designers recommended that computers
should use fewer instructions with simple constructs so that they can be executed much faster
within the CPU without having to use memory. Such computers are classified as Reduced
Instruction Set Computer or RISC.
CISC vs RISC
The following points differentiate a CISC from a RISC –

CISC RISC

 CISC is Complex Instruction Set RISC is Reduced Instruction Set

Computer Computers
 Simpler design of compiler, smaller number of instruction so that it
considering larger set of instructions. can operate at a higher speed. Complex
 Many addressing modes causing design of compiler.
complex instruction formats. Few addressing modes, fix instruction
 Higher clock cycles per second. format
 Control unit implements large Low clock cycle per second
instruction set using micro program unit. Each instruction is to be executed
 Slower execution, as instructions are to by hardware control.
be read from memory and decoded by Faster execution, as each instruction is
the decoder unit. to be executed by hardware
 CISC instructions varied in length, RISC instructions are all the same
 Pipelining is not possible. length
Pipelining of instructions is possible,
considering same length size.

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 I/O HARDWARE
Embedded processors, be they microcontrollers, DSP processors, or general-purpose processors,
typically include a number of input and output (I/O) mechanisms on chip, exposed to designers
as pins of the chip. In this section, we review some of the more common interfaces provided,
illustrating their properties through the following running example.
The I/O ports are used to connect input and output devices. The common input devices for an
embedded system include keypads, switches, buttons, knobs, and all kinds of sensors (light,
temperature, pressure, etc). The output devices include Light Emitting Diodes (LED), Liquid
Crystal Displays (LCD), printers, alarms, actuators , etc. Some devices support both input and
output, such as communication interfaces including Network Interface Cards (NIC), modems, and
mobile phones.

TIMERS AND INTERRUPTS

Time and event management in embedded systems
• Using the mbed Timer object
• Using multiple timers
• Using the mbed Ticker object
• Hardware interrupts
• External interrupts on the mbed
• Switch debouncing for interrupt control
Time and event management in embedded systems
• Many embedded systems need high precision timing control and the ability to respond urgently
to critical requests
• For example:
– A video camera needs to capture image data at very specific time intervals, and to a high
degree of accuracy, to enable smooth playback
– A automotive system needs to be able to respond rapidly to a crash detection sensor in order to
activate the passenger airbag
• Interrupts allow software processes to be halted while another, higher priority section of
software executes

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• Interrupt routines can be programmed to execute on timed events or by events that occur
externally in hardware
• Routines executed by events that occur from an external source (e.g. a mouse click or input
from another program) can be referred to as ‘event driven’.
An introduction to timers
• Interrupts in embedded systems can be thought of as functions which are called by specific
events rather than directly in code.
• The simplest type of interrupt is one which automatically increments a counter at a periodic
interval, this is done behind the scenes while the software is operating.
• Most microcontrollers have built in timers or real-time-interrupts which can be used for this
purpose.
• The main code can then be executed at specified time increments by evaluating the counter
value.
• For example, we can set some pieces of software to operate every 10ms and others to operate
every 100ms. We call this scheduled programming.
Using the mbed Timer object
We can use the mbed Timer object to perform scheduled programming:

Using multiple timers

With scheduled programs we often need to execute different sections of code at different rates.

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Consider an automotive system:
 The engine spark, valve and fuel injection system need to be controlled and executed at a
high speed, perhaps every 1 ms or less given that the engine revolves at anything up to
8,000 revs per minute.
 The fuel tank level monitoring system needs to report the fuel level less often, perhaps
every 1000 ms is sufficient.
 There is no point in executing both the injection management and the fuel level
management systems at the same rate.
• For these reasons we can use synchronous programs to improve efficiency

INTERFACING USING SYSTEM BUS

Interfacing of processor, memory and IO devices using memory system bus
System bus ─ interconnections for a simple bus structure has three sets of signals
System bus ─ defines by address bus, data bus, and control bus
A system-bus interfacing-design is according to the timing diagrams of processor signals, speed,
and word length for instructions and data.
Interconnections for a simple bus structure

Interfacing of processor, memory and IO devices using memory system bus

ADDRESS BUS: Processor issues the address of the instruction byte or word to memory system
through the address bus. Processor execution unit, when required, issues the address of
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data (byte or word) to be read or written using the memory system through address bus. The
address bus of 32-bits used to fetch the instruction or data from an address specified by 32-bit
number.
EXAMPLE
 Let a processor at the start reset the program counter at address 0. Then the processor issues
address 0 on the bus and the instruction at address 0 is fetched from memory on reset
 Let a processor instruction be such that it needs to load register r1 from the memory address
M. The processor issues address M on the address bus and data at address M is fetched.
DATA BUS: Data Bus • Instruction fetch─ Processor issues the address of the instruction, it gets
back the instruction through the data bus. • Data Read─ When it issues the address of the data, it
loads the data through data bus. • Data Write ─ When it issues the address of the data, it stores the
data in the memory through the data bus. A data bus of 32-bits fetches, loads, or stores the
instruction or data of 32-bits.
EXAMPLE
 Processor issues address m for an instruction, it fetches the instruction through data bus
from address m. [For a 32-bit instruction, word at data bus from addresses m, m + 1, m +
2, and m + 3.]
 Instruction executes for store of register r1 bits to the memory address M, the processor
issues address M on the bus and sends the data at address M through the data bus. [For 32-
bit data, word at data bus sent to the memory addresses M, M + 1, M + 2, and M + 3.]
CONTROL BUS Control Bus Issues signals to control the timing of various actions during
interconnection. Signals synchronize all the subsystems. address latch enable (ALE)[ Address
Strobe (AS) or address valid, (ADV)], memory ‘read’ (RD) or ‘write’ (WR) or IO ‘read’ (IORD)
or ‘write,’(IOWR) or ‘data valid’(DAV) Other control signals as per the processor design.
Interrupts and DMA Control Signals Interrupts and DMA Control Signals Interrupt
acknowledge (INTA) [on a request for drawing the processor attention to an event] INT (Interrupt)
from external device interrupt to the system Hold acknowledge (HLDA) [on an

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 external hold request for permitting use of the system buses] HOLD when external device sends
a hold request for direct memory access (DMA).
Program memory access and data buses multiplexed for memory access in Harvard
Architecture
Address and data buses are multiplexed
Control signal PSEN active when accessing program memory using the address and data buses
Control signal Read or Write active when accessing data memory using the address and data
buses
Time division multiplexed (TDM) address and data bits for the memories
TDM ─ Different time slots, there are different sets (channel) of the signals.
Address signals during one time slot t. and data bus signals in another time slot.
Interfacing circuit for the demultiplexing of the buses uses a control signal in such systems.
Control signal Address Latch Enable (ALE) in 8051, Address Strobe (AS) in 68HC11 and
address valid (ADV) in 80196. ALE or AS or ADV demultiplexes the address and data buses to
the devices
1. Interfacing Using System and IO
2. Interfacing Using System and IO Buses
System Bus and IO Bus
System bus interconnects
 processor
 memory systems and subsystems
 Another set of signals called I/O bus
 Interfacing of processor with system bus at first level and IO bus at second level
Popular IO buses and wireless communication
PCI Bus interfaces to devices designed to meet the PCI standard.
USB interfaces to devices designed to meet the USB IOs
PCI Bus interfaces to devices designed to meet the PCI standard. USB interfaces to devices
designed to meet the USB IOs

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TMS320LF2407 DSP Controller

4.1 TMS320LF2407 DSP Controller BASIC ARCHITECTURE

The 240xA devices offer the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost,
low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital
motor and motion control applications, have been integrated to provide a true single-chip DSP controller. It
offers increased processing performance and a higher level of peripheral integration.

Memory system bus and I/O bus interconnections in a bus structure

MSP430 FUNCTIONAL BLOCK DIAGRAM (Mixed signal controller)

MSP430 microcontrollers (MCUs) from Texas Instruments are 16-bit, RISC-based, mixed-
signal processors designed specifically for ultra-low power.

On the left is the CPU and its supporting hardware, including the clock generator. The emulation,
JTAG interface and Spy-Bi-Wire are used to communicate with a desktop computer when
downloading a program and for debugging.
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Figure 4.1 Block diagram of MSP 430 Micro controller

• The main blocks are linked by the memory address bus (MAB) and memory data bus (MDB).
• These devices have flash memory, 1KB in the F2003 or 2KB in the F2013, and 128 bytes of
RAM.
• Six blocks are shown for peripheral functions (there are many more in larger devices).
All MSP430s include input/output ports, Timer A and a watchdog timer, although the details
differ.
The universal serial interface (USI) and sigma–delta analog-to-digital converter (SD16_A) are
particular features of this device.
• The brownout protection comes into action if the supply voltage drops to a dangerous level.
Most devices include this but not some of the MSP430x1xx family.

There are ground and power supply connections. Ground is labeled VSS and is taken to define
0V. The supply connection is VCC.
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For many years, the standard for logic was VCC =+5V but most devices now work from lower
voltages and a range of 1.8–3.6V is specified for the F2013. The performance of the device depends
on VCC. For example, it is unable to program the flash memory if VCC < 2.2V and the maximum
clock frequency of 16MHz is available only if VCC ≥ 3.3V. TI uses a quaint notation for the power
connections.
The S stands for the source of a field-effect transistor, while the C stands for the collector of a
bipolar junction transistor, a quite different device.
The MSP430, like most modern integrated circuits, is built using complementary metal–oxide–
silicon (CMOS) technology and field-effect transistors. it contains any bipolar junction transistors
except possibly in some of the analog peripherals.
There is only one pair of address and data buses, as expected with a von Neumann architecture.
Some addresses must therefore point to RAM and some to flash, so it is a good idea to explore the
memory map next.

USB debugging interface (MSP-FET430UIF) connects a flash-based MSP430 MCU to a PC

for real- time, in-system programming and debugging

BOARD FEATURES:
• MCU: MSP430FG4619 with 120K Bytes Program Flash, 256 Bytes data Flash, 4K Bytes
RAM
• NOKIA 6610 LCD 128x128 pixels 12 bit color LCD with backlight

• Joystick with 4 directions and push button function

• SD/MMC card connector – (These are universal low-cost, high-speed data storage cards )

• MMA7620 3 axis accelerometer -( micromachined accelerometer (MMA) series acceleration

sensors are designed for end products or embedded systems that require measurement of forces
resulting from tilt, motion, positioning, shock or vibration.)
• IrDA transceiver (Infrared data association wireless device for one meter)

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• UEXT (Universal extension connector) connector - UEXT is a board to board connector which
supports three serial communication interfaces - I2C, SPI and RS232.

• JTAG connector -The interface connects to an on-chip Test Access Port (TAP) that implements
a stateful protocol to access a set of test registers that present chip logic levels and device
capabilities of various parts.

• 32 768 Hz oscillator crystal

• 8Mhz crystal oscillator
• power supply voltage regulators and filtering capacitor
• extension headers for all uC pins

• Battery holder for 2 x 1.5 V “AA” batteries

• PCB: FR-4, 1.5 mm (0,062"), solder mask, white silkscreen component print
• Dimensions: 81.20 x 62.48 mm (3.20 x 2.46")

PROCESSOR FEATURES:
MSP430-4619LCD board use mixed signal microcontroller MSP430FG4619 from Texas
Instruments, with these features: −
Low Supply-Voltage Range, 1.8 V to 3.6 V
− Ultralow-Power Consumption:
− Active Mode: 350 μA at 1 MHz, 2.2 V
− Standby Mode: 1.1 μA
− Off Mode (RAM Retention): 0.3 μA
− Five Power Saving Modes
− Wake-Up From Standby Mode in less than 6 μs
− 16-Bit RISC Architecture, Extended Memory, 125-ns Instruction Cycle Time
− Three Channel Internal DMA
− 12-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature
− Three Configurable Operational Amplifiers
− Dual 12-Bit D/A Converters With Synchronization
− 16-Bit Timer A With Three Capture/Compare Registers
− 16-Bit Timer_B With Seven Capture/Compare-With-Shadow Registers
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− On-Chip Comparator
− Supply Voltage Supervisor/Monitor With Programmable Level Detection
− Serial Communication Interface (USART1), Select Asynchronous UART or Synchronous SPI
by Software − Universal Serial Communication Interface
− Enhanced UART supporting auto -baud rate detection
− IrDA Encoder and Decoder
− Synchronous SPI
− I2CTM − Serial Onboard Programming, No External Programming Voltage Needed
Programmable Code Protection by Security Fuse
− Brownout Detector
− Basic Timer with Real Time Clock Feature
− Integrated LCD Driver up to 160 Segments With Regulated Charge Pump
− 120KB+256B Flash Memory
− 4KB RAM

ARCHITECTURE
Introduction The types of devices such as microprocessor, microcontroller, processor, digital
signal processor (DSP), amongst others, in a certain manner, are related to the same device – the
ASIC (Application Specific Integrated Circuit). Each processing device executes instructions,
following a determined program applied to the inputs and shares architectural characteristics
developed from the first microprocessors created in 1971. In the three decades after the
development of the first microprocessor, huge developments and innovations have been made in
this engineering field. Any of the terms used at the beginning of this section are correct to define
a microprocessor, although each one has different characteristics and applications. The definition
of a microcontroller is somewhat difficult due to the constantly changing nature of the silicon
industry. What we today consider a microcontroller with medium capabilities is several orders of
magnitude more powerful, than the computer used on the first space missions. Nevertheless, some
generalizations can be made as to what characterizes a microcontroller. Typically, microcontrollers
are selected for embedded systems projects, i.e., control systems with a limited number of inputs
and outputs where the controller is embedded into the system. The programmable SoC (system-
on-chip) concept started in 1972 with the 4-bit TMS1000 microcomputer developed by Texas
Instruments (TI), and in those days it was ideal for
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applications such as calculators and ovens. This term was changed to Microcontroller Unit (MCU),
which was more descriptive of a typical application. Nowadays, MCUs are at the heart of many
physical systems, with higher levels of integration and processing power at lower power
consumption.
The following list presents several qualities that define a microcontroller:
Cost: Usually, the microcontrollers are high-volume, low cost devices;
Clock frequency: Compared with other devices (microprocessors and DSPs), microcontrollers use
a low clock frequency. Microcontrollers today can run up to 100 MHz/ 100 Million Instructions
Per Second (MIPS)
Power consumption: orders of magnitude lower than their DSP and MPU
cousins;Bits: 4 bits (older devices) to 32 bits devices;
Memory: Limited available memory, usually less than 1 MByte;

Input/Output (I/O): Low to high (8-150) pin-out count.

Main characteristics of a MSP430 microcontroller
Although there are variants in devices in the family, a MSP430 microcontroller can be
characterized by: Low power consumption:
 A for RAM data retention;
 A for real time clock mode operation;
 0.8 A/MIPS at active operation.
 250
Low operation voltage (from 1.8 V to 3.6 V).
1. 1 < s clock start-up. 1
2. < 50 nA port leakage. Zero-power Brown-Out Reset (BOR).
3. On-chip analogue devices:
 10/12/16-bit Analogue-to-Digital Converter (ADC);
 12-bit dual Digital-to-Analogue Converter (DAC);
 Comparator-gated timers; Operational Amplifiers (OP Amps);
 Supply Voltage Supervisor (SVS).
16 bit RISC CPU:
 Instructions processing on either bits, bytes or words;
 Compact core design reduces power consumption and cost;

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  Compiler efficient;
 27 core instructions;
 7 addressing modes;
 Extensive vectored-interrupt capability.
Flexibility:
 Up to 256 kB In-System Programmable (ISP) Flash;
 Up to 100 pin options;
 USART, I2C, Timers;
 LCD driver;
 Embedded emulation
The microcontroller’s performance is directly related to the 16-bit data bus, the 7 addressing modes
and the reduced instructions set, which allows a shorter, denser programming code for fast
execution. These microcontroller families share a 16-bit CPU (Central Processing Unit) core,

RISC1 type, intelligent peripherals, and flexible clock system that interconnects using a Von
Neumann2 common memory address bus (MAB) and memory data bus (MDB) architecture.

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 Figure 4.2 MSP430 architecture

4.2 Physical Memory

The MSP430 is available with either Flash or ROM memory types. The memory type is identified by the letter
immediately following “MSP430” in the part numbers. Flash devices: Identified by the letter “F” in the part
numbers, having the advantage that the code space can be erased and reprogrammed. ROM devices: Identified by
the letter “C” in the part numbers. They have the advantage of being very inexpensive because they are shipped
pre-programmed, which is the best solution for high-volume designs

Address space
All memory, including RAM, Flash/ROM, information memory, special function registers
(SFRs), and peripheral registers are mapped into a single, contiguous address space as shown in
Figure. Note: See the device-specific datasheets for specific memory maps. Code access is always
performed on even addresses. Data can be accessed as bytes or words.
.

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Figure 4.3 Memory Map.

For all devices, each memory location is formed by 1 data byte. The CPU is capable of
addressing data values either as bytes (8 bits) or words (16 bits). Words are always addressed at
an even address, which contain the least significant byte, followed by the next odd address, which
contains the most significant byte. For 8-bit operations, the data can be accessed from either odd
or even addresses, but for 16-bit operations, the data values can only be accessed from even
addresses.

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Flash/ROM
The start address of Flash/ROM depends on the amount of Flash/ROM present on the device.
The start address varies between 01100h (60k devices) to 0F800h (2k devices) and always runs
to the end of the address space at location 0FFFFh. Flash can be used for both code and data. Word
or byte tables can also be stored and read by the program from Flash/ROM. All code, tables, and
hard-coded constants reside in this memory space.
Information memory (Flash devices only)
The MSP430 flash devices contain an address space for information memory. It is like an onboard
EEPROM, where variables needed for the next power up can be stored during power down. It can
also be used as code memory. Flash memory may be written one byte or word at a time, but must
be erased in segments. The information memory is divided into two 128-byte segments. The first
of these segments is located at addresses 01000h through to 0107Fh (Segment B), and the second
is at address 01080h through to 010FFh (Segment A). This is the case in 4xx devices. It is 256
bytes (4 segments of 64 bytes each) in 2xx devices.
Boot memory (Flash devices only)
The MSP430 flash devices contain an address space for boot memory, located between addresses
0C00h through to 0FFFh. The “bootstrap loader” is located in this memory space, which is an
external interface that can be used to program the flash memory in addition to the JTAG. This
memory region is not accessible by other applications, so it cannot be overwritten accidentally.
The bootstrap loader performs some of the same functions as the JTAG interface (excepting the
security fuse programming), using the TI data structure protocol for UART communication at a
fixed data rate of 9600 baud.
RAM RAM always starts at address 0200h. The end address of RAM depends on the amount of
RAM present on the device. RAM is used for both code and data.
Peripheral Modules
Peripheral modules consist of all on-chip peripheral registers that are mapped into the address
space. These modules can be accessed with byte or word instructions, depending if the peripheral
module is 8-bit or 16-bit respectively. The 16-bit peripheral modules are located in the address
space from addresses 0100 through to 01FFh and the 8-bit peripheral modules are mapped into
memory from addresses 0010h through to 00FFh.

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 Special Function Registers (SFRs)
Some peripheral functions are mapped into memory with special dedicated functions. TheSpecial
Function Registers (SFRs) are located at memory addresses from 0000h to 000Fh, and are the
specific registers for:
Interrupt enables (locations 0000h and 0001h);
Interrupt flags (locations 0002h and 0003h);
Enable flags (locations 0004h and 0005h);
SFRs must be accessed using byte instructions only. See the device specific data sheets for the
applicable SFR bits.

4.3 Software Tools

Texas Instruments MSP430 Microcontroller (MCU) Development Tools

Texas Instruments MSP430 Microcontroller (MCU) Development Tools provides kits,
programmers, debuggers, software, GUIs, and IDEs to help customers evaluate and develop with
MSP430™ microcontrollers (MCUs) for sensing and measurement applications. From easy-to-
use LaunchPad™ development kits with code examples and libraries to more advanced
application-specific evaluation modules, graphical user interfaces (GUIs), and software. They also
have online training and the TI E2E forum, which provides everything the user needs to get a
design started.

4.4 Introduction to Interrupts

Interrupt vector table
The interrupt vector table is mapped at the very end of memory space (upper 16 words of
Flash/ROM), in locations 0FFE0h through to 0FFFEh (see the device-specific datasheets). The
priority of the interrupt vector increases with the word address.

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22
 4.5 Central Processing Unit (MSP430 CPU)
The RISC type architecture of the CPU is based on a short instruction set (27 instructions),
interconnected by a 3-stage instruction pipeline for instruction decoding. The CPU has a 16-bit
ALU, four dedicated registers and twelve working registers, which makes the MSP430 a high
performance microcontroller suitable for low power applications. The addition of twelve working
general purpose registers saves CPU cycles by allowing the storage of frequently used values and
variables instead of using RAM. The orthogonal instruction set allows the use of any addressing
mode for any instruction, which makes programming clear and consistent, with few exceptions,
increasing the compiler efficiency for high-level languages such as C.

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Figure. MSP430X CPU block diagram.

Arithmetic Logic Unit (ALU)

The MSP430 CPU includes an arithmetic logic unit (ALU) that handles addition, subtraction,
comparison and logical (AND, OR, XOR) operations. ALU operations can affect the overflow,
zero, negative, and carry flags in the status register.
MSP430 CPU registers
The CPU incorporates sixteen 16-bit registers:
Four registers (R0, R1, R2 and R3) have dedicated functions;

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 There are 12 working registers (R4 to R15) for general use.
R0: Program Counter (PC)
The 16-bit Program Counter (PC/R0) points to the next instruction to be read from memory and
executed by the CPU. The Program counter is implemented by the number of bytes used by the
instruction (2, 4, or 6 bytes, always even). It is important to remember that the PC is aligned at
even addresses, because the instructions are 16 bits, even though the individual memory addresses
contain 8-bit values.

R1: Stack Pointer (SP)

The Stack Pointer (SP/R1) is located in R1. 1st: stack can be used by user to store data for later
use (instructions: store by PUSH, retrieve by POP); 2nd: stack can be used by user or by compiler
for subroutine parameters (PUSH, POP in calling routine; addressed via offset calculation on stack
pointer (SP) in called subroutine); 3rd: used by subroutine calls to store the program counter value
for return at subroutine's end (RET); 4th: used by interrupt - system storesthe actual PC value first,
then the actual status register content (on top of stack) on return from interrupt (RETI) the system
get the same status as just before the interrupt happened (as long as none has changed the value on
TOS) and the same program counter value from stack.

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R2 – Status Register

The Status Register (SR/R2) stores the state and control bits. The system flags are changed
automatically by the CPU depending on the result of an operation in a register. The reserved bits
of the SR are used to support the constants generator. See the device-specific data sheets for more
details.

R2/R3: Constant Generator Registers (CG1/CG2)

Depending of the source-register addressing modes (As) value, six commonly used constants can
be generated without a code word or code memory access to retrieve them. This is a very powerful
feature, which allows the implementation of emulated instructions, for example, instead of
implementing a core instruction for an increment, the constant generator is used.

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R4 - R15: General–Purpose Registers
These general-purpose registers are used to store data values, address pointers, or index values and
can be accessed with byte or word instructions.

Main features of the MSP430X CPU architecture

The MSP430X CPU extends the addressing capabilities of the MSP430 family beyond 64 kB to
1 MB. To achieve this, there are some changes to the addressing modes and two new types of
instructions. One type of new instructions allows access to the entire address space, and the other
is designed for address calculations. The MSP430X CPU address bus is 20 bits, but the data bus is
still 16 bits. The CPU supports 8-bit, 16-bit and 20-bit memory accesses. Despite these changes,
the MSP430X CPU remains compatible with the MSP430 CPU, having a similar number of
registers.

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Although the MSP430X CPU structure is similar to that of the MSP430 CPU, there are some
differences that will now be discussed. With the exception of the status register SR, all MSP430X
registers are 20 bits. The CPU can now process 20-bit or 16-bit data.

MSP430X CPU registers

R0 (PC) - Program Counter
Has the same function as the MSP430 CPU, although now it has 20 bits.
R1 (SP) - Stack Pointer
Has the same function as the MSP430 CPU, although now it has 20 bits.
R2 (SR) - Status Register
Has the same function as the MSP430 CPU, but still only has 16 bits.

4. 6 Instruction Set
The instructions are thoroughly documented in the section “RISC 16-Bit CPU” of the family user’s
guides. The MSP430 has 27 native instructions, and a further 24 emulated instructions are defined
to make life easier for the programmer. These include common operations such as “clear,” which
is implemented as an ordinary move with a value of 0 provided by the constant generator. I list all
instructions for completeness but concentrate on the unusual features and traps for the unwary.
The instruction set is orthogonal with few exceptions, meaning that all addressing modes can be
used with all instructions and registers. I show the .w form foroperations that can use either bytes
or words. Aside: It sounds as though the MSP430 has fewer instructions than the PIC16 with 35,
but trivial comparisons of radically different processors are always misleading. It might be more
accurate to say that the PIC has 28 instructions with up to three addressing modes. For example,
the operand for arithmetic and logic instructions can be a

28
literal value, taken from a register whose address is given explicitly, or in a register whose address
is specified indirectly in FSR.
1 Movement Instructions
There is only the one mov instruction to move data. It can address all of memory as either source
or destination, including both registers in the CPU and the whole memory map. This is an excellent
feature. Some processors have distinct instructions for loading a CPU register from memory,
storing it to memory, and memory-to-memory moves if these are available at all:

mov.w src ,dst ; move (copy) dst = src

Note the order of the operands, which is the opposite of the equivalent statement in C (and some
other assembly languages).
Peculiarity: The status bits are not affected by mov. Strings in C end with the null character \0
and other lists are often terminated by 0, so it would be helpful to detect this. The Z flag is
affected by the move itself in many processors but an explicit test must be used in the MSP430.
Stack Operations
These push data onto the stack and pop them off, as described in the section “Stack Pointer (SP)”
on page 120:
push.w src ; push data onto stack *--SP = src
pop.w dst ; pop data off stack dst = *SP++ emulated
The SP is fixed to be even, so a word of stack space is always consumed, even if only a byte is
added. The pop operation is emulated using postincrement addressing but push requires a special
instruction because predecrement addressing is not available.

29
2 Arithmetic and Logic Instructions with Two Operands
Binary Arithmetic Instructions with Two Operands
These are fairly standard. The carry bit should be interpreted as “not borrow” for subtraction:

The compare operation cmp is the same as subtraction sub except that only the bits in SR are
affected; the result is not written back to the destination. There are many examples of operations
on more than one word with the carry/borrow bit in Section 5.1 of Application Reports (slaa024).
Maxfield and Brown [37] give an entertaining account of binary arithmetic.
Arithmetic Instructions with One Operand
All these are emulated, which means that the operand is always a destination:

The test operation is the special case of comparison with 0. In many processors the clear operation
differs from a move with the value 0 because a move sets the flags but a clear does not. This does
not apply to the MSP430 because a move does not set the flags.

30
Decimal Arithmetic
These instructions are used when operands are binary-coded decimal (BCD) rather than ordinary
binary values. This means that the value of each nibble is restricted to the range of unsigned,
decimal integers 0–9 instead of the full hexadecimal range 0–F. BCD is often used for values to
be displayed in decimal form because it saves having to convert the binary value to a set of decimal
digits. This is useful in a clock, for instance, as we see in the section “Simple Applications of the
LCD” on page 264. Maxfield has several articles explaining why BCD is important and how to
use it—even signed BCD [60, 63]:

There is only one native instruction for decimal arithmetic, dadd. This adds its source plus the
carry bit decimally to its destination. The result is a BCD number provided that the operands were
valid BCD numbers themselves. Some processors have a “decimal adjust” instruction instead,
which converts the value in a register from binary to BCD. The emulated instruction dadc adds
only the carry bit decimally to the destination. The CPU itself provides no other operations on
nibbles, but there are routines for converting between BCD and binary numbers in Section 5.5 of
Application Reports (slaa024) and I show an example in the section “Conversion from Binary to
Binary-Coded Decimal” on page 270. Peculiarity: The mnemonic dadd is misleading: It would
better have been called daddc for “decimal add with carry.” Make sure that you set or clear the
carry bit before using dadd unless the carry has been determined by a previous operation.
Logic Instructions with Two Operands
These are not quite the same as in many other processors:
-
The MSP430 has the usual and and exclusive-OR xor instructions but not an explicit inclusive-
OR. The and and bitwise test operations are identical except that bit is only a test and does not
change its destination.
Peculiarity: The Z bit is affected in the usual way by these operations and the carry bit is given
by C = ˜ Z. The idea of this is that the carry bit can subsequently be rotated into another register to
ease serial–parallel conversion.

31
The bit set bis and bit clear bic instructions are used with masks to set and clear bits. The bis
operation is very similar to inclusive-OR and bic mask is likewise related to and ˜ mask.
Peculiarity: The bis and bic operations do not affect the status bits. Therefore bis is not quite a
substitute for the usual inclusive-OR, which would be expected to affect SR. This is not a serious
loss because the effect of an inclusive-OR operation on the status bits is largely predictable. Bit
operations are called read–modify–write operations because the CPU cannot operate on bits
individually: It must read the register into the ALU, perform the operation, and write the result
back. This can have unwanted side effects with some special registers. One example is registers
associated with interrupts, where a read may automatically clear flags. Trouble can also arise with
input/output ports in some processors but this is not a problem on the MSP430 with its separate
input and output registers.

Logic Instructions with One Operand

There is only one of these, the invert inv instruction, also known as ones complement, which
changes all bits of 0 to 1 and those of 1 to 0:
inv.w dst ; invert bits dst = dst emulated
It is emulated using xor and inherits its peculiarity C = ˜ Z. Its operand is a destination. It is not
the same as changing the sign of a number, which is the twos complement.
Byte Manipulation
These instructions do not need a suffix because the size of the operands is fixed:
swpb src ; swap upper and lower bytes (word only)
sxt src ; extend sign of lower byte (word only)
The swap bytes instruction swpb swaps the two bytes in a word; there is no corresponding swap
nibbles for the nibbles in a byte. The sign extend instruction sxt is used to convert a signed byte
into a signed word. It copies the value of bit 7, which gives the sign of the lower byte, into bits 8–
15 and gives flags C = ˜ Z. The opposite operation, truncation from a word to a byte, can be done
with mov.b. Multiplication, if present in hardware at all, is performed by a peripheral—it is not
implemented in the ALU and does not appear in the instruction set. There are routines for methods
are given in the application note Efficient Multiplication and Division Using MSP430 ).

32
Operations on Bits in Status Register
There is a set of emulated instructions to set or clear the four lowest bits in the status register, those
that can be masked using the constant generator: multiplication in software in Section 5.1 of
Application Reports (slaa024). Further

The carry bit should be set or cleared before instructions that take it as input unless it is a result
of a previous operation. This applies to adc, addc, sbc, subc, dadc, dadd (particularly easy to forget
because of the mnemonic), and the rotations rlc and rrc. The GIE flag affects only maskable
(general) interrupts; see the section “Interrupts” on page 186.

3. Shift and Rotate Instructions

Processors often offer three types of shifts and rotations as illustrated in Figure 5.4, although the
treatment of the carry bit varies. They differ in the treatment of the bits that are shifted out of and
into the register:
Logical shift inserts zeroes for both right and left shifts.
Arithmetic shift inserts zeroes for left shifts but the most significant bit, which carries the sign, is
replicated for right shifts.

33
Rotation does not introduce or lose any bits; bits that are moved out of one end of the register are
passed around to the other.
Usually the carry bit is included in rotations and it may gain the bit that is shifted out by arithmetic
or logical shifts.
The MSP430 has arithmetic shifts and rotations, all of which use the carry bit. The right-shifts are
native instructions but the left shifts are emulated, so the left- and right-shifts have different
addressing modes available:

Peculiarities: The mnemonics for the arithmetic shifts imply that they are rotations, which is
misleading. There are no logical shifts in the MSP430 but they have been added to the MSP430X.
A logical shift left is the same as an arithmetic shift left so there is no problem there. A logical
shift right can be emulated by first clearing the carry bit and making a rotation right. The rotation
operation is not available in C so assembly language may be needed if this instruction is critical.
Shifts in C are always logical for unsigned values but the nature of shifts for signed values is
undefined. They are arithmetic in EW430 to match the instruction set. Multiword shifts can be
constructed using the carry bit in much the same way as multiword arithmetic.
4 Flow of Control
Subroutines, Interrupts, and Branches
These are mainly straightforward but there is a tricky point about addresses:

Peculiarity: Both br and call can use the full range of addressing modes for a source. The most
common elementary use of call is for a subroutine that begins at a particular label. This label is
translated by the assembler to the address of the first instruction in the subroutine: direct

34
addressing. This is the value that should be loaded into the PC to call the subroutine and is
therefore like immediate data. It must consequently be given the prefix # like any other
immediate value. For example, call # Delay Tenths. This is very easy to forget. We used this in
the section “Automatic Control: Use of Subroutines” on page 99 and I will remind you of this
pitfall again. The behavior is easier to understand with br, which is emulated. The instruction br
label is translated into mov. w label, PC. This means that label is used as an absolute address so
the contents of the word whose address is label are fetched and loaded into PC. It is more likely
that we want to load the value label itself into the PC, which needs mov.w #label, PC. The call
instruction must be handled in the same way. There is no problem with the jump instructions
because they use offsets rather than full addresses and the compiler or assembler calculates these
automatically. The good side to this is that it is easy to select a branch or subroutine from a table
by using indexed, indirect, or even autoincrement addressing. The interrupt handling for Timer_
A is designed with this in mind. Be sure that subroutines end with ret and interrupt service
routines end with reti; the extra letter is crucial. The MSP430X uses calla and reta for
subroutines. The standard no-operation instruction nop is emulated to waste one cycle of the
processor. There are further suggestions in the family user’s guides for instructions to use more
cycles but their side effects may need care.
Jumps, Unconditional and Conditional
The unconditional jump instruction is less tricky:
jmp label ; unconditional jump

The target is a straightforward label: It does not have the peculiarity (or versatility) of br. The
difference between them is that:
jmp fits in a single word, including the offset, but its range is limited to about ±1KB from the
current location.
br can go anywhere in the address space and use any addressing mode but is slower and requires
an extra word of program storage.
The nomenclature varies between manufacturers; jump and branch have the opposite meaning in
Freescale processors, for instance. The symbol $ stands for the current value of the program
counter in the assembler so jmp $ is a concise way of getting an empty, infinite loop.

35
The conditional jumps are the “decision-making” instructions and test certain bits or combinations
in the status register. It is not possible to jump according to the value of any other bits in SR or
those in any other register. Typically a bit test instruction bit is used to detect the bit(s) of interest
and set up the flags in SR before a jump. Many branches have two names to reflect different usage.
For example, it is clearer to use jc if the carry bit is used explicitly—after a rotation, for instance—
but jhs is more appropriate after a comparison:

Both mnemonics jl and jlt are used. It is up to the programmer to select the correct instruction. For
example, suppose that two bytes contain 0x99 and 0x01. They are related by 0x99 > 0x01 if the
values are unsigned but 0x99 < 0x01 if they are signed, twos complement numbers because 0x99
is the representation of −0x67 Peculiarities: There are tests for the conditions < and ≥ but not for
≤ nor >. It may be possible to choose the source and destination in a comparison to avoid this
problem. Unfortunately the asymmetric addressing modes often prevent this, particularly if one
value is immediate. Two tests may then be necessary.
5 Instruction Timing
The number of MCLK cycles required for most instructions is limited by access to memory. This
is a typical feature of a RISC-like CPU with a von Neumann architecture and also applies to the
ARM7, for instance. Values for typical instructions are listed in Table 5.1 but there are several
exceptions, including instructions that change the flow of control and those where the destination
36
is PC. The general principle for Format I instructions (two operands) is as follows. Most of these
must read the instruction and two operands from memory and write the result back. The duration
is set by the modes used to address memory for the operands.
 It takes one cycle to fetch the instruction word itself. This is all if both source and
destination are in CPU registers. Values from the constant generators are effectively in
registers.
 One more cycle is needed to fetch the source if it is given indirectly as @Rn or @Rn+, in
which case the address is already in the CPU. This includes immediate data.
 Alternatively, two more cycles are needed if one of the indexed modes is used. The first is
to fetch the base address, which is added to the value in a CPU register to get the address
of the source. A second cycle is necessary to fetch the operand itself. This includes absolute
and symbolic modes.

Two more cycles are needed to fetch the destination in the same way if it is indexed.
 A final cycle is needed to write the destination back to memory if required; no allowance
is needed for a register in the CPU.
These are illustrated in Figure 5.5. It is amusing that no dedicated cycles are needed for the
computation itself. A similar principle applies to the arithmetic operations with a single operand
but most instructions with Format II change the flow of control and have individual timings. Jumps
always use two cycles, whether conditional jumps are taken or not. There is no difference in the
timing between bytes and words so it is pointless to squeeze variables into bytes in the hope of
gaining speed. Of course it is an equally bad idea to waste memory by storing large tables as words
when the elements would fit into bytes.

37
A few instructions have been speeded up in the MSP430X. These include mov, which does not
need to fetch its destination, and bit and tst, which do not produce a result that needs to be written
back. The number of cycles for these instructions with addressing modes as in mov.w

Rs,D(Rd) has been reduced from four to three. The interfaces to subroutines and interrupt service
routines have also been made faster.

38
4.7 code generation

Machine Code

Occasionally you may need to decode the binary machine code to deduce the instruction to be
executed. This is an unfulfilling activity and fortunately is rarely needed with modern debuggers.
The layout of the bits within a Format I instruction (two operands) instruction is shown in
Figure taken from the family user’s guide. These are the individual fields:
 opcode (4 bits) is the operation code. The highest 12 values are used for Format I
instructions, the remainder for jumps and Format II.
 S-Reg and D-Reg (4 bits each) specify the CPU registers associated with the source and
destination; the registers either contain the operands themselves or their contents are used
to form the addresses.
 As (2 bits) gives the mode of addressing for the source, which has four basic modes.
 Ad (1 bit) similarly gives mode of addressing for the destination, which has only two basic
modes.
 B/W (1 bit) chooses whether the operand is a byte (1) or a word (0).
Here is a trivial example of a move from register to register with the resulting machine
code:
mov.w R5 ,R6 ; 4506

The instruction can be broken into its fields of opcode = 4, S-reg = 5, Ad = 0, B/W = 0,
As = 0, D-reg = 6. What do these mean?
 The opcode of 4 represents a move.
 The bit B/W = 0 shows that the operand is a word.
 The addressing mode for the source is As = 0, which is register. The register is S-reg = 5,
which is R5 as expected.
 Similarly, the addressing mode for the destination is Ad = 0, which again means register.
The register is D-reg = 6 = R6.
Here is an addition rather than a move:
add.w R5 ,R6 ; 5506

The machine code is identical except for the opcode, which is now 5 rather than 4. The

39
specification of the operands is unchanged. This is because of the orthogonality: All instructions
use the same addressing modes. Let us move an immediate value instead of a register:

mov.w #5,R6 ; 4036 0005

Now there are two words. The fields of the instruction are opcode = 4, S-reg = 0, Ad = 0, B/W =
0, As = 3 = 11b, D-reg = 6. The difference is in the specification of the source, which means
autoincrement. The register is Sreg = 0, which is the PC. Autoincrement addressing on the PC is
the way in which immediate values are implemented. The value itself is contained in the second
word.
Next look at a value of 4 instead, which can be supplied by the constant generator. I use a byte
rather than a word for a change:

mov.b #4,R6 ; 4266

This breaks into opcode = 4, S-reg = 2, Ad = 0, B/W = 1, As = 2 = 10b, D-reg = 6. The B/W bit
flags a byte rather than a word.
The source appears to have indirect register mode on R2/SR/CG1, but this is translated by the
constant generator into a value of 0x0004, as required. Only a single word is needed for the
instruction. Next, let us return to the first three active lines which were reviewed in the section
“Machine Code”

These are a bit more complicated because the source is given as an absolute address rather than a
register. The first instruction breaks into opcode = 4, S-reg = 0, Ad = 1, B/W = 0, As = 3 = 11b,
D-reg = 2. The source has autoincrement addressing on PC, which means an immediate value. The
destination has Ad = 1, which means indexed. The register is Dreg = 0010b = R2/SR/CG1, which
means absolute addressing (the register acts like a base value of 0). The instruction is

followed by words for the immediate value and absolute address. The third line is very similar but
the B/W bit is set to indicate a byte rather than a word. The second line looks rather different
40
 because the constant generator is used to provide the value of 4, as described earlier.

4.8 Components of the C2xx DSP core

MSP430 Microcontroller Family

MSP430F2618
F: Indicates a memory type or specialized application. "F" indicating flash memory is by far the
most popular. Other options for memory type include "C" for masked ROM, "FR" for FRAM, "G"
for Flash Value Line, and "L" as in the MSP430L09x series, which indicates a RAM-only part; it
must remain continuously powered to retain its programming.
2: The generation of device
6: The model within the generation.
18: One or two digits indicating the amount of memory on the device.

The MSP430 is a 16-bit microcontroller that has a number of special features not commonly
available with other microcontrollers:
 Complete system on-a-chip — includes LCD control, ADC, I/O ports, ROM, RAM, basic
timer, watchdog timer, UART, etc.
 Extremely low power consumption — only 4.2 nW per instruction, typical
 High speed — 300 ns per instruction @ 3.3 MHz clock, in register and register
addressing mode
 RISC structure — 27 core instructions
 Orthogonal architecture (any instruction with any addressing mode)
 Seven addressing modes for the source operand
 Four addressing modes for the destination operand
 Constant generator for the most often used constants (–1, 0, 1, 2, 4, 8)

 Only one external crystal required — a frequency locked loop (FLL) oscillator derives all
internal clocks
 Full real-time capability — stable, nominal system clock frequency is available
afteronly six clocks when the MSP430 is restored from low-power mode (LPM) 3; — no
waiting for the main crystal to begin oscillation and stabilize
41
The 27 core instructions combined with these special features make it easy to program the MSP430
in assembler or in C, and provide exceptional flexibility and functionality. For example, even with
a relatively low instruction count of 27, the MSP430 is capable of emulating almost the complete
instruction set of the legendary DEC PDP-11.
MSP430 Family
The MSP430 family currently consists of three subfamilies:
□ MSP430C31x
□ MSP430C32x
□ MSP430C33x

All three are described in detail in the MSP430 Family Architecture User’s Guide and Module
Library. The hardware features of the different devices are shown in Tables and in figures.

42
1 MSP430C31x

43
2 MSP430C32x

44
3 MSP430C33x

45
 MSP430 Application Operating Modes
MSP430 applications fall into two main classes, depending on the power supply:

 AC power-driven applications such as electricity meters and AC-powered controllers. In

these applications, the microcontroller needs to be active at all times. The low current
consumption of the MSP430 when active (900 A @ 5 V & fC = 1 MHz) puts it well
within the typical low-power category now (currently < 40 mA) and in the future as
tolerable current consumption diminishes.
 Battery-powered applications such as gas meters, water flow meters, heat volume counters,
data loggers, and other controller and remote metering tasks. For these applications, power
consumption is the key issue since operation from a single battery for 10 years or longer is
often required. The average current drawn by the MSP430 needs to
be in the range of the self discharge current of the battery, approximately 1 A to 3 A.
MSP430 has six operating modes, each with different power requirements. Three of these
modes are important for battery-powered applications:
 Active mode — CPU and other device functions run all the time
 Low power mode 3 (LPM3) — the normal mode for most applications during 99% to
99.9% of the time. This mode is also called done mode or sleep mode
 Low power mode 4 (LPM4) — the mode typically used during storage. This mode is also
called off mode
1 Active Mode
Active mode is used for calculations, decision-making, I/O functions, and other activities that
require the capabilities of an operating CPU. All of the peripheral functions may be used, provided
that they are enabled. The examples shown in this document use the active mode.

2 Low Power Mode 3 (LPM3)

LPM3 is the most important mode for battery-powered applications. The CPU is disabled, but
enabled peripherals stay active. The basic timer provides a precise time base. When enabled,
interrupts restore the CPU, switch on MCLK, and start normal operation. Table 1–2 lists the status
of the MSP430 system when in LPM3.

46
3 Low Power Mode 4 (LPM4)
Low power mode 4 (LPM4) is used if the absolute lowest supply current is necessary or if no
timing is needed or desired (no change of the RAM content is allowed). This is normally the case
for storage preceding or following the calibration process. Table 3 lists the status of the MSP430
system when in LPM4

47
Once the MSP430 is waked from LPM4, the software has to decide if it is necessary to either enter
LPM4 again (if the wake-up was caused by EMI, for example), or to enter one of the other
operating modes. To ensure the correct decision is made, a code can be placed on a port that can
be checked by the MSP430 software. Then, the active mode is entered only if this code is present.
The start-up frequency of the DCO is approximately 500 kHz and may last up to 4 seconds until a
stable MCLK frequency is reached. To enter the LPM4 the following code is necessary:

The exit from LPM4 is principally the same as described for LPM3. Interrupt handler software has
to determine if the CPU stays active or if a return to a low power mode is necessary. When entering
the LPM4 the information in control registers SCFI0 and SCFI1 of the system clock frequency
integrator (SCFI) remains stored. If at this time the ambient temperature is high, SCFI1 contains
a relatively high value to compensate the negative temperature coefficient of the DCO. If the LPM4
is later exited and the ambient temperature is very low, it is possible that the resulting DCO
frequency, based on the value in SCFI1, will be outside of the oscillator range. It is therefore a
good programming practice to set the SCFI control register to a low value before entering LPM4.

48
TI's new MSP430F5xx generation allows for more scalability than ever for MSP430
microcontrollers. The F5xx generation provides a broad range of performance, memory, price,
connectivity, and peripheral options to suite your applications.

49
MSP430 generations:

There are six general generations of MSP430 processors. In order of development, they were the
'3xx generation, the '1xx generation, the '4xx generation, the '2xx generation, the '5xx generation,
and the '6xx generation. The digit after the generation identifies the model (generally higher model
numbers are larger and more capable), the third digit identifies the amount of memory on board,
and the fourth, if present, identifies a minor model variant. The most common variation is a
different on-chip analog-to-digital converter.

The 3xx and 1xx generations were limited to a 16-bit address space. In the later generations this
was expanded to include '430X' instructions that allow a 20-bit address space. As happened with
other processor architectures (e.g. the processor of the PDP-11), extending the addressing range
beyond the 16-bit word size introducedsome peculiarities and inefficiencies for programs larger
than 64 kBytes.

In the following list, it helps to think of the typical 200 mA·Hr capacity of a CR2032 lithium coin
cell as 200,000 μA·Hr, or 22.8 μA·year. Thus, considering only the CPU draw, such a battery
could supply a 0.7 μA current draw for 32 years. (In reality, battery self-discharge would reduce
this number.)

The significance of the 'RAM retention' vs the 'real-time clock mode' is that in real time clock
mode the CPU can go to sleep with a clock running which will wake it up at a specific future time.
In RAM retention mode, some external signal is required to wake it, e.g. I/O pin signal or SPI slave
receive interrupt.
MSP430x1xx series

The MSP430x1xx Series is the basic generation without an embedded LCD controller. They are
generally smaller than the '3xx generation. These flash- or ROM-based ultra-low-power MCUs
offer 8 MIPS, 1.8–3.6 V operation, up to 60 KB flash, and a wide range of analog and digital
peripherals.

 Power specification overview, as low as:

 0.1 μA RAM retention
 0.7 μA real-time clock mode
 200 μA / MIPS active
 Features fast wake-up from standby mode in less than 6 µs.
50
  Device parameters
 Flash options: 1–60 KB
 ROM options: 1–16 KB
 RAM options: 128 B–10 KB
 GPIO options: 14, 22, 48 pins
 ADC options: Slope, 10 & 12-bit SAR

 Other integrated peripherals: 12-bit DAC, up to 2 16-bit timers, watchdog

timer, brown-outreset, SVS, USART module (UART, SPI), DMA, 16×16
multiplier, Comparator_A, temperature sensor
MSP430F2xx series:

The MSP430F2xx Series are similar to the '1xx generation, but operate at even lower
power, support up to 16 MHz operation, and have a more accurate (±2%) on-chip clock
that makes it easier to operate without an external crystal. These flash-based ultra-low
power devices offer 1.8–3.6 V operation. Includes the very-low power oscillator (VLO),
internal pull-up/pull-down resistors, and low-pin count options.

 Power specification overview, as low as:

 0.1 μA RAM retention
 0.3 μA standby mode (VLO)
 0.7 μA real-time clock mode
 220 μA / MIPS active
 Feature ultra-fast wake-up from standby mode in less than 1 μs

 Device parameters
 Flash options: 1–120 KB
 RAM options: 128 B – 8 KB
 GPIO options: 10, 11, 16, 24, 32, and 48 pins
 ADC options: Slope, 10 & 12-bit SAR, 16 & 24-bit Sigma Delta
 Other integrated peripherals: operational amplifiers, 12-bit DAC, up to 2 16-bit
timers, watchdog timer, brown-out reset, SVS, USI module (I²C, SPI), USCI
module, DMA, 16×16multiplier, Comparator_A+, temperature sensor
MSP430G2xx series[

The MSP430G2xx Value Series features flash-based Ultra-Low Power MCUs up to 16 MIPS
51
with 1.8–3.6 V operation. Includes the Very-Low power Oscillator (VLO), internal pull-up/pull-
down resistors, and low-pin count options, at lower prices than the MSP430F2xx series.

 Ultra-Low Power, as low as (@2.2 V):

 0.1 μA RAM retention
 0.4 μA Standby mode (VLO)
 0.7 μA real-time clock mode
 220 μA / MIPS active
 Ultra-Fast Wake-Up From Standby Mode in <1 μs

 Device parameters
 Flash options: 0.5–56 KB
 RAM options: 128 B–4 KB
 GPIO options: 10, 16, 24, 32 pins
 ADC options: Slope, 10-bit SAR
 Other integrated peripherals: Capacitive Touch I/O, up to 3 16-bit timers,
watchdog timer,brown-out reset, USI module (I²C, SPI), USCI module,
Comparator_A+, Temp sensor
MSP430x3xx series

The MSP430x3xx Series is the oldest generation, designed for portable instrumentation with an
embedded LCD controller. This also includes a frequency-locked loop oscillator that can
automatically synchronize to a low-speed (32 kHz) crystal. This generation does not support
EEPROM memory, only mask ROM and UV- eraseable and one-time programmable EPROM.
Later generations provide only flash memory and mask ROM options. These devices offer 2.5–
5.5 V operation, up to 32 KB ROM.

 Power specification overview, as low as:

 0.1 μA RAM retention
 0.9 μA real-time clock mode
 160 μA / MIPS active
 Features fast wake-up from standby mode in less than 6 µs.

 Device parameters:
 ROM options: 2–32 KB
 RAM options: 512 B–1 KB
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  GPIO options: 14, 40 pins
 ADC options: Slope, 14-bit SAR
 Other integrated peripherals: LCD controller, multiplier

MSP430x4xx series[

The MSP430x4xx Series are similar to the '3xx generation, but include an integrated LCD
controller, and are larger and more capable. These flash or ROM based devices offers 8–16 MIPS
at 1.8–3.6 V operation, with FLL, and SVS. Ideal for low power metering and medical applications.

 Power specification overview, as low as:

 0.1 μA RAM retention
 0.7 μA real-time clock mode
 200 μA / MIPS active

 Features fast wake-up from standby mode in less than 6 µs.

 Device parameters:
 Flash/ROM options: 4 – 120 KB
 RAM options: 256 B – 8 KB
 GPIO options: 14, 32, 48, 56, 68, 72, 80 pins
 ADC options: Slope, 10 & 12-bit SAR, 16-bit Sigma Delta
 Other integrated peripherals: SCAN_IF, ESP430, 12-bit DAC, Op Amps, RTC,
up to 2 16-bittimers, watchdog timer, basic timer, brown-out reset, SVS, USART
module (UART, SPI), USCI module, LCD Controller, DMA, 16×16 & 32x32
multiplier, Comparator_A, temperature sensor, 8 MIPS CPU Speed
MSP430x5xx series

The MSP430x5xx Series are able to run up to 25 MHz, have up to 512 KB flash memory and up
to 66 KB RAM. This flash-based family features low active power consumption with up to 25
MIPS at 1.8–3.6 V operation (165 uA/MIPS). Includes an innovative power management module
for optimal power consumption and integrated USB.[3]

 Power specification overview, as low as:

 0.1 μA RAM retention

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  2.5 μA real-time clock mode
 165 μA / MIPS active
 Features fast wake-up from standby mode in less than 5 µs.

 Device parameters:
 Flash options: up to 512 KB
 RAM options: up to 66 KB
 ADC options: 10 & 12-bit SAR
 GPIO options: 29, 31, 47, 48, 63, 67, 74, 87 pins
 Other integrated peripherals: High resolution PWM, 5 V I/O's, USB, backup
battery switch,up to 4 16-bit timers, watchdog timer, Real-Time Clock, brown-
out reset, SVS, USCI module, DMA, 32x32 multiplier, Comp B, temperature
sensor
MSP430x6xx series

The MSP430x6xx Series are able to run up to 25 MHz, have up to 512 KB flash memory and up
to 66 KB RAM. This flash-based family features low active power consumption with up to 25
MIPS at 1.8–3.6 V operation (165 uA/MIPS). Includes an innovative power management module
for optimal power consumption and integrated USB.

 Power specification overview, as low as:

 0.1 μA RAM retention
 2.5 μA real-time clock mode
 165 μA / MIPS active
 Features fast wake-up from standby mode in less than 5 µs.

 Device parameters:
 Flash options: up to 512 KB
 RAM options: up to 66 KB
 ADC options: 12-bit SAR
 GPIO options: 74 pins
 Other integrated peripherals: USB, LCD, DAC, Comparator_B, DMA, 32x32
multiplier, power management module (BOR, SVS, SVM, LDO), watchdog
timer, RTC, Temp sensor

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RF SoC (CC430) series

The RF SoC (CC430) Series provides tight integration between the microcontroller core,
peripherals, software, and RF transceiver. Features <1 GHz RF transceiver, with 1.8 V–3.6 V
operation.

 Power specification overview, as low as:

 1 μA RAM retention
 1.7 μA real-time clock mode
 180 μA / MIPS active

 Device parameters:
 Speed options: up to 20 MHz
 Flash options: up to 32 KB
 RAM options: up to 4 KB
 ADC options: 12-bit SAR
 GPIO options: 30 & 44 pins
 Other integrated peripherals: LCD Controller, up to 2 16-bit timers, watchdog
timer,RTC, power management module (BOR, SVS, SVM, LDO), USCI
module, DMA, 32x32 multiplier, Comp B, temperature sensor
FRAM series

The FRAM Series from Texas Instruments provides unified memory with dynamic partitioning
and memory access speeds 100 times faster than flash. FRAM is also capable of zero power state
retention in all power modes, which means that writes are guaranteed, even in the event of a power
loss. With a write endurance of over 100 trillion cycles, EEPROM is no longer required. Active
powerconsumption at less than 100μA/MHz.

 Power specification overview, as low as:

 320 nA RAM retention
 0.35 μA real-time clock mode
 82 μA / MIPS active

 Device parameters:
 Speed options: 8 to 24 MHz
 FRAM options: 4 to 128 KB
 RAM options: 0.5 to 2 KB
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  ADC options: 10 or 12-bit SAR
 GPIO options: 17 to 83 GPIO pins

 Other possible integrated peripherals: MPU, up to 6 16-bit timers, watchdog

timer, RTC, power management module (BOR, SVS, SVM, LDO), USCI
module, DMA, multiplier, Comp B, temperature sensor, LCD driver, I2C and
UART BSL, ExtendedScan Interface, AES, IR modulation
Low voltage series

The Low Voltage Series include the MSP430C09x and MSP430L092 parts. These 2 series of low
voltage 16 bit microcontrollers have configurations with two 16-bit timers, an 8-bit analog- to-
digital (A/D) converter, an 8-bit digital-to-analog (D/A) converter, and up to 11 I/O pins. For more
information, see Low Voltage Wiki.

 Power specification overview, as low as:

 1 μA RAM retention
 1.7 μA real-time clock mode
 180 μA / MIPS active

 Device parameters:
 Speed options: 4 MHz
 ROM options: 1–2 kB
 SRAM options: 2 kB
 ADC options: 8-bit SAR
 GPIO options: 11 pins
 Other integrated peripherals: up to 2 16-bit timers, watchdog timer, brown-out
reset,SVS, comparator, temperature sensor

Other MSP430 families

Additional families within MSP430 include Fixed Function, Automotive, and Extended
Temp parts.Fixed Function: The MSP430BQ1010 16-bit microcontroller is an advanced fixed-
function device that forms the control and communications unit on the receiver side for wireless
power transfer in portable applications. MSP430BQ1010 complies with the Wireless Power
Consortium (WPC) specification. For more information, see Contactless Power.

Automotive: Automotive MSP430 microcontrollers (MCUs) from Texas Instruments (TI) are 16-
bit, RISC-based, mixed-signal processors that are AEC-Q100 qualified and suitable for
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automotive applications in environments up to 105 °C ambient temperature. LIN compliant drivers
for theMSP430 MCU provided by IHR GmbH.

Extended Temp: MSP430 devices are very popular in harsh environments such as industrial
sensing for their low power consumption and innovative analog integration. Some harsh
environment applications include transportation/automotive, renewable energy,
military/space/avionics, mineral exploration, industrial, and safety & security.

 Device Definitions:
 HT: -55 °C to 150 °C
 EP: Enhanced products -55 °C to 125 °C
 Q1: Automotive Q100 qualified -40 °C to 105 °C
 T: Extended temperature -40 °C to 105 °C applications

Note that when the flash size is over 64K words (128 KBytes), instruction addresses can no longer
be encoded in just two bytes. This change in pointer size causes some incompatibilities
withprevious parts.

Addressing modes
The MSP430 supports seven addressing modes for the source operand and four addressing modes
for the destination operand (see Table 4-5). The following sections describe each of the addressing
modes, with a brief description, an example and the number of CPU clock cycles required for an
instruction, depending on the instruction format and the addressing modes used.

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 1. Register Mode
Register mode operations work directly on the processor registers, R4 through R15, or on special
function registers, such as the program counter or status register. They are very efficient in terms
of both instruction speed and code space.
Description: Register contents are operands.
Source mode bits: As = 00 (source register defined in the opcode).

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Destination mode bit: Ad=0 (destination register defined in the opcode).
Syntax: Rn. Length: One or two words.
Comment: Valid for source and destination.
Example 1: Move (copy) the contents of source (register R4) to destination (register R5).
Register R4 is not affected.
Before operation: R4=A002h R5=F50Ah PC = PCpos
Operation: MOV R4, R5
After operation: R4=A002h R5=A002h PC = PCpos + 2
The first operand is in register mode and depending on the second operand mode, the cycles
required to complete an instruction will differ. Table 4-7 shows the cycles required to complete an
instruction, depending on the second operand mode.

2. Indexed mode
The Indexed mode commands are formatted as X(Rn), where X is a constant and Rn is one of the
CPU registers. The absolute memory location X+Rn is addressed. Indexed mode addressing is
useful for applications such as lookup tables.
Description: (Rn + X) points to the operand. X is stored in the next word.
Source mode bits: As = 01 (memory location is defined by the word immediately following the
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 opcode).
Destination mode bit: Ad=1 (memory location is defined by the word immediately following the
opcode).

Syntax: X(Rn).
Length: Two or three words.
Comment: Valid for source and destination.
Example 2: Move (copy) the contents at source address (F000h + R5) to destination (register
R4).
Before operation: R4=A002h R5=050Ah Loc:0xF50A=0123h
Operation: MOV F000h(R5), R4
After operation: R4=0123h R5=050Ah Loc:0xF50A=0123h

3. Symbolic mode
Symbolic mode allows the assignment of labels to fixed memory locations, so that those
locations can be addressed. This is useful for the development of embedded programs.
Description: (PC + X) points to the operand. X is stored in the next word. Indexed mode X(PC)
is used.
Source mode bits: As = 01 (memory location is defined by the word immediately following the
opcode).
Destination mode bit: Ad=1 (memory location is defined by the word immediately following the
opcode).

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 Syntax: ADDR.
Length: Two or three words.
Comment: Valid for source and destination.
Example 3: Move the content of source address XPT (x pointer) to the destination address YPT
(y pointer).

Before operation: XPT=A002h Location YPT=050Ah

Operation: MOV XPT, YPT
After operation: XPT= A002h Location YPT=A002h

4. Absolute mode
Similar to Symbolic mode, with the difference that the label is preceded by “&”.
Description: The word following the instruction contains the absolute address. X is stored in the
next word. Indexed mode X(SR) is used.
Source mode bits: As = 01 (memory location is defined by the word immediately following the
opcode).
Destination mode bit: Ad=1 (memory location is defined by the word immediately following the
opcode).
Syntax: &ADDR.
Length: Two or three words.
Comment: Valid for source and destination.
Example 4: Move the content of source address XPT to the destination address YPT.
Before operation: Location XPT=A002h Location YPT=050Ah
Operation: MOV &XPT, &YPT

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 After operation: Location XPT= A002h Location YPT=A002h

5. Indirect register mode

The data word addressed is located in the memory location pointed to by Rn. Indirect mode is
not valid for destination operands, but can be emulated with the indexed mode format 0(Rn).
Description: Rn is used as a pointer to the operand.
Source mode bits: As = 10.
Syntax: @Rn.
Length: One or two words.
Comment: Valid only for source operand. The substitute for destination operand is 0(Rn).
Example 5: Move the contents of the source address (contents of R4) to the destination (register
R5). Register R4 is not modified.
Before operation: R4=A002h R5=050Ah Loc:0xA002=0123h
Operation: MOV @(R4), R5
After operation: R4= A002h R5=0123h Loc:0xA002=0123h

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6. Indirect auto increment mode
Similar to indirect register mode, but with indirect auto increment mode, the operand is
incremented as part of the instruction. The format for operands is @Rn+. This is useful for working
on blocks of data.
Description: Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for byte
instructions and by 2 for word instructions.
Source mode bits: As = 11.
Syntax: @Rn+.
Length: One or two words.
Comment: Valid only for source operand. The substitute for destination operand is 0(Rn) plus
second instruction INCD Rn.
Example 6: Move the contents of the source address (contents of R4) to the destination (register
R5), then increment the value in register R4 to point to the next word.
Before operation: R4=A002h R5=050Ah Loc:0xA002=0123h
Operation: MOV @R4+, R5
After operation: R4= A004h R5=0123h Loc:0xA002=0123h

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7. Immediate mode
Immediate mode is used to assign constant values to registers or memory locations.
Description: The word following the instruction contains the immediate constant N. Indirect
autoincrement mode @PC+ is used.

Source mode bits: As = 11.

Syntax: #N.
Length: Two or three words. It is one word less if a constant in CG1 or CG2 can be used.
Comment: Valid only for source operand.
Example 7: Move the immediate constant E2h to the destination (register R5).
Before operation: R4=A002h R5=050Ah
Operation: MOV #E2h, R5
After operation: R4= A002h R5=00E2h

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MSP Programs

Programming Levels

• Machine language – Description of instructions in terms of 0’s and 1’s. This is the model for
the actual contents in program memory – Normally presented in Hex Notation.

• Assembly language – Machine language in human-readable form. Allows better control of

program

• High level language – Preferred by most programmers because of its English like syntaxis and
notation.

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66
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 Two marks questions and answers

1. What is an embedded system?

An embedded system is a microprocessor or micro controller based system of S/W and H/W
designed to perform functions.

2. What is VON NEWMAN architecture?

data and code lie in the same memory block, then the architecture is referred as Von
Neumann architecture

3. What is MSP430 Microcontroller?

TMS320 DSP architectural has low-cost, low-power, and high-performance processing capabilities.

Several advanced peripherals, optimized for digital motor and motion control applications,

have been integrated to provide a true single-chip DSP controller. It offers increased

processing performance and a higher level of peripheral integration.

4. What is ASIC?

An ASIC, or application-specific integrated circuit, is a microchip designed for a special application,

such as a kind of transmission protocol or a hand-held computer.

5. What is the use of USB debugging interface ?

USB debugging interface connects a flash-based MSP430 MCU to a PC for real- time,
in-system programming and debugging
6. How many ADC and DACSs are in MSP 430 Controller?

MSP 430 Controller has 10/12/16-bit Analogue-to-Digital Converter (ADC);

12-bit dual Digital-to-Analogue Converter (DAC).
7. What is brownout protection ?
Brownout is an intentional or unintentional drop in voltage in an electrical power supply system.
Intentional brownouts are used for load reduction in an emergency.
8. What is BOOT Memory?
The MSP430 flash devices contain an address space for boot memory, located between
addresses 0C00h through to 0FFFh. The “bootstrap loader” is located in this memory space,
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 which is an external interface that can be used to program the flash memory in addition to the
JTAG. This memory region is not accessible by other applications, so it cannot be overwritten
accidentally. The bootstrap loader performs some of the same functions as the JTAG interface
(excepting the security fuse programming), using the TI data structure protocol for UART
communication at a fixed data rate of 9600 baud.

9. What are the general purpose registers in MSP 430 Controller?

R4 - R15 are the General–Purpose Registers in MSP 430 Controller.
These general-purpose registers are used to store data values, address pointers, or index values
and can be accessed with byte or word instructions

10. What are the memory location for special function registers?
Interrupt enables
(locations 0000h and 0001h)
Interrupt flags
(locations 0002h and 0003h);
Enable flags (locations 0004h and 0005h).

11. Write about program counter in a MSP 430 Controller.

The 16-bit Program Counter (PC/R0) points to the next instruction to be read from memory and executed
by the CPU.

12. What are the blocks in MSP 430 Controller?

On the left is the CPU and its supporting hardware, including the clock generator. The emulation,JTAG
interface and Spy-Bi-Wire are used to communicate with a desktop computer whendownloading a
program and for debugging.
The main blocks are linked by the memory address bus (MAB) and memory data bus (MDB).
These devices have flash memory, 1KB in the F2003 or 2KB in the F2013, and 128 bytes of
RAM.
Six blocks are shown for peripheral functions (there are many more in larger devices).
All MSP430s include input/output ports, Timer A and a watchdog timer, although the details
differ.
The universal serial interface (USI) and sigma–delta analog-to-digital converter (SD16_A) are
particular features of this device.
The brownout protection comes into action if the supply voltage drops to a dangerous level.
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Most devices include this but not some of the MSP430x1xx family.

10 mark Questions
(a). Explain briefly about characteristics of Embedded system. (b). Write various applications of
Embedded System?
2. Explain Embedded System Architecture.
3. (a). Compare Port I/O & Memory Mapped I/O. (b). Explain CISC vs RISC design philosophy.
4. (a). Compare Harvard vs Von-Neumann memory architectures. (b). What are the features of MSP430
microcontrollers?
5. Explain the architecture of MSP430 microcontroller.
6. Describe the Instruction set of MSP430 microcontroller.
7. Explain the instruction formats of MSP430 microcontroller.
8. Explain the MSP430 microcontroller addressing modes.
9. Compare MSP430 family viz.MSP430x2x,4x, and 5x series devices?
10. Briefly explain any sample embedded system based on MSP430 microcontroller.
11. Explain the CPU of MSP430 microcontroller.
12. a) Explain in detail about the interrupts of MSP430 microcontroller.
b) Write a program to demonstrate interrupt processing in MSP430 microcontroller.

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