S V ENGINEERING COLLEGE

KARAKAMBADI ROAD, TIRUPATI-517507

DEPARTMENT OF ELECTRICAL AND ELECTRONICS
ENGINEERING

LECTURE NOTES

20A02602T DIGITAL COMPUTING PLATFORMS

Regulation R20
Academic Year
(2023 – 24)
Year/semester:
III/II

Prepared by
K.V.L.KEERTHI,
Assistant professor
Department of ECE

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 UNIT V: FPGA Introduction to Field Programmable Gate Arrays – CPLD Vs FPGA – Types
of FPGA – Xilinx, XC3000 series - Configurable logic Blocks (CLB) – Input / Output Block
(IOB) – Programmable Interconnect Point (PIP) – Xilinx 4000 series – HDL programming –
overview of Spartan 3E and Virtex II pro FPGA boards- case study. Learning Outcomes:-
After completion of this unit student will

 To know about FPGA as one of the digital compute platforms

 To know about various types of FPGA

 To know about programmable inter connect points

 To understand about Xilinx-HDL programming

 To know about applications of FPGA

with a case studyCourse Outcomes:

1. Understand the basic architecture & pin diagram of 8086 microprocessor.

2. Assembly language programming to perform a given task, Interrupt service

routines for allinterrupt types

3. Microprocessor and Microcontroller designing for various applications.

4. Write Assembly Language Programs for the Digital Signal Processors and use
Interrupts for real-time control applications
Write Xilinx programming and understanding of Spartan FPGA board

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 CONTENTS
V 2
UNIT-V: FPGA
Introduction 2
Unit-V notes 2
Solved Problems
Part A Questions (2 marks) 35
Part B Questions (10 marks) 37

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 UNIT V
FPGA
5.1 Introduction to Field Programmable Gate Arrays – CPLD Vs FPGA – Types of FPGA –
Xilinx, XC3000 series - Configurable logic Blocks (CLB) – Input / Output Block (IOB) –
Programmable Interconnect Point (PIP) – Xilinx 4000 series – HDL programming –overview of
Spartan 3E and Virtex II pro FPGA boards- case study

Introduction to Field Programmable Gate Arrays

Field Programmable Gate Arrays (FPGAs) are digital ICs (Integrated Circuits) that enable the
hardware design engineer to program a customized Digital Logic as per his/her requirements.
The term “Field Programmable” implies that the Digital Logic of the IC is not fixed during its
manufacturing (or fabrication) but rather it is programmed by the end-user (designer).

In order to provide this programmability, an FPGA consists of Configurable (or Programmable)

Logic Blocks and configurable interconnects between these blocks. This configurable Logic and
the Interconnections (Routing) of FPGAs makes them general purpose and flexible but at the
same time, it also makes them slow and power hungry when compared to a similar calibre ASIC
with Standard Cells.

It has been more than three decades since the introduction of FPGAs into the market and in this
long span, they have undergone a severe technological advancement and gained a continuously
growing popularity.

PLD (Programmable Logic Device)

Before diving into the main topic, I want to briefly discuss the concept of Programmable Logic
Devices. So, what is a PLD. It is an IC containing a large number of Logic gates and Flip-flops
that can be configured by the user to implement a wide variety of functions.

The simplest of Programmable Logic Devices consists of an array of AND & OR gates and the
logic of these gates and their interconnections can be configured by a programming process.

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PLDs are particularly useful when an engineer wants to implement a customized logic and is
restricted by the pre-configured integrated circuits. PLDs provide a way to implement a custom
digital circuit through the power of hardware configuration rather than implementing it using a
software.

Different Types of PLDs

Basically, PLDs can be categorized into three types. They are:

 Simple Programmable Logic Devices (SPLD)

 Complex Programmable Logic Devices (CPLD)
 Field Programmable Gate Arrays (FPGA)
The Simple Programmable Logic Devices are further divided into:

 Programmable Logic Array (PLA)

 Programmable Array Logic (PAL)
 Generic Array Logic (GAL)
Let us now see some basic details about all these PLDs.

Programmable Logic Array (PLA)

A PLA consists of an AND gate plane with programmable interconnects and an OR gate plane

with programmable interconnects. The following is a simple four input – four output PLA with

AND & OR gates.

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Any input can be connected to any AND gate by connecting the horizontal and vertical

interconnect lines. The outputs from different AND gates can then be applied to any of the OR

gates with programmable interconnects.

Programmable Array Logic (PAL)

A PAL is similar to the PLA but the difference is that in PAL, only the AND gate plane is
programmable while the OR gate plane is fixed during fabrication. Even though PALs are less
flexible than PLAs, they eliminate the time delays associated with programmable OR Gates.

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Generic Array Logic (GAL)
Architecture wise, a GAL is similar to a PAL but the difference lies in programmable structure.
PALs use PROM, which is one-time programmable, while GAL uses EEPROM, which can be
reprogrammed.
5.2 CPLD Vs FPGA

Complex Programmable Logic Devices (CPLD)

Moving up from SPLD devices, we get CPLD. It is developed on top of SPLD devices to create
mush larger and complex designs. A CPLD consists of a number logic blocks (or functional
blocks), which internally consists of either a Pal or a PAL along with a Macrocell.

Macrocell consists of any additional circuitry and signal polarity control to provide true signal or
its complement

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Field Programmable Gate Arrays (FPGA)
Complexity wise, CPLD are much more complex than SPLDs. But FPGA are even more complex
than CPLDs. The architecture of an FPGA is completely different as it consists of programmable
Logic Cells, programmable interconnects and programmable IO blocks.
Field Programmable Gate Arrays or FPGAs in short are pre-fabricated Silicon devices that consists
of a matrix of reconfigurable logic circuitry and programmable interconnects arranged ina two-
dimensional array. The programmable Logic Cells can be configured to perform any digital
function and the programmable interconnects (or switches) provide the connections among
different logic cells.

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Using an FPGA, you can implement any custom design by specifying the logic or function of
each logic block and setting the connection of each programmable switch. Since this process of
designing a custom circuit is done in the field rather than in a fab, the device is known as “Field
Programmable”.

The following image shows a typical internal structure of an FPGA in a very broad sense.

As you can see, the core of the FPGA is made up of configurable logic cells and programmable
interconnections. These are surrounded by a number of programmable IO blocks, which are used
to talk to the external world.

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Components of an FPGA

Let us now take a closer look at the structure of an FPGA. Typically, an FPGA consists of
three basic components. They are:

 Programmable Logic Cells (or Logic Blocks) – responsible for implementing the core
logic functions.
 Programmable Routing – responsible for connecting the Logic Blocks.
 IO Blocks – which are connected to the Logic Blocks through the routing and help to
make external connections

Logic Block
The Logic Block in Xilinx based FPGAs are called as Configurable Logic Blocks or CLB while
the similar structures in Altera based FPGAs are called Logic Array Blocks or LAB. Let us use
the term CLB for this discussion. A CLB is the basic component of an FPGA, which provides
both the logic and storage functionalities. The basic logic block can be anything like a transistor,

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a NAND gate, Multiplexors, Look-up Table (LUT), a PAL like structure or even a processor.
Both Xilinx and Altera use Look-up Table (LUT) based logic blocks to implement the logic as
well as the storage functionalities.

A Logic Block can be made up of a single Basic Logic Element or a set of interconnected Basic
Logic Elements, where a Basic Logic Element is a combination of a Look-up table (which is in
turn made up of SRAM and Multiplexors) and a Flip-flop

A LUT with ‘n’ inputs consists of 2n configuration bits, which are implemented by SRAM Cells.
Using these 2n SRAM Bits, the LUT can be configured to implement any logical function.

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Routing
If the computational functionality is provided by the Logic Blocks, then the programmable
routing network is responsible for interconnection these logic blocks. The Routing Network
provides interconnections between one logic block to other as well as between the logic block
and the IO Block to completely implement a custom circuit.

Basically, the routing network consists of connecting wires with programmable switches, which
can be configured using any of the programming technologies. There are basically two types of
routing architectures. They are:

 Island Style Routing (also known as Mesh Routing)

 Hierarchical Routing
In island style routing architecture, the logic blocks are arranged in a two-dimensional array and
are interconnected using a programmable routing network. This type of routing is widely used in
commercial FPGAs.

Many logic blocks are confined to a local set of connections and hierarchical routing architecture
makes use of this feature by dividing the logic blocks into several groups or clusters. If the logic
blocks are residing in the same cluster, then the hierarchical routing connects them in a low level
of hierarchy.

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5.3 Types of FPGA

FPGA Programming Technologies

We have talked about the reprogrammable architecture of FPGAs quite a bit but now let us see
some of the most commonly used programming techniques that is responsible for such
reconfigurable architecture.

The following are three of the well-known programming technologies used in FPGAs.

 SRAM
 EEPROM / Flash
 Anti-Fuse

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Other technologies include EPROM and Fusible Link but they are used in CPLDs and other
PLDs but not in FPGAs, Hence, let us keep the discussion limited to FPGA related programming
technologies.

SRAM
We know that there are two types of semiconductor RAM called the SRAM and DRAM. SRAM
is short for Static RAM while DRAM is short for Dynamic Ram. SRAM is designed using
transistors and the term static means that the value loaded on a basic SRAM Memory Cell will
remain the same until deliberately changed or when the power is removed.

A typical 6 transistor SRAM Cell to store 1 bit is shown in the following image.

This is in contrast to the DRAM, which consists of a combination of a transistor and a capacitor.
The term Dynamic refers to the fact that the value loaded in the basic DRAM Memory Cell is

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valid until there is charge in the capacitor. As capacitor loses its charge over time, the memory
cell has to be periodically recharged to maintain the charge. This is also known as refreshing.

Many FPGA vendors implement Static Memory Cells in SRAM based FPGAs for programming.
SRAM based FPGAs are used to program both the logic cells and the interconnects and they
have become quite predominant due to their re-programmability and use of CMOS technology,
which is known for its low dynamic power consumption, high speed and tighter integration.

EEPROM / Flash
A close alternative to SRAM based programming technology is based on EEPROM or Flash
programming technologies. The main advantage of flash-based programming is its non-volatile
nature. Even though flash supports re-programmability, the number of times this can be done is
very small when compared to an SRAM technology.

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Anti-Fuse
The anti-fuse programming technology is an old technique of producing one-time programmable
devices. They are implemented using a link called the antifuse, which in its unprogrammed state
has a very high resistance and can be considered an open circuit.

When programming, a high voltage and current is supplied to the input. As a result, the antifuse,
which is initially in the form of amorphous silicon (basically an insulator with very high
resistance) linking two metal tracks, comes to life by converting to a conducting polysilicon.

When compared to the other two technologies, the antifuse one occupies the least amount of
space but comes only as one-time programmable option.

5.4 Xilinx
Xilinx is the inventor of the FPGA, programmable SoCs, and now, the
ACAP. Xilinx delivers the most dynamic processing technology in the industry.

Xilinx, Inc. (/ˈzɪlɪŋks/ ZEE-links) was an American technology and semiconductor company
that primarily supplied programmable logic devices. The company was known for
inventing the first commercially viable field-programmable gate array (FPGA) and
creating the first fabless manufacturing model,

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Xilinx was co-founded by Ross Freeman, Bernard Vonderschmitt, and James V Barnett II
in 1984 and the company went public on the NASDAQ in 1989. AMD announced its
acquisition of Xilinx in October 2020 and the deal was completed on February 14, 2022
through an all-stock transaction worth an estimated $50 billion.

Before 2010, Xilinx offered two main FPGA families: the high-performance Virtex series
and the high-volume Spartan series, with a cheaper EasyPath option for ramping to
volume production. The company also provides two CPLD lines: the CoolRunner and the
9500 series. Each model series has been released in multiple generations since its launch.
With the introduction of its 28 nm FPGAs in June 2010, Xilinx replaced the high-volume
Spartan family with the Kintex family and the low-cost Artix family.

5.5 XC3000 series

Features

Complete line of four related Field Programmable Gate Array product families - XC3000A,
XC3000L, XC3100A, XC3100L

• Ideal for a wide range of custom VLSI design tasks - Replaces TTL, MSI, and other PLD logic
- Integrates complete sub-systems into a single package - Avoids the NRE, time delay, and risk
of conventional masked gate arrays

• High-performance CMOS static memory technology - Guaranteed toggle rates of 70 to 370

MHz, logic delays from 7 to 1.5 ns - System clock speeds over 85 MHz - Low quiescent and
active power consumption

• Flexible FPGA architecture - Compatible arrays ranging from 1,000 to 7,500 gate complexity -
Extensive register, combinatorial, and I/O capabilities - High fan-out signal distribution, low-
skew clock nets - Internal 3-state bus capabilities - TTL or CMOS input thresholds - On-chip
crystal oscillator amplifier

• Unlimited reprogrammability - Easy design iteration - In-system logic changes

• Extensive packaging options - Over 20 different packages - Plastic and ceramic surface-mount
and pin-gridarray packages - Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options

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• Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-
tested devices - Excellent reliability record

Complete Development System - Schematic capture, automatic place and route - Logic and
timing simulation - Interactive design editor for design optimization - Timing calculator -
Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others

5.6 Configurable logic Blocks

A configurable logic block (CLB) is the basic repeating logic resource on an FPGA. When
linked together by routing resources, the components in CLBs execute complex logic functions,
implement memory functions, and synchronize code on the FPGA.

CLBs contain smaller components, including flip-flops, look-up tables (LUTs), and multiplexers.

 Flip-Flop—A circuit capable of two stable states that represents a single bit. A flip-flop
is the smallest storage resource on the FPGA. Each flip-flop in a CLB is a binary register
used to save logic states between clock cycles on an FPGA circuit.

 Look-up Table (LUT)—A collection of gates hardwired on the FPGA. An LUT stores a
predefined list of outputs for every combination of inputs. LUTs provide a fast way to
retrieve the output of a logic operation because possible results are stored and then
referenced rather than calculated. The LUTs in a CLB can also implement FIFOs and
memory items in LabVIEW.

 Multiplexer—A circuit that selects between two or more inputs and then returns the
selected input.

When you compile code to run on an FPGA target, LabVIEW implements much of the code
using flip-flops, LUTs, and multiplexers.

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Figure Configurable logic Blocks

5.7 Input / Output Block (IOB)

The input/output block (IOB) is used for communication between the problem program and the
system. It provides the addresses of other control blocks, and maintains information about the
channel program, such as the type of chaining and the progress of I/O operations. You must
define the IOB and specify its address as the only parameter of the EXCP or EXCPVR macro
instruction.

The input/output block (IOB) is not automatically constructed by a macro instruction; it must be
defined as a series of constants and be on a word boundary. For unit-record and tape devices, the
IOB is 32 bytes long. For direct access, teleprocessing, and graphic devices, 8 additional bytes
must be provided. Use the system mapping macro IEZIOB, which expands into a DSECT, to
help in constructing an IOB. IEZIOB fields that are not described here are not part of the
programming interface.

In Figure 1 the shaded areas indicate fields in which you must specify information. The other
fields are used by the system and must be defined as all zeros. You cannot place information into
these fields, but you can examine them.

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You do not have to set the following IOB fields to any particular value before issuing EXCP
because the system itself sets them:

 IOBSENS0
 IOBSENS1
 IOBECBCC
 IOBCSW
 IOBSIOCC
 IOBCMD31

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. Figure Input/Output Block (IOB) Format

IOBFLAG1 (1 byte)
Set bit positions 0, 1, 6, and 7. One-bits in positions 0 and 1 (IOBDATCH and
IOBCMDCH) indicate data chaining and command chaining, respectively. (If you

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 specify both data chaining and command chaining, the system does not use error recovery
routines except for the direct access and tape devices.) If an I/O error occurs while your
channel program executes, a failure to set the chaining bits in the IOB that correspond to
those in the CCW might make successful error recovery impossible. The integrity of your
data could be compromised.

A one-bit in position 6 (IOBUNREL) indicates that the channel program is not a related
request; that is, the channel program is not related to any other channel program. See bits
2 and 3 of IOBFLAG2 below.

If you intend to issue an EXCP or XDAP macro with a BSAM, QSAM, or BPAM DCB,
you should turn on bit 7 (IOBSPSVC) to prevent access-method appendages from
processing the I/O request.

IOBFLAG2 (1 byte)
If you set bit 6 in the IOBFLAG1 field to zero, bits 2 and 3 (IOBRRT3 and IOBRRT2)
in this field must then be set to one of the following:

 00, if any channel program or appendage associated with a related request might
modify this IOB or channel program.
 01, if the conditions requiring a 00 setting do not apply, but the CHE or ABE
appendage might retry this channel program if it completes normally or with the
unit-exception or wrong-length-record bits on in the CSW.
 10 in all other cases.

The combinations of bits 2 and 3 represent related requests,known as type 1 (00), type 2
(01), and type 3 (10). The type you use determines how much the system can overlap the
processing of related requests. Type 3 allows the greatest overlap, normally making it
possible to quickly reuse a device after a channel-end interruption. (Related requests that
were executed on a pre-MVS system are executed as type-1 requests if not modified.)

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IOBSENS0 and IOBSENS1 (2 bytes)
are set by the system when a unit check occurs. These are the first two sense bytes.
Occasionally, the system is unable to obtain any sense bytes because of unit checks when
sense commands are issued. In this case, the system simulates sense bytes by moving
X'10FE' to IOBSENS0 and IOBSENS1.
The first six of these 16 bits have these device-independent meanings:

1.............. Command reject

.1............. Intervention required
..1............ Bus out check
...1........... Equipment check
.... 1. ....... Data check
.... .1.. Overrun

The last ten of these 16 bits have device-dependent meanings. See appropriate hardware
documentation.

If you wish to retrieve more than two sense bytes, supply an IOBE and IEDB

OBECBCC (1 byte)
The first byte of the completion code for the channel program. The system places this
code in the high-order byte of the event control block when the channel program is
posted complete.
OBECBPT (3 bytes)
The address of the 4-byte event control block (ECB) you have provided.
IOBFLAG3 (1 byte) and IOBCSW (7 bytes)
The system stores status information in these eight bytes
IOBSIOCC (1 byte)
If the channel program uses format 0 CCWs, bits 2 and 3 contain the start subchannel
(SSCH) condition code for the instruction the system issues to start the channel
program.

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 If this is a format 1 CCW channel program or is a zHPF channel program, then field
IOBSIOCC is redefined as field IOBSTART, which contains the four byte starting
address of the channel program to be executed

IOBSTRTB (3 bytes)
If the channel program uses format 0 CCWs, the three byte starting address of the
channel program to be executed.
IOBFLAG4 (1 byte)
Set bit 3 (IOBCEF) to indicate whether you are supplying an IOB common extension
(IOBE). If this bit is 1, then register 0 contains the IOBE address
IOBDCBPT (3 bytes)
The address of the DCB of the data set to be read or written by the channel program.
Reserved (1 byte)
Used by the system.
IOBRESTR+1 (3 bytes)
If a related channel program is permanently in error, this field is used to chain together
IOBs that represent dependent channel programs.
IOBINCAM (2 bytes)
For magnetic tape, the amount by which the system increments the block count
(DCBBLKCT) field in the device-dependent portion of the DCB. You can alter these
bytes at any time. For forward operations, these bytes should contain a binary positive
integer (usually +1); for backward operations, they should contain a binary negative
integer.
IOBERRCT (2 bytes)
Used by the system.
IOBSEEK (first byte, M)
For direct access devices, the extent entry in the data extent block that is associated
with the channel program (0 indicates the first entry; 1 indicates the second, and so
forth).
IOBSEEK (last 7 bytes, BBCCHHR)
For direct access devices, the seek address for your channel program.

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5.8 Programmable Interconnect Point (PIP)
Programmable Interconnect Points (PIPs)
• Also known as Configurable Interconnect Points (CIPs)
Transmission gate connects to 2 wire segments–Controlled by configuration memory bit
•0 = wires disconnected
•1 = wires connected

PIPs
Break-point PIP–Connect or isolate 2 wire segments

• Cross-point PIP–Turn corners•Multiplexer PIP–Directional and buffered–Select 1-of-Ninputs for

output
• Decoded MUX PIP –Nconfig bits select from 2Ninputs•Non-decoded MUX PIP – 1 config bit
per input
• Compound cross-point PIP–Collection of 6 break-point PIPs
• Can route to two isolated signal nets.

5.9 Xilinx 4000 series

The XC4000E family of high-performance, high-density Field Programmable Gate Arrays
(FPGAs) provides the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay,
and inherent risk of a conventional masked gate array. The XC4000E family combines
architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes,
increased speed, abundant routing resources, and new, sophisticated software to achieve fully
automated imple-mentation. The FPGAs are customized by loading configuration data into the
internal memory cells. The FPGA can either actively read its configuration data out of external
serial or byte-parallel PROM (master mode), or the configuration data can be written into the
FPGA (slave and peripheral mode). The XC4000E family can run at synchronous system clock
rates of up to 70 MHz and internal performance in excess of 150 MHz.

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Features

Third Generation Field-Programmable Gate Arrays

Select-RAM TM memory: on-chip ultra-fast RAM with - synchronous write option -
dual-port RAM option
Fully PCI compliant
Abundant flip-flops
Flexible function generators
Dedicated high-speed carry-propagation circuit
Wide edge decoders (four per edge)
Hierarchy of interconnect lines
Internal 3-state bus capability
8 global low-skew clock or signal distribution network
Flexible Array Architecture
Programmable logic blocks and I/O blocks
Programmable interconnects and wide decoders
Sub-micron CMOS Process
High-speed logic and Interconnect
Low power consumption
Systems-Oriented Features
IEEE 1149.1-compatible boundary scan logic support
Programmable output slew rate (2 modes)
Programmable input pull-up or pull-down resistors
12-mA sink current per output
24-mA sink current per output pair
Configured by Loading Binary File
Unlimited reprogrammability
Six programming modes
Readback capability

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Backward Compatible with XC4000 Family
XACTstep Development System runs on ‘386/’486/ Pentium-type PC, Sun-4, and Hewlett-
Packard 700 series
Interfaces to popular design environments including VIEWlogic, Mentor Graphics and
OrCAD
Fully automatic partitioning, placement and routing
Interactive design editor for design optimization
Unified Libraries, including 288 soft macros and 34 Relationally Placed Macros (RPMs)
RAM/ROM compiler

The XC4000E family is supported by powerful and sophisticated software, covering every aspect
of design from schematic or behavioral entry, floor planning, simulation, automatic block
placement and routing of interconnects, to the creation, downloading, and read back of the
configura-tion bit stream.

The Xilinx XC4000E family includes three major configurable elements: configurable logic
blocks (CLBs), input/output blocks, and interconnects.

The CLBs provide the functional elements for constructing user's logic. The IOBs provide the
interface between the package pins and internal signal lines.

The programmable interconnect resources provide routing paths to connect the inputs and
outputs of the CLBs and IOBs onto the appropriate networks.

Customized configuration is established by programming internal static memory cells that

determine the logic functions and internal connections implemented in the FPGA.

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 Specifications
Device XC4013E
Aproximate Gate Count 13,000
CLB Matrix 24 x 24
Number of CLBs 567
Number of Flip-Flops 1,536
Max. Decode Inputs per Side 72
Max. RAM Bits 18,432
Number of IOBs 192
Horizontal Longlines 48
TBUFs per Longlines 26
PROM Size (bits) 247,96

XC4000E Series SRAM FPGA Overview

The XC4000E family of high-performance, high-density Field Programmable Gate Arrays

(FPGAs) provides the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay,
and inherent risk of a conventional masked gate array. The XC4000E family combines
architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes,
increased speed, abundant routing resources, and new, sophisticated software to achieve fully
automated imple-mentation. The FPGAs are customized by loading configuration data into the
internal memory cells. The FPGA can either actively read its configuration data out of external
serial or byte-parallel PROM (master mode), or the configuration data can be written into the
FPGA (slave and peripheral mode). The XC4000E family can run at synchronous system clock
rates of up to 70 MHz and internal performance in excess of 150 MHz.

Features

Third Generation Field-Programmable Gate Arrays

Select-RAM TM memory: on-chip ultra-fast RAM with - synchronous write option -
dual-port RAM option
Fully PCI compliant

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 Abundant flip-flops
Flexible function generators
Dedicated high-speed carry-propagation circuit
Wide edge decoders (four per edge)
Hierarchy of interconnect lines
Internal 3-state bus capability
8 global low-skew clock or signal distribution network
Flexible Array Architecture
Programmable logic blocks and I/O blocks
Programmable interconnects and wide decoders
Sub-micron CMOS Process
High-speed logic and Interconnect
Low power consumption
Systems-Oriented Features
IEEE 1149.1-compatible boundary scan logic support
Programmable output slew rate (2 modes)
Programmable input pull-up or pull-down resistors
12-mA sink current per output
24- mA sink current per output pair

Configured by Loading Binary File

Unlimited reprogrammability
Six programming modes
Readback capability

Backward Compatible with XC4000 Family

XACTstep Development System runs on ‘386/’486/ Pentium-type PC, Sun-4, and Hewlett-
Packard 700 series
Interfaces to popular design environments including VIEWlogic, Mentor Graphics and
OrCAD
Fully automatic partitioning, placement and routing
Interactive design editor for design optimization
Unified Libraries, including 288 soft macros and 34 Relationally Placed Macros (RPMs)
RAM/ROM compiler

The XC4000E family is supported by powerful and sophisticated software, covering every aspect
of design from schematic or behavioral entry, floorplanning, simulation, automatic block
placement and routing of interconnects, to the creation, downloading, and readback of the

29
configura-tion bit stream. The Xilinx XC4000E family includes three major configurable
elements: configurable logic blocks (CLBs), input/output blocks, and interconnects. The CLBs
provide the functional elements for constructing user's logic. The IOBs provide the interface
between the package pins and internal signal lines. The programmable interconnect resources
provide routing paths to connect the inputs and outputs of the CLBs and IOBs onto the appropriate
networks. Customized configuration is established by programming internal static memory cells
that determine the logic functions and internal connections implemented in the FPGA.

Specifications
Device XC4013E
Aproximate Gate Count 13,000
CLB Matrix 24 x 24
Number of CLBs 567
Number of Flip-Flops 1,536
Max. Decode Inputs per Side 72
Max. RAM Bits 18,432
Number of IOBs 192
Horizontal Longlines 48
TBUFs per Longlines 26
PROM Size (bits) 247,960

Configurable Logic Blocks (CLB)

The principle CLB elements are shown in Figure . Each CLB contains a pair of flip-flops and two
independent 4-input function generators. These function generators have a good deal of flexabilty
as most combinatorial logic functions need less than four inputs. Thirteen CLB inputs and four
CLB outputs provide access to the functional flip-flops. Configurable Logic Blocks implement
most of the logic in an FPGA. The principal CLB elements are shown in Figure 1. Two 4-input
function generators (F and G) offer unre-stricted versatility. Most combinatorial logic functions
need four or fewer inputs. However, a third function generator (H) is provided. The H function
generator has three inputs. One or both of these inputs can be the outputs of F and G; the other
input(s) are from outside the CLB. The CLB can therefore implement certain functions of up to
nine variables, like parity check or expandable-identity comparison of two setsof four inputs.

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Figure Block Diagram of XC4000 Families Configuration Logic Block (CLB)

Each CLB contains two flip-flops that can be used to store the function generator outputs.
However, the flip-flops and function generators can also be used independently. DIN can be used
as a direct input to either of the two flip-flops. H1 can drive the other flip-flop through the H
function gen-erator. Function generator outputs can also be accessed from outside the CLB, using
two outputs independent of the flip-flop outputs. This versatility increases logic density and
simplifies routing. Thirteen CLB inputs and four CLB outputs provide access to the function
generators and flip-flops. These inputs and outputs connect to the programmable interconnect
resources outside the block.

5. 10 HDL LANGUAGE
Advances in semiconductor technology continue to increase the power and complexity of digital
systems. To design such systems requires a strong knowledge of Application Specific Integrated
Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs), as well as the CAD tools
required. Hardware Description Language (HDL) is an essential CAD tool that offers designers

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an efficient way for implementing and synthesizing the design on a chip. HDL Programming
Fundamentals: VHDL and Verilog teaches students the essentials of HDL and the functionality
of the digital components of a system. Unlike other texts, this book covers both IEEE standardized
HDL languages: VHDL and Verilog. Both of these languages are widely used in industry and
academia and have similar logic, but are different in style and syntax. By learning both languages
students will be able to adapt to either one, or implement mixed language environments, which are
gaining momentum as they combine the best features of the two languages in the same project.
The text starts with the basic concepts of HDL, and covers the key topics such as data flow
modeling, behavioral modeling, gate-level modeling, and advanced programming. Several
comprehensive projects are included to show HDL in practical application, including examples
of digital logic design, computer architecture, modern bioengineering, and simulation.

5.11 overview of Spartan 3E

The XA Spartan®-3E FPGA is the world’s lowest cost logic optimized full feature platform of
five devices with system gates ranging from 100K to 1.6M gates, and I/Os ranging from 66 to 376
I/Os, with density migration.

XA Spartan-3E FPGA Family Benefits

Industry’s lowest total cost

 Large selection of device/package options

 Industry’s most comprehensive IP library

 Leading embedded and DSP solutions

 Efficient, cost-effective board designs

 Allows use of fewer components

 Increased system reliability by eliminating external components

Industry's first robust anti-cloning security for low cost FPGAs

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Multiple Domain-Optimized Platforms Spartan-3 Generation

The Spartan®-3 Generation of FPGAs offers a choice of five platforms, each delivering a unique
cost-optimized balance of programmable logic, connectivity, and dedicated hard IP for your low-
cost applications.

 Spartan-3A DSP– DSP Optimized

o For applications where integrated DSP MACs and expanded memory are required

o Ideal for designs requiring low cost FPGAs for signal processing applications
such as military radio, surveillance cameras, medical imaging, etc.

 Spartan-3AN – Non-volatile

o For applications where non-volatile, system integration, security, large user flash
are required

o Ideal for space-critical or secure applications as well as low cost embedded

controllers

 Spartan-3A – I/O Optimized

o For applications where I/O count and capabilities matter more than logic density

o Ideal for bridging, differential signaling and memory interfacing applications,

requiring wide or multiple interfaces and modest processing

 Spartan-3E – Logic Optimized

o For applications where logic densities matter more than I/O count

o Ideal for logic integration, DSP co-processing and embedded control, requiring
significant processing and narrow or few interfaces

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  Spartan-3 – For Highest Density and Pin-Count Applications

o For applications where both high logic density and high I/O count are important

o Ideal for highly-integrated data-processing applications

5.12 Virtex II pro FPGA boards- case study

Target Evolvable Hardware

The target EHW is implemented as an OPB slave peripheral module – see Fig. 2. Interfacing
with the OPB bus has been simplified by the use of a Xilinx IP Interface core (IPIF). This
provides a simpler interface standard, the Xilinx IPIC, for the user module.Control and
configuration of this module are undertaken through register write operations. Genome values
are written to registers which are again connected to the configuration inputs of the functional
unit array. Registers are also

Figure The architecture of target EHW system

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Functional unit array

The functional unit array (FUA) is a general structure used for EHW. It is based on the principle
that the configuration of the FPGA itself is not changed, but a virtual circuit which is implemented
on top of it can be reconfigured. Hence the names ”Virtual FPGA” or ”Virtual Reconfigurable
Circuit

Our FUA consists of a fixed-size array of functional units. The array consists of C columns of R
units from input to output. Each unit has I inputs, each of which can be connected to any output
in the previous column. The unit’s output is a result of any of F functions. The function of each
unit and its inputs are configurable. They are determined by evolution, in the way that each
individual’s binary genome is sent to the FUA and mapped to the configuration lines. Fitness is
then calculated by feeding a number of input vectors on the inputs of the first column, and reading
the results from the outputs of the last column. The array is constructed in a pipelined fashion, that
is, registers are connected to the outputs of each layer. Currently, this is not exploited for fitness
evaluation. Only one input vector is evaluated at a time.

Figure The architecture of the Functional unit array subsystem.

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Table Functions used by units in the image recognition task. Inputs are A and B, ouput is O. C1
and C2 are constants available to each unit.

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 2 mark questions and answers.
1. What is FPGA?

Field Programmable Gate Arrays (FPGAs) are digital Integrated Circuit that enable the
hardware design engineer to program a customized Digital Logic as per requirements.

2. What is CPLD?

CPLD is an integrated circuit that helps to implement digital systems whereas FPGA is an
integrated circuit designed to be configured by a customer or a designer after manufacturing.

3. What are the Types of Programmable Logic Devices?

Programmable Logic Array (PLA)

Programmable Array Logic (PAL)
Generic Array Logic (GAL)

4. What is CLB ?
A configurable logic block (CLB) is the basic repeating logic resource on an FPGA.
When linked together by routing resources, the components in CLBs execute complex logic
functions, implement memory functions, and synchronize code on the FPGA.
5. What is PIP in FPGA?
Transmission Gates connects to two wire segments.
0- Wire disconnected
1- Wire connected

6. Write bout Xilinx 4000 series.

The Xilinx XC4000E family includes three major configurable elements: configurable
logic blocks (CLBs), input/output blocks, and interconnects. The CLBs provide the functional
elements for constructing user's logic. The IOBs provide the interface between the package pins
and internal signal lines.

7. What is HDL?
Digital circuits consist primarily of interconnected transistors. We design and analyze these
circuits with the aid of a hierarchical structure: we could, in theory, interpret a central
processing unit (CPU) as a vast sea of transistors, but it is much easier to organize

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 transistors into logic gates, logic gates into adders or registers or timing modules,
registers into memory banks, and so forth..

Another way to describe digital circuits is to use a textual language that is specifically intended
to clearly and concisely capture the defining features of digital design.
Such languages exist, and they are called hardware description languages (HDLs).

8. What do HDLs do?

The most popular hardware description languages are Verilog and VHDL. They are
widely used in conjunction with FPGAs, which are digital devices that are specifically
designed to facilitate the creation of customized digital circuits.

9. What is the difference between Programming Languages vs. Hardware Description

Languages?

Statements in HDL code involve parallel operation, whereas programming languages

represent sequential operation.

10. What is the use of Spartan®-3 Generation of FPGAs

The Spartan-3 Generation of FPGAs offers a choice of five platforms, each delivering a
unique cost-optimized balance of programmable logic, connectivity, and dedicated hard
IP for your low-cost applications.

11. What are the HDL languages?

1. VHLD, 2 Verilog

12. What is the difference between VHLD and Verilog?

. Both of these languages are widely used in industry and academia and have similar
logic, but are different in style and syntax.

13. What is minimum and maximum frequency of dcm in spartan-3 series fpga?

Spartan series dcm’s have a minimum frequency of 24 MHZ and a maximum of 248.

14. What are different types of FPGA programming modes?

The modes are Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary
Scan.

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10 mark questions
1. Write about some of features of FPGA which are are currently used.

2. List out some of synthesizable and non synthesizable constructs

3. Draw and explain general structure of fpga.

4. Write about FPGA design flow

5. Draw a rough diagram of how clock is routed through out FPGA?

6. a),What are dcm's? why they are used?

b) what is slice, clb, lut?

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