1

Laboratory Assignment 3

Note: Document all your work and include screenshots of the primary circuit diagram(s) for each experiment as well
as the output signals in you report. All screenshots must have a time stamp.

Objective: Utilize the knowledge acquired through theoretical analysis of the circuit elements in solving a real-life
problem.

Note that the square wave generator in the previous experiments has high voltage half of the time, which may not be
very efficient or desirable in many applications. High voltage generally means more heat because it will result in flow of
current when applied to a circuitry. So, our goal is to keep the time of the high pulse to the minimum needed. In clocking
application of digital circuits, for example, there is a minimum “hold time” needed for the clocking pulse to stay high for
the digital circuitry to safely change the state. Keeping the high pulse “high” beyond that time is just waste of energy.
We express the time when the pulse is “high” as a percentage of the time period of the wave form as the “duty cycle” of
the waveform.

Example: Figure 1 shows a 1 KHz waveform. A 1 KHz waveform has a time period of 1 mSec. (T=1/f). If the waveform has
a high pulse for 0.25 mSec. and has low voltage for the rest of the period (0.75 mSec.), the duty cycle of the waveform
would be

0.25 × 10−3
𝐷𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 = × 100 = 25%.
1.0 × 10−3
(1)
.

Figure 1: A 1 KHz waveform with 25% duty cycle.

Recall from assignment 2 that the reason we had square wave from the simple voltage comparator-based oscillator was
that we were using the same path for charging and discharging the capacitor (which means that the same time constant
was used in both cases). In order to control the duty cycle, we need to have separate charging and discharging paths so
that we are able to adjust the resistances of both paths independently. In this way, we can design an oscillator of any
desire frequency and the duty cycle of the waveform. Note that our conceptual model (see Figs. 2 and 3 of assignment
2) of the oscillator did have two separate paths for charging and discharging the capacitor.

Syed A. Rizvi Spring 2024 ENS 371

 2

We now explore the possibility of designing an oscillator with a little more control on switching so that we can have the
oscillator with a desired duty cycle (as opposed to being locked into a square wave of the Design 1). A suitable chip for
this purpose is 555 Timer IC chip. Figure 2 shows a functional diagram of the 555 IC chip, which comes as 8-pin dual-in-
line (DIP) package. The main building blocks of 555 Timer are a voltage divider, two comparators, an SR flipflop, an
inverter/buffer for the output, and a transistor switch to control the discharge path.

Figure 2: Functional diagram of the 555 Timer.

The key components of the Timer function are as follows:

Voltage divider: The three resistors of the voltage divider have the same value, which means that the voltage across
each resistor is 1/3 Vcc. That provides 1/3 Vcc after the bottom resistor, which is fed to the “+” input of the lower
comparator “L.” Also, the voltage divider provides 2/3 Vcc after the middle resistor, which is fed to the “-“ input of the
upper comparator “U.” This strategy prevents the externally connected capacitor from continue to charge above 2/3 Vcc
as well as discharge below 1/3 Vcc.

Voltage comparators: The purpose of two comparators is to trigger the RS flipflop when the external capacitor charges
above 2/3 Vcc or discharges below 1/3 Vcc (explained later in more detail with the help of the external circuitry). The “+”
input of the upper comparator is fed by the voltage at the external capacitor through pin # 6 (threshold). It causes the
upper comparator to change its output when the capacitor charges above 2/3 Vcc. The “-” input of the lower comparator
is also fed by the voltage at the external capacitor through pin # 2 (trigger). It causes the lower comparator to change its
output when the capacitor discharges below 1/3 Vcc. In this way, the external capacitor charges, and discharges between
the range of 1/3 Vcc to 2/3 Vcc.

RS Flipflop: The RS flip flop is fed by the outputs of the two comparators. This flipflop regulates the output of the 555
Timer in such a way that it remains at one level when the capacitor is charging and at the other level when the capacitor
Syed A. Rizvi Spring 2024 ENS 371
 3

is discharging. It also controls the opening and closing of the “discharge path,” (pin # 7). The F/F can be reset externally,
if needed, through pin # 4. The truth table of the RS F/F is shown below.

S R Q Q’

0 0 No change

0 1 0 1

1 0 1 0

1 1 Undefined

Control Voltage (pin # 5): The maximum charging voltage of the capacitor can be changed from the default value of 2/3
VCC to any desired value (must be higher than 1/3 VCC but less than VCC) externally through pin # 5.

Note that in the following analysis, we will use “1” at the output of any circuit component to represent a high voltage
and “0” at the output of any circuit component to represent a low voltage. The high voltage could be any voltage
between 5-15 volts depending upon VCC. The low voltage could be any voltage between 0-3.5 volts.

Figures 3 through 7 illustrate the operation of an oscillator that can provide waveforms of different duty cycles. Figure 3
shows the state of the circuit when it turned on. Here, we assume that the capacitor has no prior charge when the
circuit is turned on. That is, VC = 0. Following the circuit from left to right leads us to output of “1” with the discharge
path “open.” At that point the capacitor would start charging towards VCC through resistors R1 and R2 with a time
constant τ = (R1 + R2) C1.

Syed A. Rizvi Spring 2024 ENS 371

 4

Figure 3: Circuit behavior when VC = 0.

Figure 4 shows the state of the circuit when VC surpasses 1/3VCC. That changes the output of the lower comparator from
“1” to “0.” However, there is no effect of this change on the output, or the discharge path and the capacitor continue to
charge towards VCC.

Figure 4: Circuit behavior when VC > 1/3 VCC.

Syed A. Rizvi Spring 2024 ENS 371
 5

Figure 5 shows the state of the circuit when VC surpasses 2/3 VCC. Scanning the circuit from left to right, we observe that
now output of the upper comparator (U) is “1.” That causes the F/F to reset (Q’ = 1), which, in turn, switches the output
from “1” to “0” and closes the discharge path.

Figure 5: Circuit behavior when VC > 2/3 VCC.

At that moment, the current from VCC, after passing through R1, finds a path to the ground through the discharge path
thus preventing the capacitor C1 to charge any further. The capacitor C1 now starts discharging with the discharge
current passing through the resistor R2 and following the discharge path to the ground.

However, as the capacitor voltage VC decreases below 2/3 VCC, the output of the upper comparator (U) switches to “0”
(low). Figure 6 illustrates the state of the circuit under this condition. Note that this change in the output of the upper
comparator (U) does not have any impact on the outputs (Q and Q’) of the F/F. Consequently, the output of the
oscillator remains “0” (low) and the discharge path remains closed.

Syed A. Rizvi Spring 2024 ENS 371

 6

Figure 6: Circuit behavior when VC < 2/3 VCC.

The capacitor continues to discharge until the capacitor voltage VC decreases below 1/3 VCC. At that moment, the output
of the lower comparator (L) switches to “1.” Figure 7 illustrates the state of the circuit under this condition. Note that
this change in the output of the lower comparator (L) reverses the outputs (Q and Q’) of the F/F. Consequently, the
output of the oscillator switches to “1.” It also causes the discharge path to open. The capacitor now starts charging
towards VCC again.

Syed A. Rizvi Spring 2024 ENS 371

 7

Figure 7: Circuit behavior when VC < 1/3 VCC.

Figure 8 shows voltage across the capacitor C1 as well as the output voltage during this process.

Figure 8: The voltage across the capacitor C1 as well as the output voltage during this process. Top: The output voltage.
Bottom: The voltage across the capacitor C1.

Syed A. Rizvi Spring 2024 ENS 371

 8

The design equations for the circuit in Figure 9 can be obtained by solving step response and natural response equations
in terms of charging and discharging time, tC and td, respectively. The step response of an RC circuit is given by
−𝑡
𝑉𝐶 = 𝑉𝐶𝐶 (1 − 𝑒 𝜏𝑐 )
(2)

Where τc represents the time constant during the charging phase of the capacitor, given by

𝜏𝑐 = (𝑅1 + 𝑅2 )𝐶1 .
(3)

Let t1 be the time taken by the capacitor to reach a voltage of 1/3 VCC and t2 be the time taken by the capacitor to reach
a voltage of 2/3 VCC. Since the capacitor charges and discharges between 1/3 VCC to 2/3 VCC, we are interested in the
difference between these two times; that is

𝑡𝑐 = 𝑡2 − 𝑡1 .
(4)
.
The capacitor voltage at t = t1 is 1/3VCC. Therefore, from Eq. (2) we get

1 −𝑡1
𝑉 = 𝑉𝐶𝐶 (1 − 𝑒 𝜏𝑐 ).
3 𝐶𝐶 (5)

Solving Eq. (5) for t1 we get

𝑡1 = 0.4055 𝜏𝑐 .
(6)
.
The capacitor voltage at t = t2 is 2/3VCC. Therefore, from Eq. (2) we get

2 −𝑡2
𝑉𝐶𝐶 = 𝑉𝐶𝐶 (1 − 𝑒 𝜏𝑐 ). (7)
3

Solving Eq. (7) for t2 we get

Syed A. Rizvi Spring 2024 ENS 371

 9

𝑡2 = 1.0986 𝜏𝑐 .

(8)

or

𝑡𝑐 = (𝑡1 − 𝑡2 ) = (1.0986 𝜏𝑐 − 0.4055 𝜏𝑐 ) = 0.693(𝑅1 + 𝑅2 )𝐶1 .

(9)

Now we will use the natural repose of an RC circuit to develop the second design equation. the natural repose of an RC
circuit is given by
−𝑡
𝑉𝐶 = 𝑉𝐶𝐶 𝑒 𝜏𝑑
(10)
.
Where τd represent the time constant during the discharging phase of the capacitor given by

𝜏𝑑 = 𝑅2 𝐶1 .
(11)
.
Let t1 be the time taken by the capacitor to discharge to reach a voltage of 2/3 VCC and t2 be the time taken by the
capacitor to discharge to reach a voltage of 1/3 VCC. Note that we are only interested in the time the capacitor takes to
discharge from VC = 2/3 VCC to VC = 1/3 VCC, which given the difference

𝑡𝑑 = 𝑡2 − 𝑡1 .
(12)
.
The capacitor voltage at t = t1 is 2/3VCC. Therefore, from Eq. (10) we get

2 −𝑡1
𝑉 = 𝑉𝐶𝐶 𝑒 𝜏𝑑 .
3 𝐶𝐶 (13)

Solving Eq. (13) for t1 we get

𝑡1 = 0.4055 𝜏𝑑 .
(14)

Syed A. Rizvi Spring 2024 ENS 371

 10

The capacitor voltage at t = t2 is 1/3VCC. Therefore, from Eq. (10) we get

1 −𝑡2
𝑉 = 𝑉𝐶𝐶 𝑒 𝜏𝑑 .
3 𝐶𝐶 (15)

Solving Eq. (15) for t2 we get

𝑡2 = 1.0986 𝜏𝑑 .

(16)
or

𝑡𝑑 = (𝑡1 − 𝑡2 ) = (1.0986 𝜏𝑑 − 0.4055 𝜏𝑑 ) = 0.693𝑅2 𝐶1 .

(17)

The time period, T, of the output waveform is given by

𝑇 = 𝑡𝑐 + 𝑡𝑑 = 0.693(𝑅1 + 𝑅2 )𝐶1 + 0.693𝑅2 𝐶1

(18)

and the frequency, f, of the output waveform is given by

1 1
𝑓= = .
𝑇 𝑡𝑐 + 𝑡𝑑 (19)

Note that during the charging time the output is high. The duty cycle can be expressed as

𝑡𝑐
𝐷𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 = .
𝑇 (20)

where, the duty cycle is greater than 0 and less than 1. The duty cycle is expressed in percentage. For example, duty
cycle of 0.8 would be referred to as 80% and vice versa.
Syed A. Rizvi Spring 2024 ENS 371
 11

Here is the set of design equations:

𝑡𝑐 = 0.693(𝑅1 + 𝑅2 )𝐶1
(21)

𝑡𝑑 = 0.693𝑅2 𝐶1
(22)

1 1
𝑓= = .
𝑇 𝑡𝑐 + 𝑡𝑑 (23)

𝑡𝑐
𝐷𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 =
𝑇 (24)

𝑇 = 𝑡𝑐 + 𝑡𝑑
(25)

Syed A. Rizvi Spring 2024 ENS 371

 12

Experiment 1: Use the design equations (21) to (25) to compute the component values for the experiment.

Build the circuit in Fig. 9 to meet the following requirements:

A. Design a pulse generator for frequencies = 15 KHz, 10 KHz, and 5 KHz with a 70% duty cycle. Use C1 = 9.4 nF.

B. For frequency = 10 kHz, generate the waveform for the following duty cycles: 90%, 70%, 50%, 30%, and 10%.

Display the output signal. Explain if the output is what you expected.

Questions:

1. Were you able to design, build, and test all the circuits to meet the requirement of part (A)? Please explain any
discrepancies in your expected and actual results.

2. Were you able to design, build, and test all the circuits to meet the requirement of part (B)? Please explain the
issues, if any, you encountered while designing the oscillators for the duty cycles mentioned in the part (B) of
the experiment.

Figure 9: An oscillator based on 555 Timer IC to produce waveforms of different duty cycles.

Syed A. Rizvi Spring 2024 ENS 371

 13

Experiment 2: Being unable to design the oscillator to meet all the requirements of part (B) of experiment 1, you sought
help from a colleague who is heading out to attend a meeting. Your colleague takes a quick look at you design
(equations, circuit diagram etc.) and suggests the resistance in the charging path is always larger than the resistance in
the discharging path, which prevents you from meeting the some of the duty cycle requirements. He then suggests a
quick solution:

Switch the resistances in the charging and discharging paths, which would allow you to make the resistance in the
charging path less than the resistance in the discharge path (see circuit in Fig. 10). You can then build the oscillator to
meet the missing duty cycle requirements. He further suggests doing the math again to make sure everything adds up.
You decide to follow your colleague’s suggestion but do the theoretical analysis and the design implementation in
parallel.

Questions:
1. Were you able to build the oscillator to generate the waveforms with for the remaining duty cycles? Either way
explain as to why the circuit behaved the way it did.
2. Do the new/modified design equations meet the duty cycle requirements? Either way, explain why or why not.

Figure 10: A modified version of the oscillator shown in Fig. (9).

Syed A. Rizvi Spring 2024 ENS 371