Fault Memory : Provides fault memory capability to store up to 13 faults per flight leg.

The fault memory management is controlled by the CFDIU. This management incudes leg incrementation, fault type storage, and fault reporting. In the absence or failure of the CFDIU, the landing gear strut switch signal is utilized for this purpose. - BITE Built In Test Equipment. La plupart des calculateurs possdent un BITE. C'est un dispositif lectronique permettant de dtecter, localiser et mmoriser les pannes du systme correspondant. - CFDS Centralized Fault Display System. Le rle du CFDS est de faciliter les tches de maintenance en permettant, partir du MCDU l'accs aux messages de panne et l'initialisation de tests spcifiques - CFDIU Centralized Fault Display Interface Unit. Ce calculateur central dialogue avec le BITE de la plupart des systmes de l'avion et reoit les messages de panne de ces systmes.

CFDS Compatible : CPU module interfaces fault memory and BITE data between VOR/Marker receiver and line maintenance Centralized Fault Display Interface Unit (CFDIU) for the purpose of extracting maintenance information and initiating tests Designed to conform with ARINC 604, and Airbus Industrie ABD-O018 via ARINC 429 interfaces.

CPU Module : P103 , BITE and Audio Amplifier : P305,

Using a microprocessor for determining phase difference ensures that an accurate digital bearing is produced. The microprocessor also permits monitoring and comparing various signals, voltage levels, and flag warnings to determine if a malfunction has occurred. If a failure is detected in the receiver, a failure warning code (status bits 30 and 31) is generated in the bearing word. When the data is suspect but the receiver appears to be healthy, an NCD (no computed data) code is inserted in the bearing word.

The BITE self test feature is activated as a routine part of the microprocessor program. During this test, the microprocessor monitors dedicated test nodes on each module and internal computations are made during signal processing. The data obtained by monitoring is compared with limits stored in the program to determine if there has been a malfunction. If a malfunction is detected, and the self test was initiated by the front panel test button, the green VOR pass LED on the front panel of the unit will not light and the red VOR fail lamp will

be turned on, a failure warning code will be inserted in the output (on the bearing word), and the fault annunciator on the BITE module will display a hexadecimal digit on the fault annunciator, indicating which module the microprocessor has determined to be at fault. Similarly, if the input data is faulty, the red DATA IN LED will light on the front panel. If a marker receiver failure is detected, a red MARKER LED is illuminated.

The CFDS test feature interfaces the RVA-36A fault memory and built-in test equipment (BITE) with the Centralized Fault Display System (CFDS) to allow line maintenance to initiate the RVA-36A BITE and extract maintenance information pertaining to faults. The CPU module compares this data to data stored in memory to determine if a malfunction has occurred. If a failure is detected, the red MKR LED on the front panel of the unit will be turned on and the fault annunciator on the BITE module will indicate the failed module if energized.

A ROM is a device that stores data in the form of a program or "look-up tables" and is only read from. The ROM is connected to the address bus, data bus, and control bus. The address bus selects a specific location within the ROM. The control bus then issues a memory read command that gates the addressed data onto the data bus. A RAM is also a device that stores data. This data can be a program, "look-up" tables, temporary values, or external stacks. The differences between a RAM and a ROM is that data can be written into a RAM; thus the device is a read/write storage element. The microprocessor treats the RAM in exactly the same manner as the ROM for addressing data to be read. Writing data into a RAM is similar to reading data out. First the RAM is issued an address to specify the storage location. Then when data is written out of the microprocessor, a control signal to the input of the RAM strobes the data into the addressed location.

The function to be performed by the microprocessor and the sequence in which they are to be executed are determined by the instruction stored in erasable and electrically programmable read only memory (EEPROM) UIIO. Data can be read from the EEPROM but cannot be written into the EPROM. The computer program is stored in the EEPROM during manufacture and cannot be altered in the field.

The microprocessor accesses the EEPROM and other devices through a data bus and an address bus. The data and address buses provide for two-way transfer of data and/or instructions between the microprocessor and other devices. Devices on the CPU module accessed and controlled by the microprocessor include EEPROM, random access memory (RAM), option PROM (programmable read only memory), analog and digital multiplexers, ADC/DAC converters, interval and watchdog timers, and latches. The microprocessor reads and executes the program instructions stored in the EEPROM. The instruction may be to perform an arithmetic computation, logic function, data transfer, or other functions. If the instruction is to perform an arithmetic computation, the result may be stored in the microprocessor registers or written into RAM. If the microprocessor will provide the storage location, and the data will be transferred to that location on the data bus. Erasable/Electrically Programmable Read Only Memory (EEPROM) EEPROM UI03 stores the microprocessor program. The EEPROM is a 256K, 32K, 8-bit byte CMOS device with a total storage capacity of 32768 bytes. The EEPROM is programmed during manufacture and are not interchangeable or programmable in the field. Storage locations are addressed by address bits AO-AIO on the address bus. A chip select low input from the address decoder at pin 20, U]03 transfers the address data to the DO-D7 data bus lines.

Random Access Memory (RAM) RAM U116 provides temporary read/write storage for 8192 bytes of data. The RAM device is eight bits wide and has 8192 locations. The device is addressed by address bits AO-A12 from the address bus. Data present on the DO-D7 data bus is written into RAM at the selected location when a low input signal from the address decoder is applied at chip enable input pin 8 (CE--) and a low input from the microprocessor is applied at write enable pin 10 (WR--). When reading data from the RAM, write enable WR-- must be held high when chip enable CE-- goes low. Notice that operation during both read and write operations.

Fault Memory The center for the Centralized Fault Display System (CFDS) is the electrically erasable read only memory (EEROM) U121. All fault information is stored within this device. The EEROM is a 64K, 8192 byte NMOS device. Information pertaining to the last 64 flight legs is stored in

the EEPROM. A maximum of ten air and three ground faults per flight segment can be stored. All fault records and header information for the 64 flight legs recorded use a total of 5120 bytes, some of the remaining storage is used for tracking the current flight leg. Fault recording is provided by CFDS information; control commands received on the maintenance port direct the LRU as to what information to store. Should the maintenance port not be working, the air/ground discrete signal is used instead. All flight failures are recorded in one of ten slots within each flight leg of the fault memory. Ground faults are stored in three other slots within each flight leg of fault memory. Data present on the DO-D7 data bus is written into EEROM at the selected location when a low input signal from the address latch is applied to the enable input pin 20 (CE--) and a low from the microprocessor is applied to the write enable pin 27 (WE--). During a write operation an internal time and input latch frees the microprocessor to perform other functions. An automatic byte erase is performed prior to a byte write operation. At the completion of a write operation the read/busy pin signals the microprocessor that it is available for another write or read cycle. When reading data from the EEROM the write enable (WR--) must be held high while the (CE--) and (OE--) are low. Fault memory dump request is accomplished through specific test equipment. Dump commands must be sent twice to be accepted by the LRU. Upon receiving a valid dump request a series of label 351 words are issued on the main output ARINC port of the LRU. The dump begins with a Start of Text Word (STX), followed by data, and ending with an End of Transmission Word (COT). The fault memory can only be cleared in the shop with specific test equipment. Reception of CFDS command code 76H causes clearing of the fault memory to all zeros. A clear fault memory command must be issued twice for the LRU to recognize the command. An Acknowledge Fault Memory Clear (ACK) word is sent upon completion of the fault memory clear process. The fault memory consists of 64 flight legs with the current flight leg having the numeric value of one (I). The flight legs before the current flight leg are referred to as previous legs and are numbered 2 through 64. The fault memory uses a numeric fault code structure with each flight leg containing flight information header and a fault record section. The 64 flight legs are used in the direction toward the top of the fault memory. When the top of the fault memory is reached, the next fault will be read into the first location over the existing fault code.

The flight leg is incremented by the CFDS issuing a fault command code of 12H or label 227 word, this occurs during aircraft takeoff. Each flight leg consists of a 28 BYTE header followed by 10 flight fault record locations and 3 ground fault record locations. An example of one fault flight leg is illustrated in figure 12.

To accommodate all the fault records and flight header information for the 64 flight legs, a total of 5120 BYTES of the 8192 BYTE EEPROM are used. Some extra storage is used to track the current flight leg. 1 Calendar Date Information a-Label (Bits I through 8) b-SDI (Bits 9, 10) c-Year (Bits 11 through 18) d-Month (Bits 19 through 23) e-Day (Bits 24 through 29) f- S/S (Bits 30 and 31) Sign/Status Matrix g- Parity (Bit 32) 2 City Pairs a- City Pairs Information Word Label (Bits I through 8) b- City identifier 3 Flight Phase 4Flight Number (Aircraft Identification Word) _5 Fault Record Format Each fault record contains the time, flight phase, failure code, and number of occurrences, up to a total of 4. Ground faults also contain a sequence number to simplify the order of reporting when reading back during a memory dump. A fault record is illustrated in figure 24.

_a Fault Code The first BYTE (first eight bits), contain the fault code. A zero in the fault code indicates that no fault information has been recorded in the fault record. b Greenwich Mean Time BYTES 2 and 3 contain the time information and is updated by the aircraft clock. Time is stored in hours and minutes in binary coded decimal (BCD) with the hours being in BYTE 2 and minutes being in BYTE 3. Addition Information (BYTE 4) The flight phase bits 0 through 3 can change value often. Each fault record contains the current flight phase value received on the maintenance input port using the lower four bits. The error repetition bits 4 and 5 are used to count the repetitions of failures. A maximum of number of 3 can be shown, indicating at least 4 total failures occurred. The ground failure sequence bits 7 and 8 identify in order which of the three ground failure records were written. ~6 Fault Memory Dump and Clear Operations The fault memory dump and clear operations are performed during ground operation using specified test equipment. The contents is transmitted through the 429 bus to the test panel by pressing the PRT/CLR key with the EDIT key ON. The CFDS can not normally issue these codes and must be encoded with the LRU specific equipment identifier code. The fault memory and clear commands must be sent twice to be accepted by the LRU. Reception of CFDS command (label 227) causes clearing of the fault memory to all zeros, meaning that no information is stored in fault memory records.

Upon receiving a valid "DUMP MEMORY" code, a series of label 351 words are issued on the main output ARINC port of the LRU. The dump begins with a start of text (STX) word, followed by data, and ending with and end of transmission (EOT) word. In the data, the earliest flight leg is sent followed by all flight legs up to the latest in the exact BYTE sequence shown for the flight leg record.

(c) Fault Annunciator

The fault annunciator (DS301) is a single-digit hexadecimal LED display, which displays 0 through 9 or A through F. When the blanking input (pin 8) is high, the display is blanked regardless of the levels of the data inputs. This indicates a CPU module has timed out. When the blanking input is low, a character iS displayed as determined by the data that is set into internal latches in the device. The fault annunciator is not activated unless +SV is applied from the ATE connector (via P305-B20) to the BENCH TEST input at pin 14 of DS301. The AO, At, A2, and D~ lines from the CPU module, which address the LSI, also provide the data inputs to the internal latches in the annunciator (DS301). When the strobe input (pin 5 of DS301) goes low, it sets the selected internal latch. When the strobe input is high, the data in the latches will not change, regardless of the inputs. The binary weight of the data inputs to DS301 is: A=I, B=2, C=4, and D=8. The resultant displays for the values of the binary (hexadecimal) data that is set in the internal latches are: O=OH through 9=9H, IO=AH, 11=BH, 12=CH, 13=DH, 14=EH, and 15=FH. The fault annunciator codes are shown in figure 32. The display is blanked when either of the CPU time-out circuits goes high (trap inputs at P305-B3, A4). This is done to prevent erroneous data being displayed by the annunciator.

B. Fault Annunciator Functioning of the RVA-36A is constantly being monitored to assure proper operation. If a failure is detected, a failure warning code (status bits 30 and 31) is inserted in the bearing word and the fault annunciator on the BITE and audio amplifier module will display a hexadecimal digit indicating the module that the microprocessor has determined to be at fault. Figure 119 lists the modules together with their assigned number/letter code.