Principles of VLSI Design DC and AC Response CMPE 413

DC Response

DC Response: Vout vs. Vin for a gate

 Ex: Inverter
When Vin = 0 -> Vout = VDD
When Vin = 1 -> Vout = 0
In between, Vout depends on transistor size and current.

By KCL, must settle such that Idsn = | Idsp|

VDD
Could solve analytically or using simulations
but a graphical solution is easier.
Idsp
Vin Vout
From previous analysis, we know that current
depends on the region of operation. Idsn

So we need to the region of operation for all

values of Vin and Vout.

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Principles of VLSI Design DC and AC Response CMPE 413

NMOS Operation

Cutoff Linear Saturation

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn

Vdsn < Vgsn - Vtn Vdsn > Vgsn - Vtn

Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin
Idsp
Vin Vout Vdsn= Vout

Idsn Vtn > 0

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Principles of VLSI Design DC and AC Response CMPE 413

PMOS Operation

Cutoff Linear Saturation

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp

Vdsp > Vgsp - Vtp Vdsp < Vgsp - Vtp

Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD
Idsp
Vin Vout Vdsp =Vout - VDD

Idsn Vtp < 0

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Principles of VLSI Design DC and AC Response CMPE 413

I-V Characteristic

Vgsn5

Vgsn4
Idsn

Vgsn3
-Vdsp
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

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Principles of VLSI Design DC and AC Response CMPE 413

Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

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Principles of VLSI Design DC and AC Response CMPE 413

Load Line Analysis

For a given Vin, Plot Idsn, Idsp vs. Vout. (Vout values where |currents| are equal)
Vin0

Vin = 0 Idsn, |Idsp|

Vin0
VDD
Vout

Vin = 0.2 VDD Idsn, |Idsp|

Vin1

Vin1
VDD
Vout

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Principles of VLSI Design DC and AC Response CMPE 413

Load Line Analysis

Idsn, |Idsp|
Vin = 0.4 VDD
Vin2
Vin2

VDD
Vout

Vin = 0.6 VDD

Idsn, |Idsp|

Vin3
Vin3

VDD
Vout

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Principles of VLSI Design DC and AC Response CMPE 413

Load Line Analysis

Vin4
Idsn, |Idsp|
Vin = 0.8 VDD

Vin4
VDD
Vout

Vin0 Vin5

Vin = VDD
Vin1
Idsn, |Idsp|

Vin2
Vin3
Vin4
VDD
Vout

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Principles of VLSI Design DC and AC Response CMPE 413

Load Line Summary

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

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Principles of VLSI Design DC and AC Response CMPE 413

DC Transfer Curve
Vin0 Vin5

Vin1 Vin4

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1 VDD
VDD
Vout A B

Vout
C

D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

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Principles of VLSI Design DC and AC Response CMPE 413

Operating Regions and Supply Current

VDD
Region NMOS PMOS A B

A Cutoff Linear Vout

B Saturation Linear C

C Saturation Saturation
D Linear Saturation D
E
E Linear Cutoff 0 Vtn VDD/2 VDD+Vtp
VDD
Vin

A
B

C
IDD Supply current IDD vs. Vin.

D
E
Vin VDD
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Principles of VLSI Design DC and AC Response CMPE 413

Beta Ratios

 If β p ≠ β n , switching point will move from VDD/2.

 Called skewed gate
 Other gates: Collapse into equivalent
inverter VDD
 Curves shift, but the output transition
βp
in the C region still remains sharp βn
= 10

 Therefore, beta ratios don't affect Vout 2

switching performance 1
 With equal beta values the time 0.5
βp
required to charge or discharge the out- = 0.1
βn
put load capacitance is equal
 Results in equal rise and fall times 0
VDD
Vin

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Principles of VLSI Design DC and AC Response CMPE 413

Noise Margins

 A parameter that determines the maximum noise voltage on the input of a gate that
allows the output to remain stable.
 Two parameters, Low noise margin (NML) and High noise margin (NMH).
NML = difference in magnitude between the max LOW output voltage of the driving
gate and max LOW input voltage recognized by the driven gate. NMH is similar for
high voltage input and output range.
VDD
Logical high
output range VOHmin Logical high
NMH input range
VIHmin
indeterminate
region
VILmax
NML Logical low
Logical low VOLmax input range
output range
GND

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Principles of VLSI Design DC and AC Response CMPE 413

Logic Levels

To maximize noise margins, select logic levels at unity gain points of DC transfer charac-
teristics
V out NMH = VOH - VIH
NML = VIL - VOL
U n ity G a in P o in ts
V DD
S lo p e = -1
V OH

β p /β n > 1

V in V out

V OL
V in
0
V tn V IL V IH V D D - V D D
|V tp |

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Principles of VLSI Design DC and AC Response CMPE 413

Pseudo-nMOS Inverter
VDD
p-device pull-up
(load) Vout
p
Vout
2.5V Wp/Lp = 4
Vin n-device pull-down
n
(driver)
Wp/Lp = 2

When driver is on, steady-state current Wp/Lp = 1/2

flows - not a good choice for low-power 0V
2.5V Vin VDD
circuits.
Therefore, the shape of the transfer characteristic and the VOL of the inverter is affected by
βn
the ratio ------ .
βp
In general, the low noise margin is considerably worse than the high noise margin for
Pseudo-nMOS.

Pseudo-nMOS was popular for high-speed circuits, static ROMs and PLAs.

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Principles of VLSI Design DC and AC Response CMPE 413

Pseudo-nMOS

Example: Calculation of noise margins:

VDD
4.6V
VIH
VOH
p
Vout Vout
Vin
n

0.60V
Pseudo-nMOS inverter
VOL
1.2V 2.2V Vin VDD

VIL

NMH = VOH - VIH = 4.6V - 2.2V = 2.4V

NML = VIL - VOL = 1.2V - 0.60V = 0.60V (This is quite a bit worse than NMH)

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Principles of VLSI Design DC and AC Response CMPE 413

Transient Response

DC analysis tell us Vout if Vin is constant.

Transient analysis tells us Vout(t) if Vin(t) changes.

Requires solving differential equations

Input is usually considered to be a step or ramp from VDD to 0 or vice versa.

Step response of inverter driving a capacitive load

Vin(t)
Vout(t)
Cload

Idsn(t)

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Principles of VLSI Design DC and AC Response CMPE 413

Inverter Step Response

V in ( t ) = u ( t − t 0 )V DD
Vin(t)
V out ( t < t 0 ) = V
DD
dV out I dsn ( t )
---------------- = ------------------
dt C load Vout(t)
t
t0
0 t < t0
β 2
--- ( V − V ) V out > V DD − V t
I dsn ( t )= 2 DD

β ( V DD − V t − V out ( t ) ⁄ 2 )V out ( t ) V out < V DD − V t

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