0% found this document useful (0 votes)
14 views13 pages

Memory 1

The document discusses various types of memory technologies, including EEPROM and SRAM, highlighting their characteristics and functionalities. It explains how EEPROM can be erased and reprogrammed without removal, while SRAM operates synchronously with clock signals. Additionally, it covers the processes involved in accessing and writing data in these memory types.

Uploaded by

kurkutemrunmay7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
0% found this document useful (0 votes)
14 views13 pages

Memory 1

The document discusses various types of memory technologies, including EEPROM and SRAM, highlighting their characteristics and functionalities. It explains how EEPROM can be erased and reprogrammed without removal, while SRAM operates synchronously with clock signals. Additionally, it covers the processes involved in accessing and writing data in these memory types.

Uploaded by

kurkutemrunmay7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
You are on page 1/ 13
son = egpanatte pape peo Port worpetaed Blau & art pened ae by see wwieg Guerce z 20 nF xarmmatle ROM. EpRorT cau be feogeanmed K erared multiple times by “UU A gUEI aie foe eccalig al ei _Teemnspaeoucd quate ladeur gee UU excuse, FEEPROM —> Bleclatcally erasable fregranmable ROM EEPROM js like EPROM Dur it cou Le erased & Apptogrammed | | tecteically voithaut Wemovfug UF -Yeou Hix cael Tr ed loa erasuze & ag zal Li Gu Ce xewutlen flrousaud of £6 eddies fg lomo you ecud 40 read is ger upa muah ke Gfatia hefee trad ole begios (Ri stalulify erauses cotrech mumory Ol v gelecked @ GlapSet Select Ouce His addeess 4 Vatid jHa clup veleck wiguel bs actvakeal aaually Gees Faas, Gy The tells the memar undies “elevice ebouldl japend fo addeess, This coutect ciquel allows Hu ports jp deen fo place _ tHe data frou“ yelected addeets cute data Dug © Ourpur eoaule O Access Huse data atid = vy delay sic OE Lefere data eppeout ox dabey Td xeprseuts fla Haw ory foky fo betes & oyp atoved al data wand Pexiod al ers advanced foo of eepRo Luk aa ee eed gf Ons | = Gases dala 14 (loca[page milead of Blade + ; mel ta RTO G Weg lee cosk ual is ackvaled, pieaperiae Readflaiie Memon ts CRA aun uu» oe nae canies our Hea proesss | Wadi sk—=sa 5 dake, | sce woul oF eat peach a ¢. ee Preerory behaves bike | DRAM SS Bre eta gem ag aa TFetatay——— iene deals ouly fee foue milli ccdnaly 7 rat reepreuls Jecanion | Dtsch ssellia So Bil ettind decaiig a Sw Bouts Fortin MAS ES oe CPU caches CHI 1219), registess is oT RAM Tabet, f eles ule Priggen Se! fates Brea | | 2, pen vad Tyaddeas must remaic walle Vefore & after achivaling Hut wilte euaule sigual Ta dota ts dated (wollen) on oe falling edge Jogicel AND of Write enable &K Gulp elect (C8) Didixectioual data iu out pins Ly Espectatly common or wide denice. RAM desic —> diuwlas fo ROM packages x Synchronous SRAM —> E ‘Fype of SRAM that weeks with spnehsoniention with a clock siqual. ar Peajourns mead & waite opesations on clock edges addihonal fo requlae SRATT —> @ adds registees de input of = @ address Ting © Gols} igus @ data fing ourReq Enside Cpu peel hee DED te 64 KB, @ V J Saductios data fear uses one ipiee Storey aaeae! el ee SS _@ hit fines axe precharged to middle ve ® He ward line is achuated < @ 1p capacitor = 4, iF chongas the bik line voltage slightly + Deedling aboys Ha conde G copaci tor fo Afje xeading, PRAM writer tha valve Back fo epee S [arie} Activate werd line Crow) Apply Ligh (lou voltage te tte Dir Dine Life ici BLM bow 7 ake a0 Jour op word Lica fo complete urile ORAM change Tealage | ; rit ale ao E v Egy = XK Te clargcos Hu capacitor Deak angy ovee bine spat! lucl, you Poote date BRT meat Oot er a This Asha pe cll read & sod. eorumplion duc #7 a ze : See ee i = column Pakelies + é waulbipledte ke demalkiplecee | ASL | WET —e| z ai “a RAS/cas —> which call {0 read valu wuulkiplend addrasi Ie poms => spins (hist ow addees) trigger RAS: Column address biqgeed _b vaddrens you addees is latched word fine is activated — Hen column addres is latched E TRe correct bit is selected Prom yo Rcolumn & pub op bal Say * DRAM eral Hudug —> \ 70d Address CAS=L i (ms 3 Seud yoo addras —>5 RAS-1 fall fo lake it~ vend columa addeas, —> CAS L pally to lak, (Es Sek Hye Ud Bae ie hugh = fo write a 4 low —+ fo write a0 Be word Yin goer ow, diconnakd Ra coll a 7

You might also like