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Assignment 2

The assignment requires the development of a model for a Cascaded H-Bridge (CHB) converter in MATLAB/Simulink to manage 50 MVAR of reactive power for a 3-phase 11 kV ac grid. It involves implementing phase-shifted PWM, voltage balancing techniques, and a control structure with inner loop current control and outer loop voltage control. A report detailing observations, simulation results, and plots must be submitted by April 18, 2025.

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rpatnaik1998
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5 views1 page

Assignment 2

The assignment requires the development of a model for a Cascaded H-Bridge (CHB) converter in MATLAB/Simulink to manage 50 MVAR of reactive power for a 3-phase 11 kV ac grid. It involves implementing phase-shifted PWM, voltage balancing techniques, and a control structure with inner loop current control and outer loop voltage control. A report detailing observations, simulation results, and plots must be submitted by April 18, 2025.

Uploaded by

rpatnaik1998
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MULTILEVEL CONVERTERS: ANALYSIS AND CONTROL( EE60208 )

Indian Institute of Technology Kharagpur KGP, Spring-2025

Assignment-2: Simulation of MMC


Date of announcement: 4-04-2025, To be submitted: on or before 18-04-2025
Total mark: 100

1. Develop a model of CHB in MATLAB/Simulink to be used to supply/absorb 50 MVAR of reactive


power to 3-phase 50 Hz, 11 kV ac grid. Use phase-shifted pulse width modulation technique with
converter net switching frequency in the range of 6 kHz while the individual device switching
frequency should not be more than 1 kHz. Use three modules per each phase. The energy-power
ratio of the converter should be in the range of 100 – 120 ms. Show the waveforms (converter
output pole voltage, phase current, capacitor voltages of any phase) when the converter is
operated (a) to supply 25 MVAR. and (b) to absorb 25 MVAR. Initially you may start with dc
sources in each module instead of capacitor if you couldn’t balance the capacitor voltages. Later
implement the cluster voltage balancing (common mode voltage injection) and individual voltage
balancing.

The control structure of the converter should be inner loop current control and outer loop voltage
control. Inner loop current controller should be implemented in synchronously rotating d-q frame that
will produce the voltage references in d-q references. You may use direct sin and cosine functions in
sync with the grid voltage instead of implementing PLL for grid synchronization. The outer loop voltage
control generates the active component of the current that compensates the losses. The VAR demand
decides the reference of the reactive component of the current. The PI controller can be designed
with pole zero cancellation.

For outer loop voltage controller, compare the average value of all the capacitor voltages with
reference voltage and use a PI controller to generate the active current reference from the voltage
error. To design the PI controller, you can assume the controller bandwidth of 2-5 Hz and phase
margin of 60-70 degree.

A report in pdf format along with the simulated model is to be submitted through Moodle.

General instruction: for each part write down your observations and also include simulation
results/plots along with brief description mentioning mainly what to infer from these plots. Try to
avoid readymade solution as much as possible.

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