Module-3

 Hardware Software Co design and Program

Modelling: Fundamental issues in Hardware
Software Co-design, Computational models in
Embedded System Design.
 Embedded Hardware Design and Development:
Analog Electronic Components, Digital Electronic
Components, VLSI & Integrated Circuit Design,
Electronic Design Automation Tools
FUNDAMENTAL ISSUES IN HARDWARE SOFTWARE CO-
DESIGN
Selecting the model
• In hardware software co-design, models are used for
capturing and describing the system characteristics and is
a system, that consists objects and composition rules.
• Since it is hard to select model for particular system
design, often designers switch between a variety of
models from the requirements specification to the
implementation aspect of the system design.
• At the specification stage, only the functionality of the
system is in focus and but at the implementation, the
information about the system components is revealed and
the designer has to switch to a model capable of capturing
the system’s structure.
Selecting the Architecture
• A model only captures the system characteristics and does
not provide information on ‘how the system can be
manufactured?’
• The architecture specifies how a system is going to
implement in terms of the number and types of different
components and the interconnection among them.
• Controller Architecture, Datapath Architecture, Complex
Instruction Set Computing (CISC), Reduced Instruction Set
Computing (RISC), Very Long Instruction Word Computing
(VLIW), Single Instruction Multiple Data (SIMD), Multiple
Instruction Multiple Data (MIMD), etc. are the commonly
used architectures in system design.
Selecting the Architecture
• The Controller Architecture implements the finite state
machine model using a state register and two
combinational circuits where, the state register holds the
present state and the combinational circuits implement
the logic for next state and output.
• The Datapath Architecture is best suited to implement
the data flow graph model where the output is generated
due to set of predefined computations on the input data.
• Datapath represents a channel between the input and
output and it may contain registers, counters, register
files, memories and ports along with high speed
arithmetic units.
• Ports connect the datapath to multiple buses, i.e., ALU
connected in parallel with pipelining support for bringing
high performance
Selecting the Architecture
• Finite State Machine Datapath (FSMD) architecture
combines the controller architecture with datapath
architecture and implements a controller with datapath.
• The controller generates the control input using I\O port
for receiving/sending the control signals from/to the
controller unit whereas the datapath processes the data
using I/O port that interfaces the datapath with external
world for data input and data output.
• Complex Instruction Set Computing (CISC) architecture
uses an instruction set representing complex operations
to perform a large complex operation (CJNE instruction)
with a single instruction.
Selecting the Architecture
• The use of a single complex instruction in place of multiple
simple instructions greatly reduces the program memory
access and program memory size requirement.
• RISC architecture uses instruction set representing simple
operations and it requires the execution of multiple RISC
instructions to perform a complex operation.
• RISC instruction set is designed to operate on registers and
supports extensive pipelining.
• Very Long Instruction Word (VLIW) architecture
implements multiple functional units (ALUs, multipliers,
etc.) in the datapath.
• Parallel processing architecture implements multiple
concurrent Processing Elements (PEs) and each processing
element may associate a datapath containing register and
local memory.
Selecting the Architecture
• Single Instruction Multiple Data (SIMD) and Multiple
Instruction Multiple Data (MIMD) architectures are
examples for parallel processing architecture.
• In SIMD architecture, a single instruction is executed in
parallel with the help of the Processing Elements and the
scheduling of the instruction execution and controlling of
each PE is performed through a single controller.
• The processing elements of the MIMD architecture
execute different instructions at a given point of time and
MIMD forms the basis of multiprocessor systems.
• The PEs in a multiprocessor system communicates through
mechanisms like shared memory and message passing.
Selecting the language
• A programming language captures a ‘Computational
Model’ and maps it into architecture and no hard and fast
rule to choose specific language.
• A model can be captured using multiple programming
languages like C, C++, C#, Java, etc. for software
implementations and languages like VHDL, System C,
Verilog, etc. for hardware implementations.
• A single language can be used for capturing a variety of
models and some are good in capturing certain
computational model. For example, C++ is a good
candidate for capturing an object oriented model.
• The only pre-requisite in selecting a programming
language for capturing a model is that, the language
should capture the model easily.
 Partitioning System Requirements into
hardware and software
• From an implementation perspective, it may be possible
to implement the system requirements in either hardware
or software (firmware).
• It is a tough decision making task to figure out which one
to opt and there are various hardware software trade-offs
are used for making a decision on the hardware-software
partitioning.
 Computational Models in Embedded Design
• Data Flow Graph/Diagram (DFG) Model
• Control Data Flow Graph/ Diagram (CDFG)
• State Machine Model
• Sequential Program Model
• Concurrent/Communicating Process Model
• Object-Oriented Model
 Data Flow Graph/Diagram (DFG) Model
• It translates the data processing requirements into a data
flow graph and is a data driven model in which the
program execution is determined by data.
• This model emphasises on the data and operations on the
data which transforms the input data to output data and is
a visual model in which the operation on the data
(process) is represented using a block (circle) and data
flow is represented using arrows.
• An inward arrow to the process (circle) represents input
data and an outward arrow from the process (circle)
represents output data in DFG notation.
• Embedded applications which are computational intensive
and data driven are modeled using the DFG model.
 Data Flow Graph/Diagram (DFG) Model
• DSP applications are typical examples for it, for example
the computational requirement of x = a + b; and y = x – c
of a DFG model is:
• A data path is the data flow
path from input to output
• A DFG model is said to be
acyclic DFG (ADFG) if it
doesn’t contain multiple
values for the input variable
and multiple output values for a given set of input(s).
• Feedback inputs (Output is fed back to Input), events, etc.
are examples for non-acyclic inputs.
 Control Data Flow Graph/Diagram (CDFG)
• DFG model is a data driven model in which the execution
is controlled by data and it doesn’t involve any control
operations (conditionals).
• The Control DFG (CDFG) model is used for modelling
applications involving conditional program execution that
contains both data operations and control operations.
• The CDFG uses Data Flow Graph (DFG) as element and
conditional (constructs) as decision makers and it contains
both data flow nodes and decision nodes, whereas DFG
contains only data flow nodes.
 Control Data Flow Graph/Diagram (CDFG)
• If flag = 1, x = a + b; else y = a – b; which requires a
decision making process.
• The control node is represented by a ‘Diamond’ block
which is the decision making element in a normal flow
chart based design.
 Control Data Flow Graph/Diagram(CDFG)
• CDFG translates the requirement, which is modeled to a
concurrent process model and decision on which process is to
be executed is determined by the control node.
• A real world example for modelling the embedded application
using CDFG is the capturing and saving of the image to a
format set by the user in a digital still camera.
• Data driven starting from the Analog Front End which converts
the CCD sensor generated analog signal to Digital Signal.
• Storing the data from ADC to a frame buffer for the use of a
media processor which performs various operations like, auto
correction, white balance adjusting, etc.
• The decision on, in which format the image is stored (formats
like JPEG, TIFF, BMP, etc.) is controlled by the camera settings,
configured by the user.
 State Machine Model
• Is used for modelling reactive or event-driven embedded
systems whose processing behaviour are dependent on
state transitions. Embedded systems used in the control
and industrial applications are typical examples for event
driven systems.
• lt describes the system behaviour with ‘States’, ‘Events’,
‘Actions’ and ‘Transitions’ where, State is a representation
of a current situation, Event is an input to the state that
acts as stimuli for state Transition (is the movement from
one state to another) and Action is an activity to be
performed by the state machine.
• A Finite State Machine ( FSM) model is one in which the
number of states are finite that is, the system is described
using a finite number of possible states.
 State Machine Model
• As an example, let us consider the design of an embedded
system for driver/passenger ‘Seat Belt Warning’ in an
automotive using the FSM model and the system
requirements are captured as:
 When the vehicle ignition is turned on and the seat belt is
not fastened within 10 seconds of ignition ON, the system
generates an alarm signal for 5 seconds.
 The Alarm is turned off when the alarm time (5 seconds)
expires or if the driver/passenger fastens the belt or if the
ignition switch is turned off, whichever happens first.
• Here, the states are ‘Alarm Off’, ‘Waiting’ and ‘Alarm On’
and the events are ‘Ignition Key ON’, ‘Ignition Key OFF’,
‘Timer Expire’, ‘Alarm Time Expire’ and ‘Seat Belt ON’.
 State Machine Model
• FSM Model for Automatic seat belt warning system
 State Machine Model
• The ‘Ignition Key ON’ event triggers the 10 second timer
and transitions the state to ‘Waiting’. If a ‘Seat Belt ON’ or
‘Ignition Key OFF’ event occurs during the wait state, the
state transitions into ‘Alarm Off’.
• When the wait timer expires, the event ‘Timer Expire’ is
generated and it transitions the state to ‘Alarm On’ from
the ‘Waiting’ state. The ‘Alarm On’ state continues until a
‘Seat Belt ON’ or ‘Ignition Key OFF’ event or ‘Alarm Time
Expire’ event, whichever occurs first.
• The wait state is implemented using a timer where, the
timer also has certain set of states and events for state
transitions. Using the FSM model, the timer can be
modeled
 State Machine Model
FSM Model for timer

As seen from the FSM, the timer state can be either ‘IDLE’ or
‘READY’ or ‘RUNNING’
 State Machine Model
• When the timer is not running, it is said to be in the ‘IDLE’
state that is in normal condition.
• The timer is said to be in the ‘READY’ state when the timer
is loaded with the count corresponding to the required
time delay and it remains in the ‘READY’ state until a ‘Start
Timer’ event occurs.
• The timer changes its state to ‘RUNNING’ from the
‘READY’ state on receiving a ‘Start Timer’ event and
remains in the ‘RUNNING’ state until the timer count
expires or a ‘Stop Timer’ even occurs.
• The timer state changes to ‘IDLE’ from ‘RUNNING’ on
receiving a ‘Stop Timer’ or ‘Timer Expire’ event.
 State Machine Model
• Design an automatic tea/coffee vending machine based on
FSM model for the following requirement.
“The tea/coffee vending is initiated by user inserting a 5
rupee coin. After inserting the coin, the user can either
select ‘Coffee’ or ‘Tea’ or press ‘Cancel’ to cancel the order
and take back the coin”.
 State Machine Model
• It contains four states namely; ‘Wait for coin’ ‘Wait for
User Input’, ‘Dispense Tea’ and ‘Dispense Coffee’.
• The event ‘Insert Coin’ (5 rupee coin insertion), transitions
the state to ‘Wait for User Input’ and waits until it receives
‘Cancel’, ‘Tea’ or ‘Coffee’ button press.
• If the event triggered in ‘Wait State’ is ‘Cancel’ button
press, the coin is pushed out and the state transitions to
‘Wait for Coin’ else is either ‘Tea’ button press, or ‘Coffee’
button press, the state changes to ‘Dispense Tea’ and
‘Dispense Coffee’ respectively.
• After vending coffee/tea is over, the respective states
transitions back to the ‘Wait for Coin’ state.
 State Machine Model

FSM Model for Automatic Tea\Coffee Vending Machine

 State Machine Model
• Design a coin operated public telephone unit based on FSM
model for the following requirements.
1. The calling process is initiated by lifting the receiver (off-
hook) of the telephone unit
2. After lifting the phone the user needs to insert a 1 rupee coin
to make the call.
3. If the line is busy, the coin is returned on placing the receiver
back on the hook (on-hook)
4. If the line is through, the user is allowed to talk till 60 seconds
and at the end of 45th second, prompt for inserting another 1
rupee coin for continuing the call is initiated
5. If the user doesn’t insert another 1 rupee coin, the call is
terminated on completing the 60 seconds time slot.
6. The system is ready to accept new call request when the
receiver is placed back on the hook (on-hook)
7. The system goes to the ‘Out of Order’ state when there is a
line fault.
 State Machine Model
• State A: Ready
• State B: Wait for coin
• State C: Wait for number
• State D: Dialling
• State E: Call in progress
• State F: Call terminated S
• tate G: Unable to make call
• State H: Invalid number input
• State I: Out of order
 Sequential Program Model
• In this model, the functions or processing requirements
are executed in sequence and FSMs are good choice for
sequential program modelling.
• Here the program instructions are iterated and executed
conditionally and the data gets transformed through a
series of operations and tool used for modelling
sequential program is Flow Charts.
• The FSM approach represents the states, events,
transitions and actions, whereas the Flow Chart models
the execution flow.
• The execution of functions in a sequential program model
for the ‘Seat Belt Warning’ system is:
 Sequential Program Model
#define ON 1
#define OFF 0
#define YES 1
#define NO 0
void seat_belt_warn()
wait_10sec();
if (check_ignition_key()==ON)
{
if (check_seat_belt()==OFF)
{
set_timer(5);
start_alarm();
while ((check_seat_belt()==OFF )&&(check_ignition_key()==OFF )&&
(timer_expire()==NO));
stop_alarm();
}
}
}
Flow Chart
 Concurrent/Communicating Process Model
• Models concurrently executing tasks/processes and is
easier to implement certain requirements in concurrent
processing model than the conventional sequential
execution.
• Sequential execution leads to a single sequential execution
of task and thereby leads to poor processor utilisation,
when the task involves I/O waiting, sleeping for specifi ed
duration etc.
• If the task is split into multiple subtasks, it is possible to
tackle the CPU usage effectively, however concurrent
processing model requires additional overheads in task
scheduling, task synchronisation and communication.
• ‘Seat Belt Warning’ system in concurrent processing
model as:
 Concurrent/Communicating Process Model
• Let split the tasks into:
1. Timer task for waiting 10 seconds (wait timer task)
2. Task for checking the ignition key status (ignition key
status monitoring task)
3. Task for checking the seat belt status (seat belt status
monitoring task)
4. Task for starting and stopping the alarm (alarm control
task)
5. Alarm timer task for waiting 5 seconds (alarm timer task)
• Five tasks here we cannot execute them randomly or
sequentially, need to synchronise their execution through
some mechanism.
 Concurrent/Communicating Process Model
• It needs to start the alarm only after the expiration of the
10 seconds wait timer and that too only if the seat belt is
OFF and the ignition key is ON.
• Hence the alarm control task is executed only when the
wait timer is expired and if the ignition key is in the ON
state and seat belt is in the OFF state.
 Concurrent/Communicating Process Model
• Tasks for ‘Seat Belt Warning System
Concurrent processing Program model for ‘Seat
Belt Warning System’
 Object-Oriented Model
• Is an object based model for modelling system
requirements that disseminates a complex software
requirement into simple well defined pieces called
objects.
• It brings re-usability, maintainability and productivity in
system design and here, object is an entity used for
representing or modelling a particular piece of the system
and is characterised by a set of unique behaviour and
state.
• A class is an abstract description of a set of objects and it
can be considered as a ‘blueprint’ of an object, where it
represents the state of an object through member
variables and object behaviour through member
functions.
• The member variables and member functions of a class
can be private, public or protected.
 Object-Oriented Model
• Private member variables and functions are accessible
only within the class, whereas public variables and
functions are accessible within the class as well as outside
the class.
• The protected variables and functions are protected from
external access, however classes derived from a parent
class can also access the protected member functions and
variables.
• The concept of object and class brings abstraction, hiding
and protection.
Embedded Hardware Design and Development
Analog Electronic Components, Digital Electronic
Components, VLSI & Integrated Circuit Design, Electronic
Design Automation Tools
 Analog Electronic Components
• Resistors, capacitors, diodes, inductors, operational
amplifiers (Op-Amps), transistors, etc. are the commonly
used analog electronic components in embedded
hardware design.
• A resistor limits the current flowing through a circuit.
Interfacing of LEDs, buzzer, etc. with the port pins of
microcontroller through current limiting resistors is a
typical example.
• Capacitors and inductors are used in signal filtering and
resonating circuits. Reset circuit implementation,
matching circuits for RF designs, power supply decoupling,
etc. are some examples in embedded hardware circuit.
• Electrolytic capacitors, ceramic capacitors are types.
 Analog Electronic Components
• P-N Junction diode, Schottky diode, Zener diode, etc. are
the commonly used diodes in embedded hardware
circuits.
• A schottky diode is same as a P-N junction diode except
that its forward voltage drop is very low (of the order of
0.15V to 0.45) when compared to ordinary P-N junction
diode (of the order of 0.7V to 1.7V).
• Applications: voltage clamping, Reverse polarity
protection, voltage rectification etc..
• Transistors in embedded applications are used for either
switching or amplification purpose, in switching, the
transistor is in either ON or OFF state and in amplification
operation, the transistor is always in the ON state.
 DIGITAL ELECTRONIC COMPONENTS
• Digital electronics deal with digital or discrete signals.
Microprocessors, Microcontrollers, and System on Chips
(SoCs) work on digital principles. They interact with the
rest of the world through digital I/O interfaces and process
digital data.
Open Collector and Tri-State Output:
• Open collector is an I/O interface standard in digital
system design and is commonly used in conjunction with
the output of an Integrated Circuit (IC) chip and facilitates
the interfacing of IC output to other systems which
operate at different voltage levels.
• In the open collector confi guration, the output line from
an IC circuit is connected to the base of an NPN transistor.
 DIGITAL ELECTRONIC COMPONENTS
• For the output pin to function properly, it should be
pulled, to the desired voltage for the o/p device, through a
pull-up resistor. The output signal of the IC is fed to the
base of an open collector transistor.
 DIGITAL ELECTRONIC COMPONENTS
• When the base drive to the transistor is ON and the
collector is in open state, the o/p pin floats. This state is
also known as ‘high impedance’ state.
• Here the output is neither driven to logic ‘high’ nor logic
‘low’.
• If a pull-up resistor is connected to the o/p pin, when the
base drive is ON, the o/p pin becomes at logic 0 (0V). With
a pull-up resistor, if the base driver is 0, the o/p will be at
logic high (Voltage = Vcc).
• The advantage of open collector output in embedded
system design are:
 DIGITAL ELECTRONIC COMPONENTS
1. It facilitates the interfacing of devices, operating at a
voltage different from the IC, with the IC. Thereby, it
eliminates the need for additional interface circuits for
connecting devices at different voltage levels.
2. An open collector configuration supports multi-drop
connection, i.e., connecting more than one open
collector output to a single line.
3. It is easy to build ‘Wired AND’ and ‘Wired OR’
configuration using open collector output lines
• The output of a standard logic device has two states,
namely ‘Logic 0 (LOW)’ and ‘Logic 1 (HIGH), and the
output will be at any one of these states at a given point
of time, whereas tri-state devices have three states for the
output, namely, ‘Logic 0 (LOW)’, ‘Logic 1 (HIGH) and ‘High
Impedance (FLOAT)’.
 DIGITAL ELECTRONIC COMPONENTS
• A tri-state logic device contains a device activation line
called ‘Device Enable’ and when is activated, the device
acts like a normal logic device and the output will be in
any one of the logic conditions, ‘Logic 0 (LOW)’ or ‘Logic 1
(HIGH)’.
• When the ‘Device Enable’ line is de-activated, the output
of the logic device enters in a high impedance state and
the device is said to be in the floating state.
• The tri-stated output condition produces the effect of
‘removing’ the device from a circuit and allows more than
one devices to share a common bus. With multiple ‘tri-
stated’ devices share a common bus, only one ‘device’ is
allowed to drive the bus at any given point of time and
rest of the devices should be in the ‘tri-stated’ condition.
 DIGITAL ELECTRONIC COMPONENTS
Logic Gates
• Are the building blocks of digital circuits and control the
flow of digital information by performing a logical
operation of the input signals.
• Depending on the logical operation, the logic gates are
classified into–AND, OR, XOR, NOT, NAND, NOR and XNOR.
The logical relationship between the output signal and the
input signals for a logic gate is represented using a truth
table.
• The truth table and symbolic representation of each logic
gate as:
 DIGITAL ELECTRONIC COMPONENTS
Buffer
• A buffer circuit is a logic circuit for amplifying the current
or power, that is, it increases the driving capability of a
logic circuit.
• A tri-state buffer is a buffer with Output Enable control,
when the Output Enable control is avctive, the tri-state
buffer functions as a buffer else remains at high
impedance state (Tri-stated).
• Tri-state buffers are commonly used as drivers for address
bus and to select the required device among multiple
devices connected to a shared data bus and are available
as either unidirectional or bi-directional buffers.
 DIGITAL ELECTRONIC COMPONENTS
Buffer
• 74LS244/74HC244 is an example of unidirectional octal
buffer and it contains 8 individual buffers which are
grouped into two where each buffer group has its own
output enable line.
 DIGITAL ELECTRONIC COMPONENTS
Latch
• A latch is used for storing binary data that contains an
input data line, clock or gating control line for triggering
the latching operation and an output line.
• The gating signal can be either a positive edge or a
negative edge. Whenever a latch trigger happens, the data
present on the input line is latched and the latched data is
available on the output line of the latch until the next
trigger.
• D flip flop (S-R, J-K, T)is a typical example of a latch.
• In electronic circuits, latches are commonly used for
latching data, which is available only for a short duration.
Latch
• Latches are available as integrated circuits, IC 74LS373
being a typical example, contains 8 individual D latches.
• The Address Latch Enable (ALE) pulse generated by the
processor, when the Address bits are available on the
multiplexed bus, is used as the latch trigger.
Decoder
• A decoder is a logic circuit which generates all the possible
combinations of the input signals and are named with
their input line numbers and the possible combinations of
the input as output.
• For examples, 2 to 4 decoder, 3 to 8 decoder and 4 to 16
decoder, where 3 to 8 decoder contains 3 input signal lines
and 8 different possible output lines.
• Decoders are mainly used for address decoding and chip
select signal generation in electronic circuits and are
available as integrated circuits.
• 74LS138/74AHC138 is an example for 3 to 8 decoder IC.
The decoder output is enabled only when the ‘Output
Enable’ signal lines E1\, E2\ and E3 are at logic levels 0, 0
and 1 respectively.
Decoder
3 to 8 Decoder IC and I/O signal states
Encoder
• An encoder performs the reverse operation of decoder
that is, it encodes the corresponding input state to a
particular output format.
• Examples are 4 to 2 encoder, 8 to 3 encoder and 16 to 4.
• The 8 to 3 encoder contains 8 input signal lines and it is
possible to generate a 3 bit binary output corresponding
to the input and the corresponding output line is asserted
in accordance with the input signals. If the input line 1 is
asserted, the output lines A0, A1 and A2 are asserted as 0,
1 and 1 respectively.
• Encoders are mainly used for address decoding and chip
select signal generation in electronic circuits and are
available as integrated circuits. 74F148/74LS148 is an
example of 8 to 3 encoder IC.
Encoder
• 8 to 3 Encoder IC and I/O signal states
Multiplexer (MUX)
• A MUX can be considered as a digital switch which
connects one input line from a set of input lines, to an
output line at a given point of time. It contains multiple
input lines and a single output line.
• The inputs of a MUX are said to be multiplexed and it is
possible to connect one input with the output line at a
time where the input line is selected through the MUX
control (Select) lines.
• 74S151 is an example for 8 to 1 MUX IC, where is enabled
only when the ‘Enable signal (EN)’ line is at logic 0.
• A ‘High’ on the EN line forces the output to the inactive
state. The input signal is switched to the output line
through the channel select control lines A2, A1 and A0.
Multiplexer (MUX)
• In order to select a particular input line, apply its binary
equivalent to the channel select lines A0, A1 and A2 (e.g.
set A2A1A0 as 000 for selecting Input D0, and as 001 for
selecting channel D1, etc.).
De-multiplexer (D-MUX)
• A de-multiplexer performs the reverse operation of
multiplexer and switches the input signal to the selected
output line among a number of output lines. The output
line to which the input is to be switched is selected by the
output selector control lines.
• The 1 to 2 de-multiplexer, NL7SZ18 is a typical example for
that contains a single input line and two output lines to
switch the input line. The output switching is controlled by
the output selector control.
VLSI AND INTEGRATED CIRCUIT DESIGN
• In the beginning, electronic circuits are built around the
vacuum tube technologies. As technology progressed,
transistors came into the picture and then circuit designs
shifted to transistor based technology.
• In the ancient times thousands of individual transistors
were required to build a digital or analog functionality
where, transistors were interconnected using conductive
wires for building the required functionality.
• Due to improvement in technology, the concept of
miniaturisation evolved and researchers and designers
were able to build the required functionality within a
single silicon wafer, in places of thousands of
interconnected transistors.
VLSI AND INTEGRATED CIRCUIT DESIGN
• An Integrated Circuit (IC) is a miniaturised form of an
electronic circuit containing transistors and other passive
electronic components and the circuits required for
building the functionality are built on the surface of a thin
silicon wafer.
• The first integrated circuit was designed in the 1950s and
depending on the number of integrated components, the
degree of integration within an IC called as:
• Small-Scale Integration (SSI): Integrates one or two logic
gate(s) per IC, e.g. LS7400.
• Medium-Scale Integration (MSI): Integrates up to 100
logic gates in an IC. The decade Counter 7490 is an
example for MSI device
VLSI AND INTEGRATED CIRCUIT DESIGN
• Large-Scale Integration (LSI): Integrates more than 1000
logic gates in an IC.
• Very Large-Scale Integration (VLSI): Integrates millions of
logic gates in an IC. Pentium processor is an example of a
VLSI Device.
• The IC design methodology has evolved over the years
from the first generation design, SSI to designs with
millions of logic gates where, gate count is a measure of
the complexity of the IC.
• In today’s world almost all IC designs fall under the
category VLSI and it is a common practice to term IC
design as VLSI design. Depending on the type of circuits
integrated in the IC, the IC design is categorised as:
VLSI AND INTEGRATED CIRCUIT DESIGN
• Digital Design: Deals with the design of ICs handling digital
signals and data. The I/O requirement for such an IC is
always digital. Microprocessor/ microcontroller, memory,
etc. are the examples.
• Analog Design: Deals with the design of ICs handling
analog signals and data. Analog design gives more
emphasis to the physics aspects of semiconductor devices
such as gain, power dissipation, resistance, etc.
• RF IC design, Op-Amp design, voltage regulator IC design,
etc. are examples for Analog IC Design.
• Mixed Signal Design: Mixed signal design involves design
of ICs, which handle both digital and analog signals as well
as data. Design of an analog-to-digital converter is an
example for mixed signal IC design.
VLSI AND INTEGRATED CIRCUIT DESIGN
• Integrated circuit design or VLSI design involves a number
of steps namely, system specification, functional or
architectural design, functional simulation, logic synthesis,
physical layout (placement and routing) and timing
simulation.
• In system specification the requirements of the chip under
development are listed out.
• It captures information on ‘what the chip does?’, the input
and output to the chip, timing constraints, power
dissipation requirements, etc.
• The functional or architectural design involves identifying
the various functional modules in the design and their
interconnections. It represents an abstraction of the chip
under development.
VLSI AND INTEGRATED CIRCUIT DESIGN
• The functional aspects of a chip can be captured using
Computer Aided Design (CAD) tools with various methods
like block diagrams, truth tables, flow charts, state
diagrams, schematic diagrams and Hardware Description
Language (HDL).
• The functional simulation process simulates the
functioning of the circuit captured using design entry
techniques, using a functional simulation tool.
• During simulation, input stimuli are applied to the circuit
and the output is verified for the required functionality.
• The logic synthesis phase involving optimization and
mapping, transforms the design into a gate level netlist
corresponding to the logic resource available in the target
chip.
VHDL for VLSI Design
• Very High Speed Integrated Circuit HDL or VHDL is a
hardware description language used in VLSI design.
• VHDL is a technology independent description, which
enables creation of designs targeted for a chosen
technology (like CPLD, FPGA, etc.) using synthesis tools
and enables one keep up with the fast development of
semiconductor technology.
• VHDL can be used for describing the functionality and
behaviour of the system, or describing the actual gate and
register levels of the system and it also supports
concurrent, sequential, hierarchical and timing modelling.
• VHDL also possess certain set of rules and characteristics:
VHDL for VLSI Design
VHDL for VLSI Design
VHDL for VLSI Design
VHDL for VLSI Design
VHDL for VLSI Design
VHDL for VLSI Design
• The basic structure of a VHDL design consists of
an entity, architecture and signals.
• The entity declaration defines the name of the
function being modelled and its interface ports
to the outside world, their direction and type.
VHDL for VLSI Design
• The architecture describes the internal structure
and behaviour of the model.
• Architecture can define a circuit structure using
individually connected modules or model its
behaviour using suitable statements.
VHDL for VLSI Design
• Signals in VHDL carry data which connects an
output and an input of two components (e.g. Gates,
flip-fl ops, etc.) of a circuit.
• A signal must be defined prior to its use. e.g. Signal
a: bit; where signal ‘a’ takes values of type bit.
• Once a signal has been defined, values can be
assigned to the signal. e.g. a <= ‘1’; where, value ‘1’
is assigned to the signal ‘a’.
VHDL for VLSI Design
• The library definition defines that all data types,
functions, etc available in the package std_
logic_1164 in the library ieee can be used in the
underlying entity.
• As an example for VHDL based design, let us
consider the design of a D flip-flop.
VHDL for VLSI Design
VHDL for VLSI Design
• “DFF” is the name of the model and D, CLK, Q are
the interface ports. The architecture describes the
internal structure and behaviour of the model.
• The architecture “DFF-ARCH” describes the D flip-
flop function.
• The HDL model of the circuit is then complied and
loaded in an HDL simulator.
• The simulator enables the designer to apply the
input stimuli to the design and observe whether the
output response is as expected.
• If there are any functional errors, the HDL code is
corrected and the design re-simulated, till the
design meets the functional specifications.
VHDL for VLSI Design
• A synthesiser tool compiles the source code to an
optimised technology dependent circuit at the gate
level.
• The inputs to a synthesiser are the HDL code, a
technology library, and constraints. The constraints
are in terms of the area and speed requirements of
the circuit to be realised in the target technology.
• Compilation: The HDL is translated to a generic
netlist
• Optimisation: The generic netlist is mapped to a
target technology (ASIC/FPGA) satisfying the
requirements of area and speed.
Various steps involved in a HDL based design:
ELECTRONIC DESIGN AUTOMATION (EDA) TOOLS
• Early embedded products were built around the old
transistor and vacuum tube technologies, where the
designers built the PCB with their hands, oil paper,
pencil, pen, ruler and copper plates.
• The process of building a PCB was a tedious and time
consuming process where the designers sketch the
required connections using pen, pencil and ruler on
papers and the finished sketch was used for etching the
connections on a copper plate and it took weeks and
months time to finish a PCB.
• The more the inter connections, the more difficult was
the process, accuracy and finishing of the PCB was
highly dependent on the artistic skills of the designer.
ELECTRONIC DESIGN AUTOMATION (EDA) TOOLS
• Early embedded products were built around the old
transistor and vacuum tube technologies, where the
designers built the PCB with their hands, oil paper,
pencil, pen, ruler and copper plates.
• The process of building a PCB was a tedious and time
consuming process in ancient times where the
designers sketch the required connections using pen,
pencil and ruler on papers and the finished sketch was
used for etching the connections on a copper plate and
it took weeks and months time to finish a PCB.
• The more the inter connections involved in the
hardware, the more difficult was the process
ELECTRONIC DESIGN AUTOMATION (EDA) TOOLS
• Advances in computer technology and IT brought out highly
sophisticated and automated tools for PCB design and
fabrication, where software packages gives an automatic
routing and layout for the product in a few seconds.
• These software packages are widely known as Electronic
Design Automation ( EDA) tools and various manufactures
offer these tools for different operating systems (Windows,
UNIX, Linux etc).
• EDA tool is a set of Computer Aided Design/Manufacturing
(CAD/CAM) software packages which helps in designing
and manufacturing the electronic hardware like integrated
circuits, printed circuit board, etc.
• The key players of the EDA tool industry are Cadence,
Protel, Altium, Cadsoft, Zuken, Mentor, etc.