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ELectronics-I - BJT-DC - Biasing-Lecture-02B

The document discusses various biasing techniques for BJTs, focusing on emitter-stabilized bias circuits and voltage-divider bias circuits. It highlights the improved stability of emitter-stabilized configurations compared to fixed-bias setups and introduces voltage-divider bias as a method to reduce dependence on transistor beta. Additionally, it covers the concept of DC bias with voltage feedback to further enhance stability against temperature variations and beta changes.

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7 views14 pages

ELectronics-I - BJT-DC - Biasing-Lecture-02B

The document discusses various biasing techniques for BJTs, focusing on emitter-stabilized bias circuits and voltage-divider bias circuits. It highlights the improved stability of emitter-stabilized configurations compared to fixed-bias setups and introduces voltage-divider bias as a method to reduce dependence on transistor beta. Additionally, it covers the concept of DC bias with voltage feedback to further enhance stability against temperature variations and beta changes.

Uploaded by

kmomoh599
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ELECTRICAL & ELECTRONICS

ENGINEERING

ELECTRONICS-I

Lecture Presentation By:

Dr. ABDULAI SANKOH


EMITTER-STABILIZED BIAS CIRCUIT
❑ The addition of the emitter resistor to the dc bias of the
BJT provides improved stability,
❑ Improved stability implies, the dc bias currents and
voltages remain closer to where they were set by the
circuit when outside conditions, such as temperature, and
transistor beta, changes.
Fig. 23
❑ Emitter-stabilizing circuit has
improve stability level compared
to the fixed-bias configuration.
EMITTER-STABILIZED BIAS CIRCUIT
Base-Emitter Loop Fig. 23a

❑ Using Kirchhoff’s voltage law


around the indicated loop in
the clockwise direction will
result in the following
equations:

Eq. (21)

❑ Note that the only difference between this equation for IB


and that obtained for the fixed-bias configuration is the
term (β+1)RE.
EMITTER-STABILIZED BIAS CIRCUIT
Collector-Emitter Loop Fig. 23b

❑ Again using Kirchhoff’s voltage law


for the indicated loop in will result in:

Eq. (22)

❑ The voltage from emitter ground is VE :


Eq. (23)

❑ Voltage from collector to ground is given as:

Eq. (24)
EMITTER-STABILIZED BIAS CIRCUIT
❑ Voltage at the base with respect to ground is given as:

Eq. (25)
Fig. 24
Saturation Level
❑ The collector saturation level or
maximum collector current for an
emitter-bias design can be determined
by applying a short circuit across the
collector-emitter terminals of the circuit
Fig 3 and calculate the resulting
collector current.
Eq. (26)

❑ The addition of the emitter resistor reduces the collector


saturation level below that obtained with a fixed-bias
configuration using the same collector resistor.
VOLTAGE-DIVIDER BIAS CIRCUIT
❑In the previous bias configurations the bias
current ICQ and voltage VCEQ were a function of
the current gain (β) of the transistor.

❑However, since β is temperature sensitive,


especially for silicon transistors, and the actual
value of beta is usually not well defined, it would
be desirable to develop a bias circuit that is less
dependent, or in fact, independent of the
transistor beta.

❑The voltage-divider bias configuration of the


figure below is such a network.
VOLTAGE-DIVIDER BIAS CIRCUIT
Fig. 25

❑ If analysed on an exact basis, the sensitivity to changes in


beta is quite small.

❑ If the circuit parameters are properly chosen, the resulting


levels of ICQ and VCEQ can be almost totally independent of
beta.
VOLTAGE-DIVIDER BIAS CIRCUIT
❑ It has been established that, a Q-point is defined by a fixed
level of ICQ and VCEQ. The level of IBQ will change with the
change in beta, but the operating point on the
characteristics defined by ICQ and VCEQ can remain fixed if
the proper circuit parameters are employed.

Analysis
❑ Using thevenim’s theorem, the input side of the network can be
redrawn as shown below for the dc analysis.
Fig. 25a
VOLTAGE-DIVIDER BIAS CIRCUIT

❑ For RTH, replacing the voltage source with a short circuit


result in the circuit below

Eq. (27)

❑ For ETH, the voltage source VCC is replace resulting in the open-
circuit thévenim voltage and applying the voltage-divider rule

Eq. (28)
VOLTAGE-DIVIDER BIAS CIRCUIT
❑ Redrawing the Thévenim network as shown in below, IBQ can
be determined by applying Kirchhoff’s voltage law.

Eq. (29)

❑ Once IB is known, the remaining quantities of the network can


be found in the same manner as developed for the emitter-
bias configuration. Thus,

Eq. (30)

❑ For transistor saturation, the output collector-emitter circuit


for the voltage-divider bias configuration has the same
appearance as the emitter-biased circuit analysed.
DC BIAS WITH VOLTAGE FEEDBACK CIRCUIT
❑ Stability level can be further improved by introducing a
feedback path from collector to base.
❑ Although the Q-point is not totally independent of beta (even
under approximate conditions), the sensitivity to changes in
beta or temperature variations is normally less than
encountered for the fixed-bias or emitter-biased configurations.

Fig. 26
DC BIAS WITH VOLTAGE FEEDBACK CIRCUIT
Base-Emitter Loop
❑ The circuit of Fig. 26a shows the base-emitter loop for the
voltage feedback configuration

❑ Note that the current through RC


is not IC but I'C (where I'C = IC + IB).
However, the level of IC and I'C far
exceeds the usual level of IB and
the approximation I'C = IC is
normally employed. Substituting
I'C = IC = βIB and IE = IC will yield.

Eq. (31) Fig. 26a

❑ The feedback path results in a reflection of the resistance RC


back to the input circuit, just like as the reflection of RE.
DC BIAS WITH VOLTAGE FEEDBACK CIRCUIT
Collector-Emitter Loop
❑ The dc bias voltage feedback circuit is redrawn to
produce collector-emitter circuit as shown below

❑ Applying Kirchhoff’s voltage law


around the circuit yields;

Eq. (31)

❑ Eq. (31) is exactly the same as that


obtained for the emitter-bias and
voltage-divider bias configurations. Fig. 26b
THANK YOU

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