Phase Locked Loops-A Control Centric Tutorial

Agilent Labs Phase-Locked Loops: A Control Centric Tutorial May 8, 2002
Phase-Locked Loops: A Control Centric Tutorial

Danny Abramovitch
Agilent Labs
3500 Deer Creek Road, MS: 25U-9
Palo Alto, CA 94304-1392
E-mail: [email protected]
May 8, 2002
“Then I locked the phase, now I’m a believer ...”

– Shrek takes up engineering
Slides and preprint available at: http://www.labs.agilent.com/personal/Danny Abramovitch/pubs/
COMMUNICATIONS AND OPTICS

2002 ACC RESEARCH LAB
1
Talk Outline
• Brief History
• PLL Basics
• Linear Analysis Methods for Classical PLLs
• Nonlinear Analysis Methods for Classical PLLs
• Digital PLLs
• Loop Components
– Phase Detectors
– Voltage Controlled Oscillators
– Loop Filters
• Noise
• Applications
– PLL Applications in Control Problems
• Advanced Topics/Areas For Contribution/Useful References

2
An Abbreviated History of PLLs

• Coincides with invention of “coherent communication” (DeBellescize, 1932).
• The earliest widespread use of PLLs to the horizontal and vertical sweeps used in television,
where a continuous clocking signal had to be synchronized with a periodic synch pulse (Wendt
& Fredendall, 1943). PLLs critical to development of color television (Richman, 1954).
• The first PLL IC arrived around 1965. This created an explosion in the use of PLLs.
• The first digital PLL appeared around 1970. This was of the classical digital PLL type.
• A few years later, the first all digital PLL appeared.
• The first laser appears in 1960. The first optical PLL arrives 4 years later.
• PLLs today:
– PLLs in every cell phone, television, radio, pager, computer, all telephony, ...
– The most prolific feedback system built by engineers.
– At low end: all software PLLs implement entire PLL functionality on sampled data.
– At high end: optical PLLs used in clock recovery for 160 Gbps data (OFC 2002).
– Boy band called: N’Sync.
• So, why aren’t we paying attention?
– The field is both mature and bleeding edge.

– Main contributions come from circuit designers.
– They tend to be great at circuit design, but weak with filters & loop dynamics.

3
PLL Basics
Phase Loop
Detector Filter
Reference
Signal
Voltage
Controlled
Signal Oscillator
Phase-Locked
to Reference
• Basic idea of a phase-locked loop:
– inject sinusoidal signal into the reference input

– the internal oscillator locks to the reference
– frequency and phase differences between the reference and internal sinusoid =⇒ k or 0
– Internal sinusoid then represents a filtered version of the reference sinusoid.
– For digital signals, Walsh functions replace sinusoids.

4
General PLL Block Diagram
Phase Loop
Detector Filter
Reference
Signal
Voltage
Controlled
Signal Oscillator
Phase-Locked
to Reference
• A phase detector (PD). This is a nonlinear device whose output contains the phase
difference between the two oscillating input signals.
• A voltage controlled oscillator (VCO). This is another nonlinear device which pro-
duces an oscillation whose frequency is controlled by a lower frequency input voltage.
• A loop filter (LF). While this can be omitted, resulting in what is known as a first
order PLL, it is always conceptually there since PLLs depend on some sort of low
pass filtering in order to function properly.
• A feedback interconnection. Namely the phase detector takes as its input the
reference signal and the output of the VCO. The output of the phase detector, the
phase error, is used as the control voltage for the VCO. The phase error may or may
not be filtered.

5
Unique features of PLLs as Control Loops
• Correct operation depends on being nonlinear. Phase detector action (frequency to

phase) and VCO action (phase to frequency) are nonlinear. Different parts of loop
are in different spaces (signal response and phase response).
• PLLs are almost always low order (not counting various high frequency filters and
parasitic poles). Typically first or second order. A few third or fourth order loops.
• With the exception of PLL controlled motors, the PLL designer is responsible for
designing/specifying all the components of the feedback loop. Complete feedback
loop design replaces control law design, and the designer’s job is governed only by
the required characteristics of the input reference signal, the required output signal,
and technology limitations of the circuits themselves.
• PLL control of motors, the motor and optical coupler takes the place of the VCO.
The rest is at the designer’s discretion.
• Control theory used in most PLL texts is straight linear system design with a small
amount of nonlinear heuristics thrown in.
• Stability analysis and design of the loops is combination of linear analysis, rule of
thumb, and simulation.
• Experts in PLLs tend to be electrical engineers with hardware design backgrounds.
• General theory of PLLs and ideas on how to make them even more useful seems to
cross into the controls literature only rarely.

6
PLL Basics
Asin(wit + qi)
Loop
Filter
Reference
Signal VCO
Control
cos(wot + qo) Voltage Voltage
Controlled
Signal Oscillator
Phase-Locked
to Reference
• General sinusoid at reference input can be written as:
vi = R1 (t) = A sin(ωi t + θi ). (1)
• WLOG, assume VCO output signal is
vo = V COout (t) = cos(ωo t + θo ). (2)
• Mixer output:
vd = M ixerout (t) = AKm sin(ωi t + θi ) cos(ωo t + θo ), (3)
where Km is the gain of the mixer.

7
Typical simplifying steps:
High
Bandpass Loop
Frequency
Filter Filter
LP Filter
Reference
Signal
Voltage
Controlled
Signal Oscillator
Phase-Locked
to Reference
• Using the familiar trigonometric identity in terms of the PLL:
2 sin(ωi t + θi ) cos(ωo t + θo ) = sin((ωi + ωo )t + θi + θo ) + sin((ωi − ωo )t + θi − θo ) (4)
• Two fundamental assumptions lead to common analog PLL model. Let θd = θi −θo . Then these assumptions
are:
1) The first term in (4) is attenuated by the high frequency low pass filter in and by the low pass
nature of the PLL itself.
2) Let ωi ≈ ωo , so that the difference can be incorporated into θd . This means that the VCO can be
modeled as an integrator.
3) The baseband phase detector output is then:
AKm AKm
vd (t) ≈ sin(θi (t) − θo (t)) = sin(θd (t)) (5)
2 2

8
Standard Nonlinear Model for Analog PLLs
qi qd
S Kdsin( ) F(s)
- VCO
Ko
qo s x
This is still a nonlinear system. The typical analysis methods include:
1) Linearization: For θd small
sin θd ≈ θd and cos θd ≈ 1.
Useful for studying loops that are near lock, does not help when θd is large.
2) Phase plane portraits. Classical graphical method of analyzing behavior of low order
nonlinear systems about a singular point. Can only completely describe first and second
order systems.
3) Simulation. Explicit simulation of the entire PLL is relatively rare. Problem is stiff.
Simulations that sample fast enough to characterize the 2ωo t term are often far too slow
to effectively characterize the baseband.
=⇒ Simulate the response of the components (phase detector, filter, VCO) in signal
response space.
=⇒ Simulate the entire loop only in signal phase space.

9
Standard Linear Model for Analog PLLs
qi qd
S Kd F(s)
- VCO
Ko
qo s x
Used for most analysis and measurements of PLLs. Model has some omissions:
1) The texts typically omit the input bandpass filter.
• Not in the loop itself & the actual input frequency is often not known or is variable.
• The designer has some idea of the range of the signal.
• Input bandpass filter can considerably reduce broadband noise entering the system.
2) The texts typically omit the high frequency low pass filter. The loop filter is optimized
for the stability and performance of the baseband (phase).
3) Amplitude of the phase error is dependent upon A, the input signal amplitude. The
linearized model has a loop gain that is dependent upon the loop components. Thus,
in practical loop design, the input amplitude must either be regulated or its affects on
the loop must be anticipated.

10
Linear Analysis for Classical PLLs

• Hold Range: the frequency range over which the
PLL is able to statically maintain phase tracking:
• Transfer function from reference (input) phase
to oscillator (clock) phase ∆ωH = Ko Kd F (0).
θo (s) Kd F (s)Kv /s
T (s) = =
θi (s) 1 + Kd F (s)Kv /s
• Lock Range: the frequency range within which
Kd Kv F (s)
= the PLL locks within one single-beat note be-
s + Kd Kv F (s)
tween the reference frequency and output fre-
quency:
• Transfer function from reference phase to phase ∆ωL ≈ ±Ko Kd F (∞).
error
θd (s) 1
S(s) = = • The Pull-In and Pull-Out Range:
θi (s) 1 + Kd F (s)Kv /s
s The pull-in range, ∆ωP , is defined as the fre-
= quency range in which the PLL will always be-
s + Kd Kv F (s)
come locked. The pull-out range, ∆ωP O , is de-
fined as the limit of dynamic stability for the
PLL. No simple relationships for these.

11
The Steady-State Error via the Final Value Theorem
lim θd (t) = lim sθd (s)

t→∞ s→0
= lim sθi (s)S(s)
s→0
• VCO as integrator makes every PLL at least Type 1
– Zero steady state error to a phase step.
• Most PLL designs are second order, with integrator and minimum phase zero in the filter
=⇒ Type 2 systems.
– Zero steady state error to a phase ramp.
• Third order and higher PLL designs are not that common.
– Few applications need zero steady state error for an accelerating phase (e.g. deep space
communications with Doppler shift).
– Stability bounds for nonlinear third order system are not the same as stability bounds for
third order linear system.
Many PLLs have high frequency filters or parasitic capacitances, but these are well beyond the
loop bandwidth.

12
Nonlinear Analysis Methods for Classical PLLs
• Phase Plane
– Analyze the second order equation:

d2 φ λdφ
+ − cos φ = −ν
dτ 2 dτ
– Classical nonlinear systems analysis method, but limited to first and second order systems.
=⇒ Another reason why third order loops are avoided
• Lyapunov Redesign
– Construct energy function as:

 
θ 1
d x1
V = sin(σ)dσ + x1 x2 P  ,
0 2 x2
where the xi are the internal states of the PLL, θd is the error signal at the phase detector,
and the elements of P are chosen to satisfy LaSalle’s theorem.
– Generally useful for analog PLLs and classical digital PLLs, but sampling makes analysis a
lot harder.
– Not limited to any order PLL, but becomes unwieldy at higher orders
• Circle/Popov Criteria
– See Eva Wu’s talk later this session and previous work.

13
Digital Signals
• Replace analog voltages by digital logic levels
• One or more components replaced by a digital counterpart
• Common for clock signals and digital communications
• Important feature of digital PLLs:
– Most digital phase detectors are linear in phase over some region.
– Thus linear analysis is fairly accurate.
Classical Digital PLL

Digital • The phase detector is digital, working
Loop
Phase
Filter with binary values.
Detector
Reference • The filters and VCO are analog.

Signal
• One interpretation:
Voltage – Signal space is digital.
Signal Controlled
Phase-Locked Oscillator – Signal phase space is analog.
to Reference

14
All Digital PLLs

• An all digital phase locked loop.
Up
Digital • The digital phase detector produces
Phase Counter pulses that go into the count up or
Reference Detector
count down inputs of the counter,
Signal Down
which acts as the loop filter.
• The counter then adjusts the fre-

Signal
Phase-Locked Digitally quency of the digitally controlled os-
to Reference Controlled cillator (DCO).
Oscillator
• Another all digital phase locked loop.

n-bit Phase
Digital Error Digital • The digital phase detector produces
Phase Loop samples of phase error in an n-bit
Detector Filter
value.
Reference
Signal • This value is fed to a digital filter
whose output adjusts the the fre-
Digitally
quency of the digitally controlled os-
Signal Controlled cillator (DCO).
Phase-Locked Oscillator
to Reference

15
Software PLLs
Window (Freq.) Adjustment
error b win
Int0 S
-1 • An example of a software PLL that
z Int0 does clock/data recovery.
• This heuristic loop uses a zero cross-

ing detector on the sampled input.
z -1
• The effective sample rate is derived
edge from the average bit zero crossing
a z -1
S rate.
z -1
Edge (Phase) Adjustment
When data can be sampled at a rate substantially faster than the loop center frequency,
the entire loop operation can be implemented in software. This has the advantage of
flexibility. Any type of PLL can be implemented in software provided the sample rate is
high enough. Software loops have a lot in common with simulation. One key difference
is that the software loops deal with real data. Software PLLs may operate on the data in
real time, but can also be used in the post processing of measured data. One cautionary
note is that certain operations which are highly effective in hardware, such as limiters
which have a lot of high frequency content, create real sampling issues for software loops.

16
Talk Outline
• Brief History
• PLL Basics
• Digital PLLs
• Loop Components
– Phase Detectors
– Loop Filters
• Noise
• Applications

17
Phase Detectors
Phase Loop
Detector Filter
Reference
Signal
Voltage
Controlled
Signal Oscillator
Phase-Locked
to Reference
• Whether or not a PLL can track a signal is largely dependent on the phase detector.
• This is the usual starting point for any PLL design.
• Phase detector analysis is largely accomplished by drawing square wave diagrams

and then drawing conclusions about the baseband behavior.
• This is annoying to servo people, but it works.
• Drawing your own diagram is the only way to understand the workings of a phase
detector.

18
Phase Detectors (memoryless)

Vd
Reference
Signal Vdm
-p -p/2
• Classical mixing phase detector
p/2 p qe
VCO
Signal
• An over driven mixing phase detec-

tor.
Vd
Reference
Signal Vdm • As the mixer saturates, the outputs
Vdm
depend on the effective logical states
-p -p/2
of the input signals.
p/2 p qe
VCO • It starts to behave like an XOR.
Signal
• This is also a way to implement very
high speed XORs.
Vd
Vdm
Reference
vb • Phase detection using an XOR gate.
Signal vi -p -p/2
• Note that this accomplishes the same
VCO va p/2 p qe
Signal vo thing as an over driven mixer, but
vd = vb - va with digital circuitry.

19
XOR Phase Detector (Analysis)
• Analysis via square wave drawings.
• XOR response can be split into a 2X

term and a residual term.
• The average of the residual term is the

“baseband” that we care about.
vi
• Integrating over N clock periods drives
vo out the 2X term.
• A phase shift of π/2 produces a residual

vi XOR vo
of 0.
• A phase shift of π/4 produces a nonzero

residual.
vi • This is how most phase detectors are
analyzed.
vo
• In fact, the analog voltages contain
vi XOR vo many harmonics. In designing frequency
synthesizers, much effort is spent keep-
ing these harmonics from modulating
the VCO.

20
A 2 State Phase Detector
vi R Q1
Vd
Q Vdm
D
qe
Vd -p p
D
V Q2
Q
vo
• Two state phase detection using flip-flops as well as gates.
• The addition of the flip-flops adds memory to the system.
• The flip-flops are typically sensitive to only one clock edge

=⇒ only the leading edges of the input and oscillator signals matter, not their duty cycles.
• The characteristic is a sawtooth.
• The memory elements desensitizes the PD to duty cycles, but makes it more sensitive to noise.

21
Phase-Frequency Detector
Tri-State Charge
Phase-Frequency Pump
Detector
Vd
1
D Vdm
R
Q
vi R Vu -4p -2p qe
2p 4p
V
R Z
Q
vo D Vd
1
• The combination of a tri-state phase-frequency detector and a charge pump.
• The charge pump can be viewed as a 3 position switch controlled by the phase-frequency
detector.
• The action of the charge pump is to alleviate any loading of the phase detector in driving the
rest of the circuit. This allows the response to be smoother than without the charge pump.
• An extremely popular phase detector. Used in frequency synthesis, motor control, etc.
• Note that the loop filter is often implemented in the Z block of the charge pump.
• Note that the 4π linear range is due to memory. PD can come up in one of 2 possible states
and the PLL must account for this.

22
Phase-Frequency Detector (Analysis)
vi
• A small phase difference
shows that only the lead-
vo ing edges of the signal and
not the duty cycle are im-
portant.
vu
vd
vi
vo
• As only the leading edges
are significant, these are
vu
compared to show the
phase behavior of the de-
vd tector.
vd

23
Phase-Frequency Detector Applications

vi
• This diagram shows how
vo the PFD responds to fre-
quency errors.
vu • The response rapidly
slews the frequency to-
vd wards the correct value
(albeit in a nonlinear
fashion).
vd
vi
• This same property makes
the PFD ineffective for
vo use in clock data recovery
(CDR).
vu • The “missing” transitions
in the data trick the PFD
vd into slewing the frequency
to a lower clock rate, as
shown in the right dia-
vd gram.

24
Sample and Hold Phase Detector
Vd
vi
- Vdm
vi + -p -p/2
vo
p/2 p qe
vo
vd
• The input signal, vi is sinusoidal as shown in the right top plot.
• The VCO signal, vo is used to trigger sampling of vi as shown in the right middle plot.
• If the frequency of vo matches or is close to the input frequency, the value of the sampled signal will
depend only on the relative phase of vi and vo .
• Because the sample rate is below the Nyquist frequency, the samples alias down.
• These aliased samples create a phase error signal as seen in the right lower plot.
• The shape of the phase detector characteristic is based on the shape of the input signal, vi , so that if
vi is sinusoidal, v̄d is sinusoidal. If vi is triangular, v̄d is triangular. Finally, if vi is a square/rectangular,
then v̄d has a relay characteristic.
• Note also that there is no high frequency component resulting from this phase detector. This can
be seen analytically due to the fact that the zero-order hold has a zero at the sample frequency.

25
A Linear Clock Phase Detector
vi
(Data)
D vb
vo Vd
VH - VL
(Clock) Q1 4
vd qe
-p p
D va
Q2
Data For 50% transition density.
• The Hogge phase detector (Hogge, 1985).
• Used primarily in clock data recovery applications (CDR), the Hogge detector has a linear charac-
teristic.
• XOR output V̄b generates pulses where the leading edge is controlled by the data timing and the
trailing edge is controlled by the clock.
• Both edges of V̄a are controlled by the clock.
• So V̄b is modulated by the signal phase while V̄a is not.
• The difference gives a phase error for the data signal.

26
Operation of the Hogge Phase Detector
vi • Vi is data signal
• Vo is oscillator output (clock)

vo • Q1 and Q2 are retimed versions of Vi
• XORS give the following behavior:

Q1
– Vb is XOR of data signal and re-
timed data
vb – Va is XOR of Q1 and Q2 =⇒ not
modulated by phase
Q2 • avg(Vb − Va ) is linear with phase dif-
ference between data and clock
va

27
Bang Bang Phase Detector
Vd
c a
vi D Q D Q Vdm
(Data)
Data
vo qe
(Clock) -p p
b’ b
D Q D Q
bit center
Data
c b a bit edge
• The Alexander (Bang-Bang) phase detector.
• On the left is the original version made of component flip flops.
• The Bang-Bang phase detector is unique among the detectors presented here in that its baseband
behavior is never linear.
• Instead, the detector acts as a relay over the region from −π to π (on the right).
• Nonlinearity is a bad thing, but this is highly manufacturable for extremely high speed circuits.
• Analogous to Bang-Bang control.

28
Operation of the Bang-Bang Phase Detector
vi • The signals a, b, and c are re-timed

versions of the data signal.
CKM • a and c are one bit period apart, b is
sampled at the half period between a
and c.
CKC
• Basically, if a and c are the same,
then no transition has occurred and
c
the output of the phase detector is
tri-stated.
a
• If not, then the state depends on b.
• If b = a, then the clock is early.

b’
• If b = c, then the clock is late.

29
Voltage Controlled Oscillators (VCOs)
Phase Loop
Detector Filter
Reference
Signal
Voltage
Controlled
Signal Oscillator
Phase-Locked
to Reference
• The cleanliness of the output clock is largely determined by the VCO.
• People make careers out of doing VCO design and analysis of VCO noise.
• This corresponds to the pendulum portion of a mechanical clock.

30
Voltage Controlled Oscillators

• Actual clock from PLL is the VCO output.
• VCO’s frequency is modulated by input voltage.
• Ring Oscillator: common in monolithic topologies uses an odd number of inverters connected in a
feedback loop.
• Relaxation Oscillator: uses a Schmitt-trigger to generate a stable square wave.
• Resonant Oscillator: puts a resonant circuit in the positive feedback path of a voltage to current
amplifier. The amplifier is voltage to current amplifier with close to unity gain. The resonant circuit
in the positive feedback path has poles close to the jω axis.
L
vc C1 C2
C3
• The frequency is controlled by altering the capacitance of the resonator, typically by using a varactor
diode as a capacitor.
• Other forms of VCOs, such as crystal oscillators and YIG oscillators essentially run on the same
principle, but modify the resonant circuit.

31
Resonant Oscillator VCOs
S G(s)
R
+ R L
C1 C2
L C
F(s)
• On the left, a block diagram of an oscillator implemented as a positive feedback loop between a
voltage to current amplifier through a resonant circuit.
• On the right, examples of resonant circuits: a LC tank and a π network.
• Resonant filter:
2ζω0 s
F (s) = ,
s2 + 2ζω0 s + ω02
• For G(s) = K < 1

G(s) s2 + 2ζω0 s + ω02
V CO(s) = =K 2 ,
1 − G(s)F (s) s + 2ζ1 ω0 s + ω02
where ζ1 = (1 − K)ζ.
1
• The lowering of the damping ratio is called “Q multiplication” (Q = 2ζ ) and moves the poles even
closer to the jω axis.
• In the case of the π network, there is a complex pair of poles and one pole on the negative real axis.
The dominant effect, Q amplification, takes place on the complex pair.

32
Loop Filter
Phase Loop
Detector Filter
Reference
Signal
Voltage
Controlled
Signal Oscillator
Phase-Locked
to Reference
• The loop filter is the one place where the designer really gets to shape the loop.
• Unfortunately, most filters are first order.
=⇒ Not many degrees of freedom here.
• This is where (as a rule) circuit designers seem to fall apart.

33
Analog Loop Filters

C3
R2 C
R2 C2
R1
R1
va -
vi - vb + vo
R1
+ vo
R2 C3
C2
• Analog loop filter for differential inputs.
• Filter transfer function:

• First order, single ended input.
Vo sR2 (C2 + C3 ) + 1
• Filter transfer function: =− .
Va − Vb sR1 C2 (sR2 C3 + 1)
Vo sR2 C + 1
=− .
Vi sR1 C
• For a typical second order loop, we let C3 = 0.
• For single ended input, simply tie the positive

terminal of the op-amp to ground.
• For tutorial purposes only. Real implementation is different.

34
Digital Loop Filters

n-bit n-bit Filtered
Phase Phase
Error Digital Error Digitally
• When phase detector gives n-bit number, can
Loop Controlled
Filter Oscillator use standard digital filter.
• When phase detector gives pulses, filter is often

High state
n-count Digitally
implemented as some type of counter.
Counter Controlled
Oscillator
Low state
Example of counter filter:
• DCO center frequency set for nominal counter • PLL open loop is:
value, N
θout (z) Kd Kv T z(z + 1)
= ,
• up/down pulses add to/subtract from N θd (z) 2 (z − 1)2
• counter output is an average of the PD pulses: =⇒ poles stay in unit circle.
nout (z) = (1 + z −1 + z −2 + z −3 + . . .)θd (z), • Large excess in up or down pulses saturates the
counter in one direction or another =⇒ lowers
=⇒ digital integrator with a zero at z = 0. the effective loop gain but does not destabilize
loop.
• Equivalent transfer function:
nout (z) 1 z
= = .
θd (z) 1−z −1 z−1

35
Simplified Noise Analysis

qd
qi S Kd F(s) • Linear model of input and VCO noise
- passing through a PLL.
• Noise in output phase, θo , is one of

Ko the key performance measures of a
qo
S s
PLL.
qvco VCO
Extremely simplified view of phase noise. That’s another tutorial.

• Output phase as a function of inputs: • Within loop bandwidth, designer has some con-
trol over the effect of θi on θo through the shap-
θo = T (s)θi + S(s)θvco ing of the loop, but beyond the loop bandwidth,
θo is dominated by θvco .
• Assuming θi and θvco are independent, the PSD • Every component of PLL is a potential noise
of the output phase is given by: source:
Goo (jω) = T (jω)2 Gii (jω) + S(jω)2 Gvv (jω). =⇒ There are noise inputs all around the loop.
=⇒ People make careers out of modeling the in-
put noises.

36
Talk Outline
• Brief History
• PLL Basics
• Digital PLLs
• Loop Components
– Phase Detectors
– Loop Filters
• Noise
• Applications

37
A Sample of PLL Applications
The reason that PLLs are so ubiquitous is that they are so useful in so many applications.
• Carrier Recovery
• Costas Loop
• Clock/Data Recovery
• Frequency Synthesis
• Modulation/Demodulation
• PLL Applications in Control Problems
– Disk Drive Control

– Harmonic Compensation
– Motor Control

38
Carrier Recovery
• General block diagram of frequency
recovery from a modulated signal.
Nonlinear Phase Loop
Input
Device Detector Filter • When carrier has strong component
Signal in signal spectrum, PLL can lock.
Clock or • When carrier is missing from signal
Carrier Out Voltage
Controlled spectrum, PLL must be preceded by
Oscillator
a nonlinear element.
• Squaring loop to recover carrier from

a BPSK modulated signal.
• Signal looks like

m(t)sinwit m (t)cos2wit
2
r(t) = m(t) sin ωi t

Bandpass Phase Loop
Filter ( )2 Detector Filter
Input and m(t) is ±1.
Signal
• The spectrum of r has no component
wi 2 wi Voltage
at ωi (for equally probable +1 and −1
2 Controlled
bits).
Carrier Out Oscillator
• Squaring loop locks to 2ωi and divide-

by-2 circuit recovers ωi .

39
Costas Loop
Quadrature High
Frequency
LP Filter
Loop
VCO Filter
Reference
BPSK Signal -P/2
Clock
High Data
Frequency
In-Phase LP Filter
• A Costas loop can both recover the carrier and demodulate the data from such a signal.
• Intuitively, if there were no modulation, the upper arm is simply a PLL locks to a carrier.
• The effect of the lower arm of the loop is to lock to the modulation and cancel it out of the upper
arm of the loop.
• Does the same thing as squaring loop, but down converts signal to baseband & does filtering there.
• Multiplier accomplishes same thing as squarer.

40
Clock/Data Recovery
• RZ data (dark dashed) and NRZ data (solid
light)
vi • On left, conversion from NRZ data to RZ data

using analog circuits.
v’i
• On right, conversion from NRZ data to RZ data
vo using digital circuits.
• Bang-Bang and Hogge detector recover clock

directly from NRZ signal.
Data Data
In In
Delay
T/2
d/dt
XOR
( )2
Delay T/2
Bandpass
2 Bandpass Filter
d/dt () Filter

41
Frequency Synthesis
• Want to lock a clock with an input signal of a
different frequency.
y High y
• Synthesize a clock frequency from a lower fre-
Bandpass Phase f
Filter Detector Frequency quency input.
LP Filter
Reference
Signal fr • Harmonic locking loop generates a clock at N
fr
fr times input frequency.
Loop
N VCO Filter
• Non-integer N is possible.
Phase-Locked
to Reference • Example from storage industry: DVD+RW for-
Nfr
mat uses a high frequency wobble embedded in
the groove walls to synthesize a write clock fre-
quency.
T qd qdf
High
Bandpass Phase
Frequency
Filter Detector
LP Filter
Reference Harmonic
fr
Clock Corrector
Signal mT
fr
fr
Voltage
Loop
N Controlled
Oscillator
Filter S
Clock
Phase-Locked
to Reference
• It is possible to remove harmonic phase modu-
N fr
lation with a multi-rate harmonic corrector.

42
Disk Drive Control
• Amplitude encoded position error signal (PES)

in a hard disk. PLLs are used to time the acqui-
sition of the readback signal.
Sync A B Sync A B
• In phase encoding of position error the phase
difference between the reference mark and the
position mark gives a measure of the cross track
position.
Sync Time Shift Determines

Radial Position
Harmonic Compensation
• Harmonic compensation when frequency is known is fairly well known.
• When frequency is not known, PLL techniques can be used. See Wu & Bodson in
literature and later this session and Bodson & students in general.

43
Motor Control
Power
• Motor control using PLL techniques replaces lin-
Phase Amplifier ear control with a speed setpoint as reference
Loop
Frequency
Filter
Detector input and tachometer to measure rotational ve-
Setpoint locity.
(Shaft Speed) Analogous
to VCO
Optical
• Tachometer has been replaced by an “optical
Coupler tachometer” consisting of a segmented wheel
Motor
(GaAs)
attached to the rotor shaft and an optical cou-
Measured Shaft Speed
pler.
Number of segments = KZ
• Optical coupler is a photodiode followed by a

Schmitt Trigger =⇒ produces an oscillation pro- • Open loop response:
portional to the motor speed.  
1 + sτ2 Km Kz 
• Motor & optical coupler replace the VCO. HOL (s) = Ka Kd  .
sτ1 s(1 + sTm )
• Phase-frequency detector used =⇒ infinite pull with Ka = PA gain, Kd = the PFD gain, & loop
in range and there are no missing samples. filter = integrator with minimum phase zero.
• Motor model itself is second order: • During normal operation, the PFD in nonlinear
K m Kz regime as motor speed is ramped to different
Gm (s) = ,
s(1 + sTm ) setpoints. Adkins, Marra & Walcott later this
session improve steady state response by modi-
Km : motor torque constant, Tm : motor time
fying the behavior of the PFD
constant, & Kz is the number of segments in
the wheel.

44
Some Advanced Topics
• With all the available topologies and technologies, it should be clear that the choice of what
to use is very application dependent.
• Digital techniques have the advantages that they are relatively immune to circuit drift and easy
to integrate into small chip packages. However, they are not suitable for every application.
• For high noise input signals, the traditional mixer is still preferred as it makes the best use of
information in the signal amplitude to reject noise. Classical digital PLLs are extremely useful
in high speed digital communications systems.
• Some of the tradeoffs can be seen in high speed digital communications systems. As the
standard for these systems reaches beyond 10 gigabits per second (Gbps), to 40 and 100 Gbps,
the circuit technologies are hard pressed to produce the short pulses of phase detectors such
as the linear Hogge detector. Thus, the nonlinear Alexander detector is often preferred. This
is because the latter detector’s components are easy to integrate and the detector itself has
pulses that are no shorter than half a bit interval.
• At the extreme end, optical PLLs are being tested for clock/data recovery of 160 Gbps WDM
optical communications.
• At the other end of the spectrum, as processing power goes up, it becomes more practical
to sample the data and perform all the relevant operations in software Not only is this the
ultimate in flexibility, but it can also be the lowest in cost.

45
Areas for Contribution: Where can control theory help?
• Nonlinear analysis. While many loop properties can be analyzed with linear models,
this is not true for Bang-Bang loops, locking transients, and high frequency effects.
• Analyzing effects of noise injection from various components including phase detector
and VCO.
• Improved analysis of intersample behavior of digital PLLs.
• Design tools to optimize designs of PLLs for both phase performance and signal
performance.
• Some of these tools might also be useful in designing new phase detectors that are
optimized for a particular type of loop.
• Design methods for high order PLLs. Loop shaping, etc. Often times PLL designers
get forced by parasitic capacitances to deal with higher order loops. They have no
rigorous analysis for this.
• VCO gain varies across units and over the frequency tuning range of the oscillator.
We know how to handle this.
• Efficient simulation methods to allow for complete simulation of the system despite
the two time scales would be very useful and could further be applied to software
PLLs.

46
Useful References
• Andrew Viterbi’s classic book (sadly out of print), Principles of Coherent Communication, has a wonderful
first introduction to the analysis of a PLL. A. J. Viterbi, Principles of Coherent Communication. McGraw-
Hill Series in Systems Science, New York, NY: McGraw-Hill, 1966.
• Floyd Gardner’s famous little book, Phaselock Techniques, has been the classic first book for PLLs. It
provides basic analysis and applications for PLLs. For many years, the first edition was the main book on
the subject.
F. M. Gardner, Phaselock Techniques. New York, NY: John Wiley & Sons, second ed., 1979. ISBN
0-471-04294-3.
• Another of the classic PLL text is Alain Blanchard’s book, Phase-Locked Loops .
A. Blanchard, Phase-Locked Loops. New York, NY: John Wiley & Sons, 1976.
• Dan Wolaver’s book, Phase-Locked Loop Circuit Design provides excellent coverage of the different circuits
used in PLLs, including many different phase detector models. Wolaver tends to focus on classical analog
and classical digital PLLs.
D. H. Wolaver, Phase-Locked Loop Circuit Design. Advanced Reference Series & Biophysics and Bio-
engineering Series, Englewood Cliffs, New Jersey 07632: Prentice Hall, 1991.
• Roland Best’s book, Phase-Locked Loops: Design, Simulation, and Applications provides a more classical
analysis of PLLs. It does an excellent job of describing the various classes of PLLs, including classical
analog, classical digital, all digital, and software PLLs. Furthermore, a software disk is included. However,
the treatment of actual circuits is far more cursory than Wolaver’s book.
R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications. New York: McGraw-Hill, third ed.,
1997.

47
• The IEEE Press has published two books containing papers on PLLs, both co-edited by William C. Lindsey.
Phase-Locked Loops and Their Application, co-edited with Marvin K. Simon, contains many of the seminal
papers on PLLs.
W. C. Lindsey and M. K. Simon, eds., Phase-Locked Loops and Their Application. IEEE PRESS Selected
Reprint Series, New York, NY: IEEE Press, 1978.
Phase-Locked Loops, co-edited with Chak M. Chie, has a larger emphasis on digital loops.
W. C. Lindsey and C. M. Chie, eds., Phase-Locked Loops. IEEE PRESS Selected Reprint Series, New
York, NY: IEEE Press, 1986.
A third book from the IEEE, edited by Behzad Razavi on Monolithic Phase-Locked Loops and Clock
Recovery Circuits: Theory and Design goes into much more depth on issues of integration of PLLs and
CDR circuits into silicon. The collection starts with an excellent tutorial.
B. Razavi, ed., Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. IEEE
PRESS Selected Reprint Series, New York, NY: IEEE Press, 1996.
• Hsieh and Hung have a nice tutorial on PLLs that not only includes the basic theory, but also some
applications, particularly to motor control.
G.-C. Hsieh and J. C. Hung, “Phase-Locked Loop techniques — A survey,” IEEE Transactions on Industrial
Electronics, vol. 43, pp. 609–615, December 1996.
• Paul Brennan’s book, Phase-Locked Loops: Principles and Practice is a brief book with a practical bent.
It gives an excellent explanation of phase-frequency detectors and charge pumps.
P. V. Brennan, Phase-Locked Loops: Principles and Practice. New York: McGraw Hill, 1996.
• Donald Stephens has a book with an interesting history section in the front as well as a method of
approaching analysis of digital PLLs that is closer to a typical sampled data approach than most books.
This second edition of the book includes information on optical PLLs.

48
Phase-Locked Loops for Wireless Communications: Digital, Analog and Optical Implementation. Under-
standing Science and Technology, Boston/Dordrecht/London: Kluwer Academic Press, second ed., 2002.
• Someshwar Gupta’s survey paper provides a history of analog PLLs to that point.
S. C. Gupta, “Phase-locked loops,” Proceedings of the IEEE, vol. 63, pp. 291–306, February 1975.
• William C. Lindsey and Chak M. Chie have a survey paper that outlines the history of digital PLLs up
until 1981.
W. C. Lindsey and C. M. Chie, “A survey of digital phase-locked loops,” Proceedings of the IEEE, vol. 69,
pp. 410–431, April 1981.

49
Acknowledgments
The understanding of PLL circuit components presented here has been greatly enhanced
by discussions with
• Rick Karlquist, Rick Walker, and Len Cutler of Agilent Laboratories
• Dr. Salam Marougi of Agilent Technologies’ Electronic Products and Solution Group.
The control systems interpretation of various loop components improved dramatically

after discussions with Prof. Gene Franklin of Stanford University.
This session would not have happened without the rapid generation of papers by the
other session members:
• Prof. N. Eva Wu of SUNY Binghamton
• Chris Adkins and Mike Marra (both of Lexmark) and Dr. Bruce Walcott from the
University of Kentucky
• Biqing Wu and Prof. Marc Bodson of the University of Utah
Dan Witmer of Openwave who walked into my office at Ford Aerospace 14 years ago
and asked, “How would you analyze a nonlinear phase-locked loop?”

50

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Agilent Labs Phase-Locked Loops: A Control Centric Tutorial May 8, 2002

Phase-Locked Loops: A Control Centric Tutorial

“Then I locked the phase, now I’m a believer ...”

Slides and preprint available at: http://www.labs.agilent.com/personal/Danny Abramovitch/pubs/

COMMUNICATIONS AND OPTICS

• Linear Analysis Methods for Classical PLLs

• Nonlinear Analysis Methods for Classical PLLs

– PLL Applications in Control Problems

• Advanced Topics/Areas For Contribution/Useful References

COMMUNICATIONS AND OPTICS

An Abbreviated History of PLLs

• A few years later, the ﬁrst all digital PLL appeared.

• So, why aren’t we paying attention?

– The ﬁeld is both mature and bleeding edge.

COMMUNICATIONS AND OPTICS

• Basic idea of a phase-locked loop:

– inject sinusoidal signal into the reference input

COMMUNICATIONS AND OPTICS

General PLL Block Diagram

COMMUNICATIONS AND OPTICS

Unique features of PLLs as Control Loops

• Correct operation depends on being nonlinear. Phase detector action (frequency to

• Experts in PLLs tend to be electrical engineers with hardware design backgrounds.

COMMUNICATIONS AND OPTICS

vi = R1 (t) = A sin(ωi t + θi ). (1)

• WLOG, assume VCO output signal is

vo = V COout (t) = cos(ωo t + θo ). (2)

vd = M ixerout (t) = AKm sin(ωi t + θi ) cos(ωo t + θo ), (3)

where Km is the gain of the mixer.

COMMUNICATIONS AND OPTICS

Typical simplifying steps:

• Using the familiar trigonometric identity in terms of the PLL:

2 sin(ωi t + θi ) cos(ωo t + θo ) = sin((ωi + ωo )t + θi + θo ) + sin((ωi − ωo )t + θi − θo ) (4)

COMMUNICATIONS AND OPTICS

Standard Nonlinear Model for Analog PLLs

This is still a nonlinear system. The typical analysis methods include:

1) Linearization: For θd small

sin θd ≈ θd and cos θd ≈ 1.

COMMUNICATIONS AND OPTICS

Standard Linear Model for Analog PLLs

1) The texts typically omit the input bandpass ﬁlter.

COMMUNICATIONS AND OPTICS

Linear Analysis for Classical PLLs

COMMUNICATIONS AND OPTICS

The Steady-State Error via the Final Value Theorem

lim θd (t) = lim sθd (s)

• VCO as integrator makes every PLL at least Type 1

– Zero steady state error to a phase step.

– Zero steady state error to a phase ramp.

COMMUNICATIONS AND OPTICS

Nonlinear Analysis Methods for Classical PLLs

– Analyze the second order equation:

– Construct energy function as:

COMMUNICATIONS AND OPTICS

• Replace analog voltages by digital logic levels

• One or more components replaced by a digital counterpart

• Common for clock signals and digital communications

• Important feature of digital PLLs:

Classical Digital PLL

Reference • The ﬁlters and VCO are analog.