Table of Contents

Cover
Title
Copyright
Preface
1. Summary
2. The reader
1 Number Systems
1.1. Introduction
1.2. Decimal numbers
1.3. Binary numbers
1.4. Octal numbers
1.5. Hexadecimal numeration
1.6. Representation in a radix B
1.7. Binary-coded decimal numbers
1.8. Representations of signed integers
1.9. Representation of the fractional part of a number
1.10. Arithmetic operations on binary numbers
1.11. Representation of real numbers
1.12. Data representation
1.13. Codes to protect against errors
1.14. Exercises
1.15. Solutions
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2 Logic Gates
2.1. Introduction
2.2. Logic gates
2.3. Three-state buffer
2.4. Logic function
2.5. The correspondence between a truth table and a logic function
2.6. Boolean algebra
2.7. Multi-level logic circuit implementation
2.8. Practical considerations

Ndjountche, T. (2016). Digital electronics 1 : Combinational logic circuits. John Wiley & Sons, Incorporated.
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 2.9. Demonstration of some Boolean algebra identities
2.10. Exercises
2.11. Solutions
3 Function Blocks of Combinational Logic
3.1. Introduction
3.2. Multiplexer
3.3. Demultiplexer and decoder
3.4. Implementation of logic functions using multiplexers or decoders
3.5. Encoders
3.6. Transcoders
3.7. Parity check generator
3.8. Barrel shifter
3.9. Exercises
3.10. Solutions
4 Systematic Methods for the Simplification of Logic Functions
4.1. Introduction
4.2. Definitions and reminders
4.3. Karnaugh maps
4.4. Systematic methods for simplification
4.5. Exercises
4.6. Solutions
Bibliography
Index
End User License Agreement
Copyright © 2016. John Wiley & Sons, Incorporated. All rights reserved.

List of Tables
1 Number Systems
Table 1.1. Conversion tables for 0 numbers to 15
Table 1.2. Representations of unsigned and signed 3-bit integers
Table 1.3. Range of numbers that can be represented with the IEEE-754 standard
Table 1.4. Number format based on the IEEE-754 standard
Table 1.5. Values of numbers in IEEE-754 representations
Table 1.6. Binary and Gray code representation of decimal numbers from 0 to 15

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 Table 1.7. Examples of 2 -out-of-5 code
Table 1.8. ASCII codes table
2 Logic Gates
Table 2.1. Truth table. Input: A; Output: B
Table 2.2. Truth table. Inputs: A, B; Output: C
Table 2.3. Truth table. Inputs: A, B; output: C
Table 2.4. Truth table. Inputs: A, B; Output: C
Table 2.5. Truth table
Table 2.6. Truth table (sum of products)
Table 2.7. Truth table (product of sums)
Table 2.8. Truth table (sum of products)
Table 2.9. Basic properties for the NOT, AND and OR operations
Table 2.10. Truth table
Table 2.11. Truth table for
Table 2.12. Truth table for and
Table 2.13. Basic properties for the XOR and XNOR operations
Table 2.14. Truth table
Table 2.15. Truth table
3 Function Blocks of Combinational Logic
Table 3.1. Truth table of the 2-to-1 multiplexer
Table 3.2. Truth table of a 2:1 multiplexer
Table 3.3. Truth table of a 2-to-1 multiplexer
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Table 3.4. Truth table for the multiplexer shown in Figure 3.6(a)
Table 3.5. Truth table for the multiplexer shown in Figure 3.6(b)
Table 3.6. Truth table for an 8-to-1 multiplexer
Table 3.7. Truth table for the decoder
Table 3.8. Truth table for the decoder
Table 3.9. Truth table of a 1-to-2 demultiplexer
Table 3.10. Truth table of the 1-to-2 demultiplexer
Table 3.11. Truth table of a 2-out-of-4 decoder

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 Table 3.12. Truth table of a 1-to-4 demultiplexer
Table 3.13. Truth table for an 1-to-8 demultiplexer
Table 3.14. Truth table for the logic function Y
Table 3.15. Truth table (case 1)
Table 3.16. Truth table (case 2)
Table 3.17. Truth table of the 4 : 2 encoder with a validation output
Table 3.18. Truth table for an 8 : 3 encoder
Table 3.19. Truth table for a 4:2 priority encoder
Table 3.20. Truth table for 4 : 2 priority encoder with cascading capability
Table 3.21. Truth table for the 8 : 3 priority encoder
Table 3.22. Conversion of decimal numbers from 0 to 9 into binary representation
Table 3.23. Truth table for the priority encoder 74LS147
Table 3.24. Binary and Gray code for numbers from 0 to 15
Table 3.25. BCD to XS-3 conversion table
Table 3.26. BCD to XS-3 conversion table
Table 3.27. Example of three 8-bit words with parity bits
Table 3.28. Truth table for a parity generator for 4-bit words
Table 3.29. Table illustrating the operation of the parity generator/controller
Table 3.30. Operations realized by the barrel shifter
Table 3.31. Truth table of the barrel shifter
Table 3.32. Truth table of the 4-bit barrel shifter
Table 3.33. Truth table of the function F(A, B, C )
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Table 3.34. Truth table of the 2-out-of-4 decoder

Table 3.35. Truth table of the 2-out-of-2 decoder
Table 3.36. Truth table of the 8 : 3 priority encoder
Table 3.37. Truth table of the logic function F
Table 3.38. Truth table of the 2-out-of-4 decoder
Table 3.39. Truth table of the 1-to-4 demultiplexer
Table 3.40. Truth table
Table 3.41. Truth table

Ndjountche, T. (2016). Digital electronics 1 : Combinational logic circuits. John Wiley & Sons, Incorporated.
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 Table 3.42. Truth table of the 8-to-1 multiplexer
.

Table 3.43. Truth table

Table 3.44. Truth table of a multiplier for 2-bit words
Table 3.45. Truth table of a comparator for 2-bit numbers
Table 3.46. Truth table of the BCD-to-7-segment decoder
Table 3.47. Truth table of the HEX-to-7-segment decoder
Table 3.48. Truth table of the barrel shifter
Table 3.49. Truth table of the barrel shifter for right-shift operations
4 Systematic Methods for the Simplification of Logic Functions
Table 4.1. Truth table
Table 4.2. Table to determine prime implicants
Table 4.3. Table to determine the prime implicants using the consensus theorem
Table 4.4. Prime implicant chart for F
Table 4.5. Table for the determination of prime implicants
Table 4.6. Prime implicant chart for F: a) complete form and b) reduced form
Table 4.7. Table for the determination of prime implicants
Table 4.8. Prime implicant chart for F
Table 4.9. Reduced forms of the prime implicant charts for F
Table 4.10. Table for the determination of prime implicants
Table 4.11. Prime implicant chart for F
Table 4.12. Table for the determination of prime implicants
Table 4.13. Prime implicants chart for F
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Table 4.14. Table for the determination of prime implicants

Table 4.15. Table for the determination of prime implicants using the consensus
method
Table 4.16. Prime implicant chart for the functions F, G and F · G
Table 4.17. Reduced form of the prime implicant chart for the functions F, G and F ·
G
Table 4.18. Table for the determination of the prime implicants of Z1
Table 4.19. Prime implicant chart for Z1

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 Table 4.20. Table for the determination of the prime implicants of Z2
Table 4.21. Prime implicant chart for Z2
Table 4.22. Table for the determination of the prime implicants of Z3
Table 4.23. Prime implicant chart for Z3
Table 4.24. Reduced prime implicant chart for Z3
Table 4.25. Table for the determination of the prime implicants of Z4
Table 4.26. Prime implicant chart for Z4

List of Illustrations
1 Number Systems
Figure 1.1. Decimal-binary conversion using successive division methods
Figure 1.2. Representation of logic voltage levels
Figure 1.3. Decimal-octal conversion using the successive division method
Figure 1.4. Decimal-hexadecimal conversion using the successive division method
Figure 1.5. Obtaining a two’s complement from the binary representation: a) − 1010
and b) − 11910
Figure 1.6. Conversion of the decimal number 0.59375 using the successive
multiplication method
Figure 1.7. Range of numbers that can be represented in floating-point format
Figure 1.8. Barcodes corresponding to the binary representation 01100
Figure 1.9. Barcodes based on an interleaved 2-out-of-5 encoding
Figure 1.10. Example of block codes
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2 Logic Gates
Figure 2.1. Electric circuit that is the equivalent of the NOT gate
Figure 2.2. Electric circuit corresponding to the AND gate
Figure 2.3. Electric circuit corresponding to the OR gate
Figure 2.4. Electric circuit corresponding to the XOR gate, where pressure on either
push button S1 or push button S2 turns on the diode, but pressure on push button S1
and push button S2 turns off the diode
Figure 2.5. NOT gate. B =

Ndjountche, T. (2016). Digital electronics 1 : Combinational logic circuits. John Wiley & Sons, Incorporated.
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 Figure 2.6. AND gate C = A · B
Figure 2.7. OR gate C = A + B
Figure 2.8. XOR gate (exclusive OR)
Figure 2.9. NAND (NOT AND) (a), NOR (NOT OR) (b) and XNOR (NOT exclusive OR)
(c) gates
Figure 2.10. Three-state buffer
Figure 2.11. XOR gate: a) symbol; b) construction using NAND gates
Figure 2.12. XNOR gate: a) symbol; b) construction using NOR gates
Figure 2.13. Three-variable Karnaugh map
Figure 2.14. Four-variable Karnaugh map
Figure 2.15. Duad:
Figure 2.16. Duad:
Figure 2.17. Duad:
Figure 2.18. Quad:
Figure 2.19. Quad:
Figure 2.20. Quad:
Figure 2.21. Octad:
Figure 2.22. Octad:
Figure 2.23. Octad:
Figure 2.24. Octad:
Figure 2.25. Example 2.1(1):
Figure 2.26. Example 2.1(2):
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Figure 2.27. Example 2.1(3) (case 1):

Figure 2.28. Example 2.1(3) (case 2):
Figure 2.29. Example 2.1(4):
Figure 2.30. Example 2.1(5):
Figure 2.31. Example 2.2(a):
Figure 2.32. Example 2.2(b):

Figure 2.33. Function F

Figure 2.34. Function G

Ndjountche, T. (2016). Digital electronics 1 : Combinational logic circuits. John Wiley & Sons, Incorporated.
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 Figure 2.35. Logic circuits for the implementation of F and G
Figure 2.36. Logic circuit for the implementation of F
Figure 2.37. Logic circuit for the implementation of G
Figure 2.38. Equivalent circuits for the NAND gate
Figure 2.39. Implementation of the function F: a) circuit using AND and OR gates; b)
equivalent circuit; c) circuit based on NAND gates
Figure 2.40. Implementation of the function G: a) circuit using AND and OR gates; b)
equivalent circuit; c) NAND gate based circuit
Figure 2.41. Equivalent circuits for the NOR gate
Figure 2.42. Implementation of the function F: a) circuit using AND and OR gates; b)
equivalent circuit; c) NOR gate based circuit
Figure 2.43. Implementation of the function G: a) circuit using AND and OR gates; b)
equivalent circuits; c) NOR gate based circuit
Figure 2.44. Representation of
Figure 2.45. Representation of
Figure 2.46. Representation of
Figure 2.47. Representation of
Figure 2.48. Representation of
Figure 2.49. Representation of
Figure 2.50. Representation of
Figure 2.51. Representation of
Figure 2.52. Representation of
Figure 2.53. Representation of
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Figure 2.54. Representation of

Figure 2.55. Representation of
Figure 2.56. a) Logic circuit; b) timing diagram in an ideal case; c) timing diagram
illustrating the effect of a static hazard
Figure 2.57. a) Circuit with static hazard; b) logic circuit functioning without static
hazard; c) timing diagram
Figure 2.58. Circuit with hazard
Figure 2.59. Circuit without hazard

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 Figure 2.60. a) Logic circuit and b) timing diagram illustrating the effect of a
dynamic hazard
Figure 2.61. a) Logic circuit operating without hazard and b) timing diagram
Figure 2.62. Logic circuit
Figure 2.63. a) Circuit with NAND gates and b) circuit with NOR gates
Figure 2.64. a) Circuit with NOR gates and b) circuit with NAND gates
Figure 2.65. Logic circuits
Figure 2.66. Simplified circuits
Figure 2.67. Karnaugh maps (function E)
Figure 2.68. Karnaugh maps (function F )
Figure 2.69. Karnaugh maps (function G)
Figure 2.70. Karnaugh maps (function H)
Figure 2.71. Logic circuits
Figure 2.72. Implementation of H: logic circuit based on NAND gates
Figure 2.73. Implementation of the function Y
Figure 2.74. Implementation of P : a) logic circuit using AND and OR gates; b) logic
circuit based on NAND gates; c) logic circuit based on NOR gates
Figure 2.75. Implementation of Q: a) logic circuit using OR and AND gates; b) logic
circuit based on NAND gates; c) logic circuit based on NOR gates
Figure 2.76. Logic circuits
3 Function Blocks of Combinational Logic
Figure 3.1. 2-to-1 multiplexer: a) logic circuit and b) and c) symbols
Figure 3.2. Schematic diagram of the 2-to-1 multiplexer
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Figure 3.3. 2-to-1 multiplexer with an active-low enable input

Figure 3.4. 2-to-1 multiplexer based on three-state buffers
Figure 3.5. 4-to-1 multiplexers implemented using a) logic gates and b) 2-to-1
multiplexers; c) symbol
Figure 3.6. 4-to-1 multiplexer with an enable input: a) output set to zero when EN =
1; b) output set to high impedance state when EN = 1; c) symbol
Figure 3.7. 8-to-1 multiplexer implemented using a) logic ports or b) 4-to-1
multiplexers
Figure 3.8. 1-out-of-2 decoder with an active-high enable input

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 Figure 3.9. 1-out-of-2 decoder with an active-low enable input
Figure 3.10. 1-to-2 demultiplexer: a) logic circuit, b) schematic diagram illustrating
the working principle and c) symbols
Figure 3.11. Schematic diagram of a 1-to-2 demultiplexer
Figure 3.12. Three-state buffer based 1-to-2 demultiplexer
Figure 3.13. 2-out-of-4 decoder: implemented using a) logic gates or b) 1-out-2
decoders; c) symbol
Figure 3.14. 1-to-4 demultiplexers: implemented using a) logic gates or b) 1-to-2
demultiplexers; c) symbol
Figure 3.15. 1-to-8 demultiplexer implemented using a) logic gates or b) 1-to-4
demultiplexers; c) symbol
Figure 3.16. 2-out-of-16 decoder based on a matrix-type structure
Figure 3.17. a) Karnaugh map; b) logic circuit
Figure 3.18. Implementation of the functions P and Q using a 3-out-of-8 decoder
Figure 3.19. Y1 = D3 + D2
Figure 3.20. Y0 = D3 + D1
Figure 3.21. 4 : 2 encoder (case 1)
Figure 3.22. 4 : 2 encoder (case 2)
Figure 3.23. 4 : 2 encoder with a validation output
Figure 3.24. 8 : 3 encoder with a validation output
Figure 3.25. Representation of Y1 = D3 + D2

Figure 3.26. Representation of

Figure 3.27. Representation of V = D3 + D2 + D1 + D0
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Figure 3.28. 4 : 2 priority encoder with a validation output

Figure 3.29. Representation of
Figure 3.30. Representation of
Figure 3.31. Representation of
Figure 3.32. Representation of
Figure 3.33. Circuit a) and symbol b) for a 4 : 2 priority encoder with cascading
capability; c) 8 : 3 priority encoder
Figure 3.34. 10:4 priority encoder (integrated circuit 74LS147)

Ndjountche, T. (2016). Digital electronics 1 : Combinational logic circuits. John Wiley & Sons, Incorporated.
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 Figure 3.35. Representation of
Figure 3.36. Representation of
Figure 3.37. Representation of
Figure 3.38. Binary to Gray code converter
Figure 3.39. Representation of
Figure 3.40. Representation of
Figure 3.41. Representation of
Figure 3.42. Gray code to binary code converter
Figure 3.43. Representation of X3 = B3 + B2 · B1 + B2 · B0
Figure 3.44. Representation of
Figure 3.45. Representation of
Figure 3.46. Representation of
Figure 3.47. BCD to XS-3 converter
Figure 3.48. Representation of
Figure 3.49. Representation of
Figure 3.50. Representation of

Figure 3.51. Representation of

Figure 3.52. XS-3 to BCD converter
Figure 3.53. Representation of
Figure 3.54. Parity generator a) with or b) without selection signal
Figure 3.55. Parity generator/checker SN74180
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Figure 3.56. a) Parity generator; b) parity checker for 9-bit words

Figure 3.57. Barrel shifter for 4-bit binary words
Figure 3.58. Karnaugh maps: a) Y3 ; b) Y2 ; c) Y1 and d) Y0
Figure 3.59. Four-bit barrel shifter
Figure 3.60. Logic circuits with multiplexers
Figure 3.61. 2 : 4 decoder based on 1-to-2 multiplexers
Figure 3.62. 2-out-of-4 encoder with NAND gates
Figure 3.63. 8:3 priority encoder

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 Figure 3.64. a) 4-to-1 multiplexer with enable signal; b) symbol
Figure 3.65. a) 2 : 4 decoder with an enable input; b) logic circuit
Figure 3.66. Implementation of an 8-to-1 multiplexer based on a) four 2-to-1
multiplexers or b) two 4-to-1 multiplexers
Figure 3.67. Logic circuit
Figure 3.68. Comparator
Figure 3.69. a) BCD-to-7-segment decoder; b) display of numbers from 0 to 9
Figure 3.70. a) HEX-to-7-segment decoder; b) display of numbers from 0 to 9 and
letters A–F
Figure 3.71. Logic circuit 1
Figure 3.72. Logic circuit 2
Figure 3.73. Implementation of the logic function F
Figure 3.74. 4-to-1 multiplexer: a) logic circuit, b) truth table and c) Karnaugh maps
for the output Y
Figure 3.75. a) Karnaugh maps for F; b) logic circuit implementing F
Figure 3.76. 2-out-of-4 decoder
Figure 3.77. 1-to-4 demultiplexer
Figure 3.78. Logic circuit for the function F
Figure 3.79. Logic circuit
Figure 3.80. Implementation of F: a) Karnaugh map; b) logic circuit
Figure 3.81. Implementation of the logic function F
Figure 3.82. Multiplier for 2-bit words
Figure 3.83. Logic circuit of a comparator for 2-bit numbers
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Figure 3.84. Signal a:

Figure 3.85. Signal b:
Figure 3.86. Signal c:
Figure 3.87. Signal d:

Figure 3.88. Signal e:

Figure 3.89. Signal f:
Figure 3.90. Signal g:

Ndjountche, T. (2016). Digital electronics 1 : Combinational logic circuits. John Wiley & Sons, Incorporated.
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 Figure 3.91. BCD-to-7-segment decoder
Figure 3.92. Signal :
Figure 3.93. Signal
Figure 3.94. Signal
Figure 3.95. Signal
Figure 3.96. Signal :
Figure 3.97. Signal
Figure 3.98. Signal :
Figure 3.99. Signal :
Figure 3.100. HEX-to-7-segment decoder
4 Systematic Methods for the Simplification of Logic Functions
Figure 4.1. Karnaugh map for F (A, B, C, D)
Figure 4.2. Five-variable Karnaugh map: symmetrical presentation
Figure 4.3. Five-variable Karnaugh map: a) three-dimensional representation and b)
bidimensional and non-symmetrical representation
Figure 4.4. Example of loops in the case of a symmetrical map
Figure 4.5. Example of loops in the case of an asymmetrical map
Figure 4.6. Six-variable Karnaugh map: symmetrical structure
Figure 4.7. Six-variable Karnaugh map: stacked structure
Figure 4.8. a) Karnaugh map with two entered variables (x being a don’t care state);
b) Karnaugh map when x =1
Figure 4.9. Karnaugh map (x= 1) to determine the minimized product-of-sums form
Figure 4.10. Karnaugh map with two entered variables to determine the minimized
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sum-of-products form
Figure 4.11. Karnaugh map with two entered variables to determine the minimized
product-of-sums forms
Figure 4.12. Karnaugh map
Figure 4.13. a) Five-variable Karnaugh map and b) Karnaugh map with an entered
variable
Figure 4.14. Six-variable Karnaugh map
Figure 4.15. Karnaugh map with entered variables
Figure 4.16. Karnaugh map with entered variables

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 Figure 4.17. Karnaugh map for the logic function

Figure 4.18. Karnaugh map for the logic function

Figure 4.19. Karnaugh maps

Figure 4.20. Karnaugh maps
Figure 4.21. Karnaugh map
Figure 4.22. Karnaugh maps
Figure 4.23. Karnaugh maps
Figure 4.24. Karnaugh maps
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