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Asssignment - 2024 - 2025 - Solution

The document outlines the design of a simple computer system featuring an 8K RAM, 8K ROM, and I/O interfacing modules with a basic 16-bit CPU. It explains the architecture, including memory mapping, data flow operations, and the role of the system bus. Additionally, it discusses Direct Memory Access (DMA) as a method to enhance data transfer speeds by allowing peripherals to communicate directly with memory, bypassing the CPU for most operations.

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35 views6 pages

Asssignment - 2024 - 2025 - Solution

The document outlines the design of a simple computer system featuring an 8K RAM, 8K ROM, and I/O interfacing modules with a basic 16-bit CPU. It explains the architecture, including memory mapping, data flow operations, and the role of the system bus. Additionally, it discusses Direct Memory Access (DMA) as a method to enhance data transfer speeds by allowing peripherals to communicate directly with memory, bypassing the CPU for most operations.

Uploaded by

fasiro3794
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as RTF, PDF, TXT or read online on Scribd
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Department of Information Technology

Assignment
Date:24/10 /2024 Max. Marks: 20

Subject: LDCO Class: Second Year Sem-I

Q. 1 ) Design a relatively simple computer which incorporates 8KRAM, 8K ROM, IO interfacing modules
along with processor.
Ans : Designing a simple computer system incorporating 8K RAM, 8K ROM, I/O interfacing
modules, and a processor involves outlining the architecture, key components, and the
interaction between these components. Here's a high-level design:

1. Processor (Central Processing Unit - CPU):

The CPU is the heart of the system. It fetches instructions from memory (RAM/ROM), decodes
them, and executes them. In this system, we'll assume a basic 16-bit processor for simplicity.

 Registers: Include general-purpose registers, accumulator, program counter (PC), instruction


register (IR), and a stack pointer.
 Data Bus: 16-bit wide for data transfer between the processor and memory.
 Address Bus: 16-bit wide, allowing addressing up to 64KB (enough for 8K RAM and 8K ROM).
 Control Unit: Manages the flow of data between CPU, memory, and I/O.

2. Memory (8K RAM and 8K ROM):

The system uses two types of memory: RAM (Random Access Memory) for read/write
operations and ROM (Read-Only Memory) for permanent data storage.

 RAM: 8K RAM (8192 bytes) located in a specific address range, say from 0x2000 to 0x3FFF.
 ROM: 8K ROM (8192 bytes) for storing bootloader, firmware, or initial instructions, located from
0x0000 to 0x1FFF.

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3. I/O Interfacing Modules:

The system needs Input/Output modules for communication with external peripherals such as
keyboards, displays, or other devices.

 I/O Mapped Ports: Allocate specific address ranges for I/O devices, say 0x4000 to 0x40FF.
 Memory Mapped I/O: Use part of the memory address space to control I/O modules.
 Interrupt Mechanism: Provide interrupt handling for I/O devices to allow efficient data
exchange.

4. System Bus:

The bus connects the CPU, memory, and I/O devices to transfer data, addresses, and control
signals.

 Address Bus: 16-bit wide, carrying memory addresses from CPU to RAM, ROM, and I/O.
 Data Bus: 16-bit wide, carrying data between CPU, memory, and I/O.
 Control Bus: Carries control signals such as Read/Write, Interrupt, Reset, etc.

5. Clock Generator:

Generates a clock signal to synchronize all operations of the system, including CPU cycles and
data transfers.

6. Power Supply:

A simple 5V power supply for the entire system.


Memory and I/O Address Mapping:
Component Address Range
ROM 0x0000 - 0x1FFF
RAM 0x2000 - 0x3FFF
I/O 0x4000 - 0x40FF

Flow of Operations:

1. Power On: Upon startup, the CPU fetches the first instruction from ROM at address 0x0000
(usually a bootloader or firmware).
2. Instruction Fetch-Decode-Execute: The CPU continuously fetches instructions from memory,
decodes them, and executes them.
3. RAM Interaction: For any data read/write operations, the CPU accesses RAM.
4. I/O Interaction: The CPU accesses I/O devices by either directly reading/writing to specific
memory-mapped I/O addresses or using interrupts.
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Memory and I/O Address Mapping:

+----------------------+

| Processor |

| +------------------+ |

| | Control Unit | |

| | Arithmetic Logic | |

| | Unit (ALU) | |

| +------------------+ |

+----------------------+

| | |

| | |

+----+----+----+------+

| Address | Data Bus |

| Bus | |

+----------+-----------+

| |

+---------+ +---------+ +-------------------+

| ROM | | RAM | | I/O Interface |

| (8K) | | (8K) | | (Keyboard, UART, |


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| 0x0000 | | 0x2000 | | Display, etc.) |

+---------+ +---------+ +-------------------+

| Address: 0x4000-0x40FF

+------------------------------------------------+

This design is a basic representation of a simple computer that integrates 8K RAM, 8K ROM, and basic
I/O interfacing with a processor.

Q. 2) Elaborate how DMA bypasses CPU and speeds up the memory operation?

Ans : Direct Memory Access (DMA) is a technique used to transfer data directly between
memory and peripherals (or between two memory locations) without the direct intervention of
the CPU. It significantly improves data transfer speeds and efficiency by allowing peripheral
devices to directly read from or write to memory, bypassing the CPU for most of the data
movement. Here's how it works and how it speeds up memory operations:

1. Traditional Data Transfer with CPU:

In a typical system without DMA, the CPU plays a central role in moving data between I/O
devices and memory. For example, when data needs to be transferred between a disk and RAM:
1. The I/O device (e.g., a hard disk) sends an interrupt to the CPU indicating that data is ready to be
transferred.
2. The CPU responds to the interrupt and executes a series of instructions to read data from the I/O
device.
3. The CPU then temporarily stores the data in one of its registers.
4. Afterward, the CPU writes the data from the register to the memory.
5. The process repeats for each block of data being transferred.

This CPU-driven transfer process is relatively slow because the CPU is involved in every step
of the transfer. For large amounts of data, the CPU must repeatedly issue read and write
commands, which consumes significant processing time.

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2. How DMA Works:

With DMA, the CPU is almost entirely bypassed during the data transfer process, except for
initiating and concluding the transfer. Here’s how it works:

Steps in a DMA Data Transfer:


1. DMA Controller Setup:
o The CPU programs the DMA controller by providing it with:
 The source address (memory or I/O device).
 The destination address (memory or I/O device).
 The size of the data to transfer.
 The transfer mode (read from or write to memory).
o After setting up the DMA controller, the CPU can return to performing other tasks,
freeing up its resources.
2. DMA Operation:
o The DMA controller takes over control of the system's address bus, data bus, and
control bus.
o The DMA controller directly transfers data between the source (e.g., an I/O device) and
the destination (e.g., memory) without involving the CPU in each data movement step.
o During the transfer, the DMA controller interacts with both the memory and the I/O
device, taking the data from one and writing it to the other.
3. Completion:
o Once the transfer is complete, the DMA controller raises an interrupt to notify the CPU
that the operation has finished.
o The CPU can then continue interacting with the data if necessary, without having spent
time directly managing the data transfer.

3. Types of DMA Operations:

There are different modes of DMA operation, which impact how the CPU is involved during the
data transfer:

 Burst Mode (Block Transfer):


o The DMA controller transfers the entire block of data in one go, while the CPU is halted
during the transfer. This method is fast but temporarily "freezes" the CPU.
 Cycle Stealing Mode:
o The DMA controller takes control of the bus for a few clock cycles at a time, transferring
one word of data. After the transfer, the CPU is allowed to use the bus again. This allows
the CPU to continue operating, but at a slightly reduced speed. It "steals" bus cycles
when needed, hence the name.

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 Transparent Mode:
o DMA transfers data only when the CPU is not using the bus, making it the least intrusive
but also slower, as it waits for idle CPU time.

4. Advantages of DMA:

 Reduced CPU Overhead:


o Since the CPU is not involved in the actual data transfer, it can focus on other processing
tasks. This frees up the CPU to handle more complex tasks or run other programs.
 Faster Data Transfers:
o Data can be moved in larger blocks at once (especially in burst mode), significantly
speeding up the transfer process compared to CPU-driven methods, where data is
moved word

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