A Comprehensive Analysis on Comparator,

Encoder Circuit to Develop Flash Type ADC Based

on Different Implementation Routes
Indranil Maity Suvojit Maity Siddhartha Bhattacharya
Department of Electronics and Department of Electronics and Department of Electronics and
Communication Engineering (ECE) Communication Engineering (ECE) Communication Engineering (ECE)
Institute of Engineering and Institute of Engineering and Institute of Engineering and
Management (IEM), Kolkata Management (IEM) Management (IEM)
University of Engineering Kolkata, West Bengal, India Kolkata, West Bengal, India
and Management (UEM) E-mail: [email protected] E-mail: [email protected]
Kolkata, West Bengal, India
E-mail: [email protected]

Abstract— The present paper describes the design and than others, although optimization of different comparator
performance evaluation of two different flash-type analog-to- and encoder circuits can reduce the power dissipation.
digital converter (ADC) circuits, targeting applications towards Analog-to-digital converters (ADCs) are a crucial part of
high speed and low power consumption. The first considered
analog-to-digital communication blocks in addition to digital
flash-type ADC circuit comprised of a sample and hold circuit
signal processing systems [5]. The flash type ADC is highly
2024 IEEE Silchar Subsection Conference (SILCON) | 979-8-3315-4082-1/24/$31.00 ©2024 IEEE | DOI: 10.1109/SILCON63976.2024.10910918

(that is common for both the ADCs), clamped push-pull output

comparator, and 8:3-bit priority encoder made up via favourable in vital applications such as high-speed
employing basic logic gates (Case 1). The second flash-type ADC applications like satellite communications, low power or low
circuit comprised of an open-loop two-stage comparator, and an voltage applications and other wideband or radar
8:3-bit priority encoder circuit made up using basic logic gates applications, because of its exceptional speed and efficiency.
(Case 2). Throughout the analysis, evaluations of power The flash ADC functions in parallel, in contrast to traditional
consumption, propagation delay, and noise properties were ADCs, allowing for the quick alteration of analog impulses
investigated. The circuits were simulated in Cadence Virtuoso into digital form in a single clock cycle [6-7]. The flash ADC
platform (v 6.1.5) with 90nm CMOS technology. The power
is the best alter for applications, where speed and efficiency
consumption was found to be 31.47mW for Case 1, while in Case
2, it was 31.53mW. In addition, propagation delay and noise are crucial because of its significant reduction in conversion
analysis were also carried out for a comparative study between time and power consumption due to its simultaneous
the two cases. operation. The flash ADC is therefore positioned as a key
component in the contemporary communication systems due
Keywords—Clamped push-pull output comparator, two-stage to its unique architecture and performance benefits [8-9].
open-loop comparator, priority encoder, sample and hold circuit, In their experimental endeavor, Kumary et al. [1] focused on
flash-type ADC. designing a comparator and decoder to reduce power
I. INTRODUCTION consumption with 0.9mW in flash ADCs and also improve
the linearity, size reduction, and performance of ADCs. On
There are various applications of analog-to-digital the other hand, Mendonca et al. [2] addressed the challenges
converters (ADC circuits) in engineering domains, as it is in SAR ADCs for biomedical applications, and also focused
essential to develop different design architectures of ADC to on improving sampling rate and precision through optimized
tackle all such applications. All the sensors operate with DAC and comparator designs. Khatun et al. [3] introduced a
analog values, so data converters from analog to digital are high-frequency isolated current-fed push-pull converter with
crucial in the conversion of signals into digital form or vice zero current switching, employing small-signal modeling and
versa in concrete applications [1]. In the present time, SAR closed-loop control design for transient performance
ADC is excessively used in various biomedical applications checking. Chen et al. [4] reviewed various ADC architectures
due to its lower power consumption rate as it can avoid higher for ultrasonic imaging systems, comparing SAR, sigma-
energy-consuming Op-amp (operational amplifiers) [2]. In delta, pipelined, and hybrid ADCs, and discussed their
the application of ultrasonic image systems, different kinds performance, and challenges. Kumar et al. [5] designed a 4-
of ADC in the VLSI domain [3] have been used and bit flash ADC using transistor inverter quantization (TIQ)
performance has been compared for each type [4]. ADCs also comparator for improved efficiency. Esmailiyan et al. [6]
have applications in the wideband or radar domain. To fulfill introduced a time mode flash ADC of power consumption of
the demand for ADC circuits in various domains, different 88µW with Dickson-charge-pump-based comparator.
kinds of ADCs have been made like successive Soumya et al. [7] analyzed efficient modular adder designs
approximation ADC, sigma-delta ADC, dual slope ADC, using thermometer to binary encoding, focusing on
counter type ADC etc. Every kind has its benefits and improving performance metrics like speed, power
drawbacks. For high-speed applications, flash-type ADC is consumption, and area efficiency. Ray et al. [8] proposed a
the suitable one but it has a higher power consumption rate

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 Fig. 1. Block diagram of flash-type analog-to-digital converter (ADC) circuit

multiplexer-centered thermometer to binary encoder for a 4-

bit flash ADC. Datta et al. [9] presented a Wallace tree
encoder designed to convert thermometer code to binary code
for a 4-bit flash ADC. Maity et al. [10] computed different
topological configurations of current mirror and compared
them based on gain, noise, and power consumption. Oh et al.
[11] introduced a dynamic flash-type ADC with offset
calibration for incorporating voltage-time converters.
Chinthala et al. [12] recommended a flash type ADC circuit
for high amount of data transfer. Maity et al. [13] performed
simulations on different universal logic gates in cadence
virtuoso platform. Scott et al. [14] proposed a flash-type
digital-to-analog converter circuit for low-power
applications. Halim et al. [15] compared between different
comparator and encoder circuits for 4-bit flash-ADC. Fig. 2. Schematic circuit diagram of the sample and hold circuit
Recently, Zheng et al. [16] reviewed various schemes for made in cadence virtuoso
enhancing the resolution of ADCs. Lim et al. [17] presented a in the platform. On the other hand, in case 1 and 2, the 8:3-bit
technique for enhancing open-loop sample-and-hold circuit priority encoder circuit is made up of basic logic gates like
precision. Mashhadi et al. [18] analyzed delay, derived multiple input AND gate, OR gate and NOT gate.
analytical expressions of a dynamic comparator and proposed The above-mentioned basic gates are made up of CMOS
a modified low-power, high-speed comparator design. logic in the cadence-virtuoso platform. Though flash-type
The present work aims to find out the optimized structure of ADCs have a high-power consumption rate, they have mostly
a flash-type ADC concerning the power consumption, been used due to their high-speed operation, particularly in
propagation delay and noise margin with the deviation in the applications of ultrasonic-image systems, various sensor
frequency of analog input signal by interchanging the applications, wideband radar applications and biomedical
comparator, and encoder block in two cases of flash-type applications [1-2, 4]. It has three major parts by which analog
ADC circuits. The first considered flash-type ADC circuit signals can be changed into digital signals using digital binary
was made up of a sample and hold circuit that is common for bits. In Fig. 1, the basic block diagram of a flash-type analog-
both the two ADCs, a clamped push-pull output comparator to-digital converter circuit has been designed, where the
and a 8:3-bit priority encoder made up employing basic logic analog data input is converted to the 3-bit binary values
gates like AND gate, OR gate and NOT gate (Case 1). While, namely A, B and C, where, A bit acts as the most significant
the second flash-type ADC circuit was made up of an open- bit (MSB) and C bit acts as the least significant bit (LSB).
loop two-stage comparator and an 8:3-bit priority encoder With the help of these three binary bits, the analog input
circuit made using basic logic gates, as mentioned above waveform has been modified into the digital output waveform
(Case 2). The circuits were simulated in cadence virtuoso (v i.e., the binary value of the analog data input signal. Sample
6.1.5) with 90nm CMOS technology and a 1V supply and hold block present in all the flash-type analog-to-digital
voltage. converter circuits have been analyzed in this paper. This
block is much-needed and the most important one in the type
II. SIMULATION AND ANALYSIS
of ADC circuits, as it removes the sudden fluctuations in the
Power consumption calculation, noise analysis, and input analog signal, so that it can be converted easily into the
propagation delay of two different flash-type ADC circuits binary form. The analog input signal was preliminarily
were studied by using the Cadence Virtuoso tool (v 6.5.1). quantized by the sample and hold circuit by removing the
The considered architecture of the flash-type ADC circuit sudden fluctuations from the signal. The task was easier to
was made of a sample and hold (track and hold) circuit, a modify the quantized signal into digital form by this circuit.
comparator block and an encoder circuit as shown in Fig. 1. This track and hold circuit can be made up of various methods
In case 1 of flash-type ADC discussed in this paper, the using different components. In this paper, it has been made
comparator circuit is clamped push-pull output comparator up of an NMOS [10] having a total width of 120nm and
while, in case 2 that is two-stage open loop comparator, both length of 100nm and a capacitor of capacitance 10nF with
made up using CMOS technology, where the width to length sampling frequency 1KHz was demonstrated in Fig. 2 [11].
ratio for every PMOS or NMOS transistor is tuned as needed

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 Fig. 3. Schematic circuit diagram of the clamped push-pull output comparator made in cadence virtuoso (Case 1)
For generating the input signals in the form of pulse voltage was designed using CMOS technology varying the W/L ratio
source (means logic high and logic low) for the 8:3-bit of every PMOS and NMOS as needed, the aspect ratio of the
priority encoder circuit, seven comparator blocks were PMOS (M3 and M4) is 4.5µm/1µm, while the W/L ratio of
joined parallelly from which the output has been generated in the M6 PMOS is 38µm/1µm, and for PMOS M8 it is
the manner of pulse voltage source and this developed 4.5µm/1µm. On the other hand, the aspect ratio of the NMOS
output was worked as the input of the priority encoder circuit (M1 and M2) is 3µm/1µm, while for NMOS M5 and M9, it
(port D1 to D7, as mentioned in the priority encoder circuit is 4.5µm/1µm, and for NMOS M7 it is 35µm/1µm. The DC
part), which in turn generates binary bits from the encoder. current source used in the circuit is 10µA [12-14]. The second
In this paper, two types of comparator circuits have been comparator is a two-stage, open-loop comparator, as shown
made and analyzed in cadence virtuoso to develop the whole in Fig. 4, whose design is mostly similar to the two-stage,
flash-type ADC architecture. The clamped push-pull operational amplifier. It was designed using CMOS
comparator offers high speed and strong drive, but consumes technology varying the aspect ratio of every PMOS and
more power. On the other hand, the two-stage open-loop NMOS as needed, the W/L ratio of the PMOS (M3 and M4)
comparator provides better gain and noise immunity, is 4.5µm/1µm, while the W/L ratio of the M6 PMOS is
operates at low power, and may be slower. Both the types 38µm/1µm. On the other hand, the aspect ratio of the NMOS
were chosen here for their balance of speed, power (M1 and M2) is 3µm/1µm, while for NMOS M5 and M8, it
efficiency, and simplicity, making them suitable for high- is 4.5µm/1µm, and for NMOS M7 it is 35µm/1µm. The DC
speed, high-resolution Flash ADCs. The first comparator is current source used in the circuit is 30µA [15-16].
a clamped push-pull output comparator shown in Fig. 3. It

Fig. 4. Schematic circuit diagram of the two-stage open-loop comparator made in cadence virtuoso (Case 2)

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For generating the binary bits (A, B and C) corresponding to A = D4+D5+D6+D7
the input analog signal for the flash-type ADC block, an
B = (D2+D3) D4' D5'+D6+D7
encoder block is needed, which converts the comparator-
generated pulse signal into the corresponding binary number. C = [D1D2' D3' D4'+D3D4'+D5] D6'+D7
In this study, priority encoder circuit have been made and V = D0+D1+D2+D3+D4+D5+D6+D7
analysed in cadence virtuoso to develop the whole flash-type
ADC architecture. expressed above by which the thermometer code is
An 8-bit to 3-bit priority encoder was made using basic logic transferred into binary numbers. In a priority encoder, if more
gates within the cadence virtuoso environment, shown in Fig. than one input is active, the output will represent the highest-
5. The whole design process involves a meticulous process numbered active input. For instance, if inputs D7 to D0 are
of circuit design and simulation. In digital systems, the present, and both D2 and D1 are active, the output will
priority encoder outputs the binary code of the highest represent D2, as it has a higher priority [9]. The logic for this
priority input line that is currently in use. An 8-to-3-bit encoder can be expressed using boolean algebra, and the
priority encoder translates eight input lines into three output corresponding logic diagram can be meticulously crafted
lines, with the output line representing the input line with the using the gates mentioned. To confirm the circuit's operation,
highest order of precedence. With cadence virtuoso, the simulations were done. With the tools provided by cadence
design process began with the schematic capture, in which virtuoso, designers can test their circuits under a variety of
the encoder circuit was formed by connecting logic gates. scenarios and make sure they function as intended. The
The three fundamental gates that make up a digital circuit are outcomes of the simulation aid in verifying the priority
AND, OR, and NOT gates. To make sure that in the priority encoder's truth table, guaranteeing that the highest priority
encoder, while many inputs are active, only the input with the input is accurately encoded into a 3-bit binary output.
highest priority is taken into the account, multi-input AND In Fig. 6 the working principle of a flash-type analog-to-
gates were employed. NOT gates were used to invert signals digital converter has been demonstrated without considering
when needed, OR gates combined the outputs of the AND the type of comparator and encoder used in the circuit to
gates. Mathematical expressions for every binary bit are check the results at a specific time instant, when the signal

Fig. 5. Schematic circuit diagram of the 8:3-bit priority encoder made using logic gates in cadence virtuoso

Fig. 6. General schematic diagram of the flash-type ADC circuit

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voltage is 0.8 times of the reference voltage, which is a is preferable compared to the first one. Noise margin is also
constant DC voltage. As, for every type of comparator block an important factor in analyzing the performance of any
like two-stage open-loop comparator or clamped push-pull circuit. It depicts how much the circuit is perfect to
output comparator and for every priority encoder made by demonstrate the output from the input signal in the
any means, the working principle of the flash-type ADC interference of noise.
remains the same. Now, the analog input signal having III. RESULT AND DISCUSSION
amplitude 2.5V (full swing is 5V) and 500Hz frequency has
passed through the sample and hold circuit. The output The power consumption of the flash-type ADC (case 1)
waveform from the sample and hold circuit is gone into one and flash-type ADC (case 2) obtained are as follows:
of the inputports of every comparator joining in parallel and 31.47mW and 31.53mW respectively. The power
the other input port is filled with the reference voltage, which consumption of the flash ADCs has been calculated in the
is divided at every comparator using a certain value of resistor Cadence Virtuoso platform using the calculator tool from the
by the voltage divider rule. Applied 5V reference voltage is power graph by using the average function from the function
divided at the ports a, b, c, d, e, f, and g. At port a, the voltage panel in the tool, of that particular circuit. The propagation
is 7/8Vref, at port b, that is 6/8Vref. In that way, at port g, the delay also has been calculated using the delay function in the
voltage is 1/8Vref. So, all the comparator gives the output as cadence virtuoso platform in the calculator tool for every
logic low (0) except the topmost comparator in Fig. 6. It gives flash-ADC circuit. Noise analysis also has been done in the
high logic (1). Now, the generated thermometer code by the cadence platform using the noise analysis tool. Flash ADCs
comparator block generates the binary bits after the priority are extremely fast but come with limitations such as high-
encoder block. A thermometer code is a unary code for power consumption, exponential circuit complexity, and
integers in which each successive digit is a 1. Thus, the limited resolution (typically up to 8 bits). Even, comparator
number 3's thermometer code is “1110”. It is often used in mismatch and high input capacitance also affect accuracy and
applications involving gradual changes in value. The output speed.
port V is the indication bit that is if anyone of the input ports A. Flash-type ADC-I (Case-1)
of the encoder block is at logic high, then only the outport V
In this type of flash analog-to-digital converter, a sample and
gives logic high value, otherwise it gives logic low value [17].
hold circuit, a clamped push-pull output comparator and a
Propagation delay, power consumption and noise analysis
priority encoder made using basic logic gates like multi-input
have been done for the above-mentioned two types of flash
AND, OR and NOT gates have been used to design. In Fig.
ADC circuits to analyse the performances of these circuits.
7, the output binary bits (A, B and C) against the sinusoidal
Propagation delay = ½ {(propagation delay for the signal
input signal having 2.5V amplitude and 500Hz frequency
goes high to low) + (propagation delay for the signal goes low
have been shown. The analog-to-digital converter (Case-1)
to high)}. Power consumption is also one of the most
has been simulated for 20ms. There 2 binary stages or
important parameters to judge any circuit based on its
numbers have been detected i.e. 000 and 111. For high values
performance. If any circuit consumes more power than the
of analog signal, it gave the value 111, and for low values it
other circuit of the same functionality, then the second circuit
gave 000.

Fig. 7. Transient analysis output of the flash-type ADC-I (Case 1)

Fig. 8. Transient analysis output of the flash-type ADC-II (Case 2)

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B. Flash-type ADC-II (Case-2) power consumption was carried out and found to be 31.47mW
In this type of flash analog-to-digital converter, a sample and for case 1, while in case 2 it was 31.53mW. The noise analysis
hold circuit, a two-stage, open-loop comparator and an 8:3-bit of the circuits has also been performed and the respective
priority encoder made up using basic logic gates like multi- parameters have been computed.
input AND, OR and NOT gates, have been used to design. In
Fig. 8, the output binary bits (A, B and C) against the ACKNOWLEDGMENT
sinusoidal input signal having 2.5V amplitude and 500Hz We extend our appreciation to the Institute of
frequency have been shown. The analog-to-digital converter Engineering and Management (IEM), Kolkata for providing a
(Case-2) has been simulated for 20ms. There 2 binary stages conducive environment for academic exploration and
or numbers have been detected 001 and 110. For high values fostering an atmosphere of learning.
of analog signal, it gave the value as a pattern of 110 and for
low values, it gave 001 pattern. REFERENCES
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