2024 5th International Conference for Emerging Technology (INCET)

Karnataka, India. May 24-26, 2024

3-bit Flash ADC Using TIQ Comparator

Laxmi Koutanali Sujata S Kotabagi Ritu Vernekar
School of Electronics and School of Electronics and School of Electronics and
Communication Engineering Communication Engineering Communication Engineering
KLE Technological University KLE Technological University KLE Technological University
Hubli, India Hubli, India Hubli, India
[email protected] [email protected] [email protected]

Vijeta D Chitragar Prajwal Sangalad

School of Electronics and School of Electronics and
Communication Engineering Communication Engineering
KLE Technological University KLE Technological University
2024 5th International Conference for Emerging Technology (INCET) | 979-8-3503-6115-5/24/$31.00 ©2024 IEEE | DOI: 10.1109/INCET61516.2024.10593264

Hubli, India Hubli, India

[email protected] [email protected]

Abstract—High speed and low power consumption are criti- • The comparator’s output is in the high state when the
cal requirements for many applications of an analog-to-digital voltage at the non-inverting input (+) is greater than
converter (ADC). Implementing flash ADC, the fastest available the voltage at the inverting input (−); this is commonly
ADC type, requires a significant amount of (Integrated Circuit)IC
real estate. Significant disadvantages include its high power and represented as logic level “1” or the supply voltage.
area requirements. Threshold Inverter Quantization (TIQ) is • On the other hand, the comparator’s output is in a low
a comparator that can be used to get around this problem. state (often denoted by logic level “0” or ground) if the
Using two cascading inverters as a voltage comparator gives this voltage at the inverting input (−) is greater than the
technique its name. Internal reference voltages are compared voltage at the non-inverting input (+).
with the input voltage, which depends on the transistor sizes of
the inverters. The priority encoder gives the digital output based In many electronic applications that call for circuits capable
on the highest order active input, ignoring all other active input. of making decisions, such as ADCs, comparators are used to
While TIQ is not as fast as Flash ADC, its small size and power calculate the bit value of each step in the digitization process.
efficiency make it a worthy replacement in situations where every Additional uses include signal conditioning in different forms,
milliwatt and square millimeter counts. The design structures are
relaxation oscillators, pulse production, and voltage level sens-
stimulated using CMOS 180nm technology which uses a Vdd of
1.8V and has a power consumption of 26.39 (μW) with a delay ing.
of 32.96(μs).
Index Terms—ADC, TIQ, Cascading Inverter, Priority En-
coder, Internal Reference Voltage.

I. I NTRODUCTION

Every signal found in nature is an analog signal. An analog

signal is a time-varying signal, so it is more difficult to work
with an analog signal than a digital signal. To convert analog
signal to digital signal ADC plays an important role. Flash
ADC is the fastest way to convert analog signals to digital Fig. 1. Symbol of a Comparator
signals. A Flash ADC is the specific type known for its high
speed and parallel architecture. A flash ADC has two basic Comparators can be implemented using dedicated com-
building blocks: comparators and encoders. parator Integrated Circuits (ICs). These ICs are optimized
A comparator is an electrical circuit that determines which for this specific application and offer benefits in terms of
of two voltages or currents is larger by comparing them and speed, precision, and energy efficiency. Some options for
producing a digital signal. It contains one digital output and comparators include a two-stage open loop comparator, TIQ
two input terminals, called the inverting input (−) and the comparator, quantized differential comparator, and CMOS-
non-inverting input (+). A comparator’s primary purpose can LTE (low threshold voltage); however, since the TIQ com-
be summed up as follows: parator has a transistor count of four [3], it requires less area
and power than the two-stage open loop comparator, quantized
differential comparator, and CMOS-LTE, which have more

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transistor counts, namely seven, seven, and six, respectively. The Two-Stage Open-Loop Comparator, the TIQ Com-
Open loop flash ADC uses a resistor ladder network to provide parator, and the Quantized Differential Comparator are three
the reference voltage but not in the TIQ comparator. Two notable architectures in comparator design[3]. The Two-Stage
cascading CMOS investors were used to design the TIQ Open-Loop design, which is characterized by its multiple
comparator. amplifier stages in an open-loop configuration, functions by
An analog input voltage can be converted into a 3-bit amplifying the input signal through the first stage and adding
digital representation using a basic digital circuit called a 3-bit additional gain via the second stage to drive the output. Since
flash ADC, which uses TIQ comparators. A comparator array the amplifiers in this architecture are operating continuously,
usually consists of (2n − 1) comparators. A set of threshold they can draw moderate to high power. This is useful for
voltages that are generated as references and equally separated applications that require quick response times, including signal
from each other are compared to the analog input voltage. processing or high-speed data communication. The footprint
In Fig 2 TIQ Comparator, compares input voltages(vin ) with of the Two-Stage Open-Loop Comparator is usually moderate
internal reference voltages(vref ) if vin ≥ vref gives logic 1 when it comes to silicon space.
otherwise logic 0. Two cascading CMOS invertors in which On the other hand, each inverter stage of the TIQ Com-
the first invertor is used to set the reference volage of the parator flips its output at a particular threshold voltage. This
comparator which can be by varying the width of the N- is because the comparator uses cascaded inverters. One special
mos and P-mos transistors and the second invertor is used benefit of low power consumption is that the number of
to increase the gain of the comparator. By dividing the input inverters that switch determines the resulting digital output.
range into intervals that are equally spaced apart, this output Because of its energy-efficient architecture, the TIQ Com-
divides the analog voltage into seven different levels. Control parator is a preferred option for applications where power
systems, digital sensors, and audio processing are among efficiency is a top priority, such as Internet of Things(IoT)
the applications that benefit from 3-bit ADCs’ quick and sensors or battery-operated devices[4]. Furthermore, the TIQ
effective performance at the expense of resolution. These Comparator has a relatively minimal silicon area need, which
applications prioritize low power consumption, affordability, makes it appropriate for integrated circuit designs that have
and simplicity. spatial constraints. The TIQ Comparator is a flexible choice
for a range of applications that do not require ultra-high-speed
A. Objectives performance, even if it is not the quickest comparator type[5].
It offers a respectable speed.
The objective is to create a Flash ADC that is small in size,
The Quantized Differential Comparator, in conclusion, func-
stable, reliable, fast in converting analog signals to digital,
tions based on the idea that a differential pair of transistors
accurate in signal processing, and helpful in a variety of
compares a quantized input voltage to the opposite bias
industries, including instrumentation, telecommunication, and
voltages. For applications requiring precision, this architec-
signal processing.
ture—which provides moderate to quick response times—is
II. L ITERATURE S URVEY frequently chosen. In precise settings like measurement de-
vices and instrumentation, where linearity and accuracy are
Comparators and encoders are the two main components critical factors, the Quantized Differential Comparator finds
of flash ADCs, which are essential for high-speed analog-to- its application. It consumes a moderate amount of power and
digital conversion. Comparators are the main decision-makers; occupies a silicon area comparable to that of the Two-Stage
they generate digital output by comparing the input voltage Open-Loop Comparator. Selecting one of these three compara-
with a reference voltage. These outputs are processed by tor architectures essentially comes down to the particular needs
encoders to produce the final digital output. of the application, be they low power consumption, high speed
Two main categories of comparators are Open-Loop and operation, effective silicon area utilization, or precise signal
Dynamic. Due to their set gains, Open-Loop comparators comparison. With unique benefits suited to different target
are not as appropriate for sensitive applications. Furthermore, applications, each architecture presents a range of options in
they react to varying input voltages with slower response the field of comparator design.
times. However, because of their complex designs and the The trade-off between resolution and power efficiency is a
potential for clock signal errors to affect performance, dynamic significant feature of ADC design. More power is typically
comparators, which depend on clock signals for operation, used by traditional Flash ADCs, which frequently use resistor
provide slower responses[1]. ladder networks for reference voltage[6]. However, by avoid-
Various comparator designs meet particular requirements. ing the requirement for such networks, the TIQ Comparator
The TIQ Comparator is a notable device that boasts lower provides an energy-efficient substitute. Furthermore, after 8
power consumption than its predecessors, whereas the CMOS- bits of resolution, Flash ADC efficiency reaches a limit due to
LTE Comparator prioritizes low power consumption and quick the required number of comparators (2n − 1) , which presents
operations[2]. Comparing quantized input voltages to opposing difficulties for power optimization[7].
bias voltages, the Quantized Differential Comparator is well- Basically, the choice of comparator type greatly affects
known for its accuracy in low-power, high-speed Flash ADCs. the entire functionality of a Flash ADC system, determining

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factors like speed, resolution, and power consumption[8].
The spectrum of comparator options—from Open-Loop to
Dynamic, TIQ, Quantized Differential, and specialized am-
plifier designs—offers a range of trade-offs, emphasizing the
complex trade-off between power efficiency and resolution
demands in the implementation of ADCs[3].

III. M ETHODOLOGY
TIQ is a novel approach to Flash ADC architecture that
provides a more compact and power-efficient solution than the
conventional resistor ladder-based methods. Power-hungry re-
sistor networks are not necessary with TIQ comparators since
they use cascaded inverters that switch at certain threshold
voltages. This significantly lowers the number of components
and, thus, power consumption. Because of its larger in-
put/output swing ratio and smaller silicon footprint, this simple
design is perfect for highly integrated circuits. It also improves Fig. 3. TIQ Comparator Block
precision. TIQ-based Flash ADCs so stand out in industries
like signal processing and telecommunications as excellent
options for applications requiring accuracy, efficiency, and Next, a priority encoder receives the outputs from these
downsizing. comparators. Because it guarantees that only the comparator
with the greatest priority—that is, the comparator with the
highest trigger voltage that trips—is taken into account in
situations where several comparators may trip as a result of
the input voltage being above their thresholds, this priority
encoder is essential. The priority encoder converts the outputs
from the comparators into a 3-bit digital code. The analog
input signal is efficiently converted into an accurate digital
representation by this digital code, which corresponds to the
most significant comparator that has triggered.
Switch point can be mathematically calculated as

K
(Vdd − Vtp ) Knp + Vtn
Vs =  (1)
K
1 + Knp

where
- Vs : Switching Voltage
Fig. 2. TIQ Comparator Design - Vdd : Supply Voltage
- Vtp : PMOS Threshold Voltage
- Vtn : NMOS Threshold Voltage
A. Threshold Voltage - Kp : Proportional Constant for PMOS, defined as μp Wp
Seven comparators serve as the central component of the - Kn : Proportional Constant for NMOS, defined as μn Wn
TIQ method used in this three-bit ADC system. A distinct - μp : Mobility of holes
”trigger voltage” that varies from 0.3V to 1.5V is built into - μn : Mobility of electrons
every comparator. By altering each comparator’s transistor - Wp : Width of PMOS
ratio, this range is created, allowing the comparators to trip - Wn : Width of NMOS
at these preset voltage levels.
This ADC compares an analog signal applied to it simul- By calculating reference voltages obtained voltages are
taneously with the trigger voltages of all seven comparators. 0.3V, 0.4V, 0.66V, 0.91V, 1.19V, 1.4V, and 1.7V.
The theory behind this is that when the input voltage rises None of the comparators would trip if the input voltage fell
beyond a given threshold, each comparator will ”trip” or react. below the lowest trigger voltage (0.3V in this configuration).
The highest priority signal is represented by the comparator In order to solve this, the system is configured such that, in the
with the highest trigger voltage that still trips; this effectively event that the input voltage falls below the ADC’s detectable
quantizes the analog input into a digital value dependent on range, all comparators will output the default digital value of
which comparator reacts first. 000.

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B. Priority Encoder
A priority encoder is a particular kind of digital circuit
designed to overcome a significant drawback of standard
digital encoders: their incapacity to process several high inputs
at once. By ranking its inputs in order of significance, a priority
encoder effectively eliminates the ambiguity that arises when
many inputs are active, unlike conventional digital encoders
that may provide incorrect outputs.

Fig. 5. Block Diagram

Fig. 4. Priority encoder Design

It functions according to the idea that only the active

input with the highest priority is taken into account while
producing the output, hence disregarding any signals with a
lower priority.
Typically, a combinational logic circuit has 2n input lines
and n output lines. The bit count required to encode the
highest-priority input is denoted by n. The priority encoder
chooses the input with the highest precedence as specified Fig. 6. Truth Table for 3-bit ADC
in its design when numerous inputs are active at once and
encodes that input into the output. Because of this feature,
priority encoders are especially helpful in systems that need est threshold voltage that was surpassed to handle situations
to determine which of multiple simultaneous inputs is the most where multiple comparators are triggered.
urgent. An example of such a system would be a computer’s Because it is the closest approximation to the actual mag-
interrupt controller, which must handle the most important nitude of the input voltage, this choice is critical. After that,
interrupt first. the priority encoder converts this selection into a digital code,
giving the analog input a digital representation. This accurate
C. Implementation and effective conversion procedure ends the conversion cycle
The processes outlined below show how an analog input by preserving the substance of the analog signal in a digital
signal is transformed into a digital output utilizing a sequence format that may be used for additional electronic processing
of comparators and a priority encoder. This process is com- or analysis.
monly carried out in the context of an ADC that makes use
IV. R ESULTS
of comparator TIQ comparators.
Using a sequence of comparators and a priority encoder, A Flash ADC that uses a TIQ comparator has many benefits
the procedure is a simplified way to transform an analog over conventional open-loop comparator designs. Better power
signal into a digital format. TIQ comparators are frequently economy, faster processing, and less silicon space are all ben-
used in ADCs. First, the analog input is sent through several efits of the TIQ design. Since TIQ comparators have intrinsic
comparators, each of which is configured to trip at a different design features that reduce power consumption, they are the
voltage threshold. When the conditions are satisfied, each of best choice for energy-sensitive applications when compared
these comparators generates a high signal. They all evaluate to traditional open-loop comparators. TIQ comparators also
if the input exceeds their respective thresholds concurrently. guarantee high-speed analog-to-digital conversion due to the
Next, all comparator outputs are supplied into a priority use of cascaded inverters, which enable quick response inter-
encoder, which chooses the comparator output with the great- vals. Because TIQ designs are compact, their silicon footprints

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are reduced, which makes it possible to combine them into
extremely small and densely packed integrated circuits.

Fig. 9. Validation Result

the circuit’s capacity to compare two input signals with little

Fig. 7. TIQ Comparator Block Result
offset error, fast speed, and low power consumption efficiently
and accurately. The circuit’s three-stage architecture, which
includes an output buffer stage, a positive feedback stage,
and a preamplification stage, thoughtfully tackles the need
for precision and resistance to process and environmental
fluctuations.
The CMOS-LTE comparator, the open loop comparator, the
TIQ comparator, the quantized differential comparator, and
the two-stage CMOS amplifier with an output inverter are
just a few of the comparators that are carefully studied in
the extensive literature research. The evaluation emphasizes
Fig. 8. 3-bit flash ADC Result the wide range of comparator designs and their distinctive
qualities. The paper also illustrates the comparator circuit’s
Because of these combined advantages, the TIQ comparator versatility in electronic systems by highlighting its possible
is the best option for creating Flash ADCs. It provides a uses in low-power devices, sensor interfaces, and analog-to-
convincing solution that strikes a compromise between power digital converters.
efficiency, speed, and space restrictions in various applications, In addition to providing a thorough examination of the
including instrumentation, signal processing, and telecommu- prerequisites for effective voltage comparison, the research
nications. To meet the demanding specifications of contempo- successfully illustrates the design of a high-precision compara-
rary electronic systems, the TIQ-based Flash ADC offers an tor circuit. The results show the well-engineered performance
effective and dependable way to convert analog signals into of the finished circuit, which is explained in detail.
digital form.
VII. F UTURE SCOPE
TABLE I • Integration with Emerging Technologies: Examine how
P OWER C ONSUMPTION AND DELAY the high-precision comparator circuit can be integrated
with cutting-edge technologies like machine learning and
Reference Technology (nm) VDD (V) Power (μW) Delay (μs)
[1] 180 1.8 3472 116.54 artificial intelligence. Examine how these technologies
[9] 180 1.8 8000 - can be used in real-time applications to improve the
[10] 180 1.8 20000 - comparator circuit’s self-optimization, performance, and
This work 180 1.8 26.39 32.96
adaptability.
• Advanced Process Technologies: Examine how the com-
This functions as a sinusoidal signal with an input amplitude
parator circuit can be used in new process technologies,
of 1.8V and a frequency of 10k Hz. The comparator’s step size
such as submicron or nanoscale CMOS technology. Ex-
is 1.8V, and it compares signals in the range of 0.3V to 1.7V.
amine how the circuit may adjust to and benefit from the
Additionally, the comparator is independent of frequency.
special qualities and difficulties that these cutting-edge
V. VALIDATION technologies offer.
Results from a validation procedure using a 3-bit Digital • Low Power Design for IoT Devices: Explore the potential
Analog Converter (DAC) to determine whether the digital uses of the circuit’s low power consumption feature in
output is actually and accurately converted to an analog signal Internet of Things (IoT) devices through Low-Power
are shown in Fig [9]. Design. Concentrate on creating comparators that are
energy-efficient and appropriate for battery-powered In-
VI. C ONCLUSION ternet of Things applications.
The study highlights the development and successful appli- • Enhancements in Speed and Bandwidth: Look into ways
cation of a high-precision comparator circuit, demonstrating to make the comparator circuit even faster and more

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 versatile while still using a minimal amount of electricity.
This can entail investigating different architectures, refin-
ing the circuit topology, or using cutting-edge materials
during manufacture.
• Exploration of New Comparator Designs: Proceed with
the investigation of unique comparator designs that go
beyond the document’s three-stage architecture. Look at
different configurations or topologies that can provide
better performance or extra features for particular appli-
cations.
R EFERENCES
[1] M. Sowmya Priya, M. Senthil Sivakumar, and S. Pulya, ”Comparative
analysis of the CMOS 180nm technology-based flash ADC designs using
a dynamic comparator and TIQ comparator,” 2019 2nd International
Conference on Power and Embedded Drive Control (ICPEDC), Chennai,
India, 2019, pp. 111-115, doi: 10.1109/ICPEDC47771.2019.9036632.
[2] M. Kulkarni, V. Sridhar and G. H. Kulkarni, ”4-bit Flash Analog to
Digital Converter design using CMOS-LTE Comparator,” 2010 IEEE
Asia Pacific Conference on Circuits and Systems, Kuala Lumpur,
Malaysia, 2010, pp. 772-775, doi: 10.1109/APCCAS.2010.5774817.
[3] Neha, Amana Yadav and Ila Chaudhary. “Design and Analysis of
Comparators using 180 nm CMOS Technology.” (2016).
[4] J. Talukdar and B. Das, ”An improved TIQ comparator based 3-bit
flash ADC,” 2017 1st International Conference on Electronics, Materials
Engineering and Nano-Technology (IEMENTech), Kolkata, India.
[5] R. Joglekar, R. Daniels, A. Jagare, P. Shah and S. S. Rathod, ”TIQ
Comparator Based 8-bit Flash ADC for Communication Applications,”
2022 Sardar Patel International Conference on Industry 4.0 - Nascent
Technologies and Sustainability for ’Make in India’ Initiative, Mumbai,
India, 2022, pp. 1-6, doi: 10.1109/SPICON56577.2022.10180784.
[6] S. K. Vinodiya and R. S. Gamad, ”Analysis and design of low power,
high-speed comparators in 180nm technology with low supply voltages
for ADCs,” 2017 8th International Conference on Computing, Commu-
nication and Networking Technologies (ICCCNT), Delhi, India, 2017,
pp. 1-5, doi: 10.1109/ICCCNT.2017.8203994.
[7] Mishra, Sujeet Kumar, and Bal Chand Nagar. “DESIGN of a TIQ
COMPARATOR for HIGH SPEED and LOW POWER 4 BIT FLASH
ADC.” (2002).
[8] S. A. V. Kuppa, S. D. N. S. S. Manikanta, S. K. Gubba, M. O. V. P.
Kumar and G. M. Sheeba, ”Design of Low Power Flash ADC using TIQ
Comparator,” 2023 International Conference on Sustainable Computing
and Data Communication Systems (ICSCDS), Erode, India.
[9] YOUNG, J.; HOON, K.; CHULWOO, K.; SOO-WONK, K. A5-bit 500-
Ms/s flash ADC using time- domain comparison. Journal of Circuits,
Systems, and Computer, v. 21, n. 8, p. 1240023/1-1240023/12, 2012.
[10] AGRAWAL, N.; PAILY, R. A threshold inverter quantization based
folding and interpolation ADC in 0.18 μm CMOS. Journal Analog
Integrated Circuits and Signal Processing, v. 63, n. 2, p. 273-281, 2010.

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