Chapter 2

Computer Organization
Contents:
1. Basic Computer Organization
2. System Buses
3. Instruction Cycles
4. CPU organization
5. Memory sub-system, organization and interfacing
6. IO sub-system organization and interfacing

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1. Basic Computer Organization
• This organization has three
main components:
– CPU,
– memory subsystem, and
– IO subsystem

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 Structural view of Computer System
CPU Controls the operation of the computer
and performs its data processing
functions; also referred as processor.

Main Stores data

Memory
I/O Moves data between the memory and
its external environment
System Some mechanism that provides for
Intercon communication among CPU, main
nection memory and I/O. it is done through
system bus.

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Structural view of Computer System (Contd.)
Control Unit: Controls the operation of
the CPU and hence the
computer.
ALU: Performs the computer’s
data processing function.
Registers: Provides storage internal to
the CPU.
CPU Some mechanisms that
interconnectio provide for communication
n: among the CU, ALU and
registers.

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Structural view of Computer System (Contd.)
Control The registers which store
Memory: data related to control
operation.

Sequential Digital circuit whose

Logic: output depends on current
input and state of circuit.

CU register Performs storage and

& decoder: interpretation of the
instruction.

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2. System Buses
• Physically, a bus is a set of wires.
• The components of the computer are connected to the buses.
• To send information form one component to another, the source
component outputs data onto the bus.
• The destination component then inputs this data from the bus.
• As the complexity of a computer system increases, it becomes more
efficient at using buses rather than direct connections between
every pair of devices.
• Buses use less space on a circuit board and require less power than
a large number of direct connections.
• They also require fewer pins on the chip or chips that comprise the
CPU.

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2. System Buses (Contd.)
• It is a shared transmission medium. Multiple devices connect to the
bus, and a signal transmitted by one device is available for reception by
all other devices attached to the bus.
• If two devices transmit during the same time period, their signals will
overlap and become garbled.
• Thus, only one device, at a time, can successfully transmit.
• Typically, a bus consists of multiple communication pathways or lines.
• Each line is capable of transmitting signals representing binary 1 or 0.
• An 8-bit unit of data can be transmitted over eight bus lines.
• A bus that connects major computer components (processor, memory,
IO) is called a system bus.

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2. System Buses (Contd.)
Data The data lines provide a path for moving data
Lines among system modules. These lines,
collectively, are called the data bus.
Address The address lines are used to designate the
Lines source or destination of the data on the data
bus.
Control The control lines are used to control the
Lines access to and the use of the data and address
lines.
Control signals transmit both command and
timing information among system modules.
• Timing signals indicate the validity of
data and address information.
• Command signals specify operation to
be performed.

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3. Instruction Cycle

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3. Instruction Cycle (Contd.)

• The instruction cycle is the procedure a microprocessor goes

through to process an instruction.
• First the microprocessor fetches or reads, the instruction from
memory.
• Then it decodes the instruction, determining which instruction it
has fetched.
• Finally, it performs the operations necessary to execute the
instruction.
• Each of these functions- fetch, decode and execute- consists of a
sequence of one or more operations.

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4. CPU organization
• CPU consists of three components:
– ALU,
– CU and
– Registers.
• ALU performs arithmetic and logical operation,
• CU provides control signals, and
• Registers store binary information and provide
very fast information to ALU and out of CPU.
• These components are connected with each other
and with external environment through system
bus as shown below:

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2.4 Memory Sub-system Organization and Interfacing
• Memory is the group of circuits used to store data.
• Two types of Memory:
1. RAM
a) SRAM:
▪ More like registers, no need of refresh
b) DRAM:
▪ Leaky capacitor, needs refresh

2. ROM
a) PROM (Programmable ROM)
b) EPROM (Erasable PROM)
▪ can be reprogrammed if required by exposing it to ultraviolet light.
c) EEPROM (Electrically Erasable PROM)
▪ write and erase operations are performed one byte at a time , by application of electrical potential
d) Flash Memory
Reference: https://www.guru99.com/different-types-ram-random-access-memory.html
https://www.scaler.com/topics/what-is-rom/

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RAM Vs ROM
• Volatile in nature. • Read only memory (ROM) contains a
• Used for reading and writing data in permanent pattern of data that cannot
any order as required. be changed.
• Data is stored and read many times to • A ROM is non-volatile, i.e., no power
and from this type of memory. source is required to maintain the bit
• Memory cells can be accessed for values in memory.
information transfer from any desired • While it is possible to read a ROM, it is
random location. not possible to write new data into it.
• The data or program is permanently
presented in main memory and never
be loaded from a secondary storage
device with the advantage of ROM.

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Internal Chip Organization
• Linear organization
• Two-dimensional organization

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Linear organization
• Consider an 8 x 2 ROM chip: (Chip
is in 2n x m representation where n
is address line and m is data line)
– Address line = 3
– Data lines = 2
– 16 bits of internal storage
– If CE = 0, decoder is disabled and no
location is selected. The Tri-state
buffer for that location’s cell are
enabled, allowing data to pass to the
output buffers.
– If CE = 1and OE= 1, tri-state buffer
for that location cell is enabled and
data is output from the chip;
otherwise the outputs are tri-stated.

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Classwork:
• show the internal
linear configuration
of a 32x2 memory
chip.

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Classwork:
• show the internal
linear configuration
of a 32x2 memory
chip.

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Two-dimensional organization
• As the number of locations
increases, the size of address
decoder needed, becomes
extremely large.
• To remedy this problem, the
memory chip can be designed
using multiple dimension of
decoding.
• This configuration has four rows
with four bits per row; each holds
two data values.
• Here,
• A0→ selects one of the 2
locations in a row
• A1, A2→ selects one of 4 rows.

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2.5 Memory Sub system Configuration
• There is technique for joining memory chips to form a memory subsystem.
• Two or more chips can be combined to generate a memory with more bits
per location.
• This is done by linking the corresponding address and control signals of
the chips and linking their data pins to various bits of the data bus.

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Construction of 8 x 4 ROM from two 8 x 2 ROMs:
• Two 8 x 2 chips can be combined to generate an 8 x 4 memory as
displayed in the figure.
• Both chips get the equal three address inputs from the bus, and the
same chip enable (CE) and output enable (OE) signals.
• The data chips of the first chips are linked to bits 3 and 2 of the data
bus(i.e. D3 and D2)
• and those of the other chips are linked to bits 1 and 0 (i.e. D1 and D0)
• When the CPU reads data, it locates the address on the address bus.
• Both chips read in address bits A2, A1, and A0 and implement their
internal decoding..
• If the CE (Chip Enable) and OE (Output Enable) signals are activated,
the chips output their data onto the four bits of the data bus.
• Because the address and enable signals are equal for both chips,
either both chips and neither chip is active at any given time.
• The device never has only one of the two, active.
• For this reason, they facilitate as only a single 8 x 4 chip at least until
the CPU is concerned.
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Construction of 16 x 2 ROM from two 8 x2 ROM chip:
• Instead of
generating
wider words,
chips can be
combined to
make more
words.
• The similar two
8 x 2 chips could
alternatively be
configured as a
16 x 2 memory
subsystem.

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i) Using high-order interleaving
• The configuration in figure (a) uses high-order
interleaving. All memory locations inside a chip are
contiguous within system memory.
• The upper chip is configured as memory locations 0
to 7 (0000 to 0111) and
• the lower chip as locations 8 to 15 (1000 to 1111).
• The upper chip always has A3=0 and the lower chip
has A3=1.
• This difference can choose one of the two chips.
• When A3=0, the upper chip is enabled and the lower
chip is disabled.
• The output enables can be linked, because only the
chip that is enabled with output data.
• Both chips correspond to similar data bits, both are
linked to D1 and D0 of the data bus

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ii) Using low-order interleaving
• Consider the configuration
displayed in figure (b) which uses
low-order interleaving.
• The upper chip is enabled when
A0=0, or by addresses XXX0, in this
case, 0, 2, 4, 6, 8, 10,12, and 14.
• The lower chip is enabled when
A0=1, which is correct for addresses
1, 3, 5, 7, 9, 11, 13, and 15.

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Classwork:
1. Design an 8x4 ROM using 4x4 ROM chips using higher order
interleaving. Also explain its operation.
2. Design a 16x4 memory subsystem with low order interleaving using
8x2 memory chips for a computer system with an 8-bit address bus.
3. Design a 32x 8 memory subsystem with high-order interleaving using
16x2 memory chips for a computer system with an 8-bit address bus.

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1. Design an 8x4 ROM using 4x4 ROM chips using higher order interleaving. Also
explain its operation.
• Here:
• Available ROM size = 4x4
• Required ROM size = 8x4
8𝑥4
• No. of required ROMs = 4𝑥4 = 2 • When A2= 0, the 1:2 decoder outputs form
• Since, the multiplicand is different, we will have vertical the first line (i.e 0) and thus enables ROM1
arrangement of ROMs as below: • When A2= 0, the 1:2 decoder outputs form
the second line (i.e 1) and thus enables
ROM2.
• When address line (A2-A0) is from 000 to
011, the upper ROM1 chip is enabled and
the corresponding data (D3-D0) will be
out.
• When address line (A2-A0) is from 100 to
111, the upper ROM1 chip is enabled and
the corresponding data (D3-D0) will be
out.

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 2. Design a 16x4 memory subsystem with low order interleaving using 8x2
memory chips for a computer system with an 8-bit address bus.

Note: Decoder can be used for bit interleaving as in qstn 1

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 3. Design a 32x 8 memory subsystem with high-order interleaving using
16x2 memory chips for a computer system with an 8-bit address bus.

Note: Decoder can be used for bit interleaving as in qstn 1

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6. I/O subsystem Organization and Interfacing
• The I/O subsystem is treated as
an independent unit in the
computer.
• The CPU initiates I/O command
generally as Read, Write, Scan,
etc.
• As shown in figure:
– The I/O device is connected
to the computer system
address, data and control
buses.
– Each I/O device includes I/O
circuitry that interacts with
the buses.

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Input device
• The data from the input device goes to
the tri-state buffer.
• When the values on the address bus and
control bus are correct, the buffers are
enabled and data passes onto the data
bus.
• The CPU, then can read these data.
• The key to this design is the enable logic.
• For the input device, the read signal (RD)
should be asserted.
• Figure (b) shows the enable logic for an
input device at address 11110000 with
8-bit address and control signals RD and
IO/𝑀ഥ (IO/Memory).

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Output Device:
• For the interface circuit for an output
device, the tri-state buffer is replaced by
a register.
• Only the device with the correct address
will read it in.
• The Load logic (LD) plays the role of the
enable logic as in the input device.
• When this logic receives the correct
address and control signals, it asserts
the LD signal of the register, causing it to
read data from the system’s data bus.
• The output device can then read the
data from the register at its leisure while
the CPU performs other tasks.
• The logic to generate the load signal for
an output device at address 1111 0000 is
shown in figure (b).

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Bidirectional IO device
• Some devices are used for both input
and output. A personal computer’s
hard disk drive falls into this category.
• Such a device requires a combined
interface that is essentially two
interfaces, one for input and the other
for output.
• Some logic elements, such as the gates
that check the address and the address
bus, can be used to generate both the
buffer enable and register load signals.
• Figure below shows a combined I/O
interface for address 1111 0000.

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1. Design an interface for an input device which has binary address 1010 1010. Its
computer system uses isolated I/0.

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2. Design an interface for an input device which has binary address 1010 1010. Its
computer system uses memory mapped I/O.

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6. A CPU with 8-bit data bus and 8-bit address bus uses memory
mapped I/O. It has 32 byte of ROM at 00H and 32 byte of ROM at
20H. It also has an I/O device at FFH. Show the load logic and
enable logic.

• Here:
• Data bus width = 8 bits (D7-D0)
• Address bus width = 8 bits (A7-A0)
• ROM1 size= 32x8 starting at 00H (5 Address lines: A4-A0)
• ROM2 size= 32x8 starting at 20H (5 Address lines: A4-A0)
• I/O device starting at FFH

Memory HexCod A7 A6 A5 A4 A3 A2 A1 A0
e

ROM1 00H 0 0 0 0 0 0 0 0

1FH 0 0 0 1 1 1 1 1

ROM2 20H 0 0 1 0 0 0 0 0

3FH 0 0 1 1 1 1 1 1

IO FFH 1 1 1 1 1 1 1 1

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7. A computer system with an 8-bit address and an 8-bit data bus
using isolated I/O. It has 16 x 8 ROM starting at address 00H
constructed using 8 x8 chips; 64 x 8 of RAM starting at address
80H constructed using 64 x 4 chips. There is an I/O device at
40H. Show the design for the system.

Here:
• Data bus width = 8 bits (D7-D0)
• Address bus width = 8 bits (A7-A0)
• ROM1 size= 8x8 starting at 00H (Address lines: A2-A0)
• ROM2 size= 8x8
• RAM1 size= 64x4 starting at 80H (Address lines: A4-A0)
• RAM2 size= 64x4
• I/O device starting at 40H

Memory HexCo A7 A6 A5 A4 A3 A2 A1 A0
de

ROM1 00H 0 0 0 0 0 0 0 0

07H 0 0 0 0 0 1 1 1

ROM2 08H 0 0 0 0 1 0 0 0

0FH 0 0 0 0 1 1 1 1

RAM1 80H 1 0 0 0 0 0 0 0
and
RAM2

BFH 1 0 1 1 1 1 1 1

IO 40H 0 1 0 0 0 0 0 0

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8. A computer system with 8-bit data bus and 8-bit control bus uses isolated
I/O. It has 64 bytes of ROM starting at 00H constructed using 64 x 4 chips;
128 bytes of RAM, starting at address 40H constructed using 32 x 8 chips; an
input device with READY signal at address 40H; and an output with no
READY signal at address 80H. Show the design for this system. Include all
enable and load logic.
Here:
• Data bus width = 8 bits (D7-D0)
40H=
• Address bus width = 8 bits (A7-A0) 0100 0000
• ROM size= 64x8 starting at 00H (5 Address lines: A4-A0)
– We require two 64x4 ROMs for its construction
• RAM size= 128x8 starting at 40H (6 Address lines: A5-A0)
– We require five 32x8 chips for its construction
• Input device with READY signal at 40H
• Output device with no READY signal at 80H
80H=
Decimal Value
1000 0000

1 and 2

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Classwork:
A computer system with an 8-bit address bus and an 8-bit data bus uses memory mapped I/O.
It has 64 bytes of PROM starting at address 00H constructed using 32x4 chips; 128 bytes of
RAM starting at address 40H constructed using 64x8 chips; an input device with READY signal
at address 40H; and an output device with no READY signal at address 80H. Show the design
for this system. Include all enable and load logic.

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Assignment:
1. A computer system with an 8-bit address bus and an 8-bit data bus uses memory mapped I/O. It has 32 bytes of ROM
starting at address 00H constructed using a single 32x8 chip; 128 bytes of RAM starting at address 80H constructed using
64x4 chips; a bidirectional I/O device with no READY signal at address 40H; and an input device with no READY signal at
address 60H. Show the design for this system. Include all enable and load logic.
2. A Computer System with an 8-bit address bus and an 8-bit data bus uses isolated I/O. it has 128 bytes of EPROM starting
at address 00H constructed using 128x2 chips; 32 bytes of RAM starting at address E0H constructed using 16x8 chips; an
input device with a READY signal at address 00H; an output device with a READY signal at address FFH; and a
bidirectional I/O device with no READY signal at address 80H. Show the design for this system. Include all enable and
load logic.
3. A computer system with an 8-bit address bus and an 8-bit data bus uses memory mapped I/O. It has 128 bytes of PROM
starting at address 00H constructed using 32x4 chips; 96 bytes of RAM starting at address 80H constructed using one
64x8 chip and several 32x2 chips; an input device with a READY signal at address F0H; an output device with a REASY
signal at address F1H; and a bidirectional I/O device with a READY signal at address F2H; and Show the design for this
system. Include all enable and load logic.

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Solution 1:

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Solution 2:

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Solution
3:

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Assignment:
1. Differentiate between Internal Linear and Two-dimensional Memory Organization.
2. Explain instruction cycle for read and write operations using their timing diagram.
3. A computer has a CPU with 8 bit data bus and 8 bit address bus. The system operates in isolated I/O
mode. It has a 64 byte ROM at 00H constructed using two 32-byte ROM. It also has a RAM of 128 byte
constructed using two 128*4 RAM chips and is integrated with starting address 80H. The system also
has an I/O device at 7EH. Show the design for this system including all the required logic.
4. A computer system with 8 bit address bus and an 8 bit data bus uses isolated IO. It has 64 bytes of
EEPROM starting at address 00H constructed using 64x4 chips; 128 bytes of RAM starting at address
40H constructed using 32x8 chips; an input device with a READY signal at address 40H; and an output
device with no READY signal at address 80H. Show the design for this system.
5. A computer has a CPU with 8 bit data bus and 16 bit address bus. The computer uses memory mapped
I/O. it has 8K of ROM starting at address 0000H, followed by 8K of RAM. It also has a bidirectional I/O
port at address 8000H. Show the design for the system including all the required logic.
6. Design a 16x8 ROM using 16x4 ROM chips. Illustrate it with both high –order and low order bit
interleaving.
7. Design a 16x8 ROM using 4x8 ROM chips. Illustrate it with both high –order and low order bit
interleaving.
8. Design a 16x8 ROM using 4x4 ROM chips. Illustrate it with both high –order and low order bit
interleaving.

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Exam questions:
1. A computer has a CPU with 8-bit address bus and 16-bit data bus. The computer uses isolated I/O. It has 64
bytes of ROM at 10 H; constructed using two 32 bytes ROM chips. It also has 32 bytes of RAM at C0 H. The
system has an I/O device at 85 H. Show the design for the system including all the required logic. [ 2017 Fall]
2. A computer has a CPU with 8-bit address bus and 8-bit data bus. The computer uses Memory mapped I/O. It has
32 bytes of ROM at 10 H; constructed using two 16 bytes ROM chips. It also has 32 bytes of RAM at 80 H. The
system has an input device at F7 H and an output device at F8 H. Show the design for the system including all
the required logic. [ 2017 spring]
3. A computer has a CPU with 8-bit address bus and 16-bit data bus. The computer uses Isolated I/O. It has 64 x 16
of ROM at 00 H; constructed using two 32 x 16 ROM chips. It also has 32 x16 of RAM at C0 H. The system has an
input device at 17 H and an output device at B5 H. Show the design for the system including all the required
logic. [PU 2018 Fall]
4. Design an 8x4 ROM chips using 4x4 ROM chips. Illustrate using lower order interleaving. [PU 2018 Spring]
5. Define enable and load logic. Generate load logic for an output device at CFh. Assume the system being
operated in isolated mode. [PU 2018 Spring]
6. Design a 32 B RAM using four 16x4 ROM chips. [PU 2019 Spring]
7. Design 16x4 memory sub-system constructed from 16x2 ROM chips with both low-level and high-level
interleaving. [PU 2020 Spring]
8. A computer has a CPU with 8-bit address bus and 8-bit data bus. The computer uses Memory mapped I/O. It has
32 bytes of ROM starting at 00 H; constructed using two 16 bytes ROM chips. It also has 32 bytes of RAM starting
at 80 H. The system has an input device and an output device at F0 H. Show the design for the system including
all the required logic. [PU 2022 Fall]

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 End of chapter

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