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Implement 16 bit division circuit using data flow architecture

The document provides VHDL code for an 8-bit division circuit using a data flow architecture, including a main division module and a test bench. The division process handles division by zero by returning a quotient of zero and the dividend as the remainder. It implements a bit-by-bit shifting approach to perform the division operation iteratively.

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3 views7 pages

Implement 16 bit division circuit using data flow architecture

The document provides VHDL code for an 8-bit division circuit using a data flow architecture, including a main division module and a test bench. The division process handles division by zero by returning a quotient of zero and the dividend as the remainder. It implements a bit-by-bit shifting approach to perform the division operation iteratively.

Uploaded by

strikerxlotal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Implement 16 bit division circuit using data flow architecture

VHDL Module code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Division8bit is
Port (
dividend : in STD_LOGIC_VECTOR(7 downto 0);
divisor : in STD_LOGIC_VECTOR(7 downto 0);
quotient : out STD_LOGIC_VECTOR(7 downto 0);
remainder : out STD_LOGIC_VECTOR(7 downto 0)
);
end Division8bit;

architecture Behavioral of Division8bit is


begin
process(dividend, divisor)
variable temp_dividend : STD_LOGIC_VECTOR(7 downto 0);
variable temp_divisor : STD_LOGIC_VECTOR(7 downto 0);
variable temp_quotient : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
variable temp_remainder : STD_LOGIC_VECTOR(7 downto 0);
begin
temp_dividend := dividend;
temp_divisor := divisor;
temp_remainder := (others => '0');

-- Handle division by zero case


if temp_divisor = "00000000" then
temp_quotient := (others => '0'); -- Return 0 for quotient
temp_remainder := temp_dividend; -- Return dividend as remainder
else
-- Perform sequential subtraction-based division
for i in 7 downto 0 loop
temp_remainder := temp_remainder(6 downto 0) & temp_dividend(7); -- Shift left
temp_dividend := temp_dividend(6 downto 0) & '0'; -- Left shift

if temp_remainder >= temp_divisor then


temp_remainder := temp_remainder - temp_divisor;
temp_quotient := temp_quotient(6 downto 0) & '1';
else
temp_quotient := temp_quotient(6 downto 0) & '0';
end if;
end loop;
end if;

-- Assign outputs
quotient <= temp_quotient;
remainder <= temp_remainder;
end process;
end Behavioral;

VHDL Test Bench


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Testbench is
end Testbench;

architecture behavior of Testbench is

-- Component declaration for the Division8bit entity


component Division8bit
Port (
dividend : in STD_LOGIC_VECTOR(7 downto 0);
divisor : in STD_LOGIC_VECTOR(7 downto 0);
quotient : out STD_LOGIC_VECTOR(7 downto 0);
remainder : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;

-- Signals to connect to the component


signal dividend : STD_LOGIC_VECTOR(7 downto 0);
signal divisor : STD_LOGIC_VECTOR(7 downto 0);
signal quotient : STD_LOGIC_VECTOR(7 downto 0);
signal remainder : STD_LOGIC_VECTOR(7 downto 0);

begin

-- Instantiate the Division8bit component


uut: Division8bit
port map (
dividend => dividend,
divisor => divisor,
quotient => quotient,
remainder => remainder
);

-- Stimulus process
stimulus_process: process
begin
-- Test Case 1: 24 / 6 = 4 remainder 0
dividend <= "00011000"; -- 24
divisor <= "00000110"; -- 6
wait for 20 ns;

-- Test Case 2: 100 / 5 = 20 remainder 0


dividend <= "01100100"; -- 100
divisor <= "00000101"; -- 5
wait for 20 ns;

-- Test Case 3: 50 / 7 = 7 remainder 1


dividend <= "00110010"; -- 50
divisor <= "00000111"; -- 7
wait for 20 ns;

-- Test Case 4: 127 / 3 = 42 remainder 1


dividend <= "01111111"; -- 127
divisor <= "00000011"; -- 3
wait for 20 ns;

-- Test Case 5: 45 / 1 = 45 remainder 0


dividend <= "00101101"; -- 45
divisor <= "00000001"; -- 1
wait for 20 ns;

-- Test Case 6: 15 / 15 = 1 remainder 0


dividend <= "00001111"; -- 15
divisor <= "00001111"; -- 15
wait for 20 ns;

-- Test Case 7: Edge Case - Divide by Zero (should handle safely)


dividend <= "00101010"; -- 42
divisor <= "00000000"; -- 0
wait for 20 ns;

-- Stop simulation
wait;
end process;

end behavior;
Explanation

 library IEEE; → Includes the IEEE standard library, which provides logic types.
 use IEEE.STD_LOGIC_1164.ALL; → Enables standard logic (std_logic_vector)
operations.
 use IEEE.STD_LOGIC_ARITH.ALL; → Enables arithmetic functions for logic vectors.
 use IEEE.STD_LOGIC_UNSIGNED.ALL; → Allows treating std_logic_vector as
unsigned numbers.
 entity Division8bit is → Defines the hardware module for division.
 dividend (8-bit input) → The number to be divided.
 divisor (8-bit input) → The number by which we divide.
 quotient (8-bit output) → The result of dividend ÷ divisor.
 remainder (8-bit output) → The remainder of the division.
 architecture Behavioral of Division8bit is → Describes how the division
works.
 process(dividend, divisor) → Runs whenever dividend or divisor changes.
 temp_dividend → Stores the current value of the dividend.
 temp_divisor → Stores the current value of the divisor.
 temp_quotient → Stores the computed quotient (initialized to 00000000).
 temp_remainder → Stores the computed remainder.
 Copies dividend and divisor into temporary variables.
 temp_remainder is initialized to 0.
 If divisor = 0, division is not allowed (undefined behavior).
 Instead of crashing:
o The quotient is set to 0.
o The remainder is set to the dividend.

This is an iterative division using subtraction and bit shifts, similar to long division.

🔄 How it works?

1. Bit-by-bit shifting approach (like hardware division):


o The remainder is shifted left and the next bit of the dividend is added.
o The dividend itself is shifted left.

2. If remainder ≥ divisor:
o Subtract divisor from remainder.
o Append '1' to quotient.

3. If remainder < divisor:


o Append '0' to quotient (indicating no subtraction happened).

This loop runs 8 times (since we're dividing 8-bit numbers).

 End of if condition (handles both normal division and division by zero).


 Final quotient and remainder are assigned to outputs.
 End of the process block and architecture definition.

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