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4x1 Multiplexer Using 2x1

The document provides VHDL code for a 4x1 multiplexer constructed using three 2x1 multiplexers. It includes the entity and architecture definitions for both the 2x1 and 4x1 multiplexers, as well as a test bench for simulating the 4x1 multiplexer. The test bench initializes inputs and applies various test cases to validate the functionality of the multiplexer.

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4 views8 pages

4x1 Multiplexer Using 2x1

The document provides VHDL code for a 4x1 multiplexer constructed using three 2x1 multiplexers. It includes the entity and architecture definitions for both the 2x1 and 4x1 multiplexers, as well as a test bench for simulating the 4x1 multiplexer. The test bench initializes inputs and applies various test cases to validate the functionality of the multiplexer.

Uploaded by

strikerxlotal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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4x1 multiplexer using three 2x1 multiplexer VHDL

code:
Truth Table:

2X1 MULTIPLEXER VHDL CODE:


library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity MUX2X1_MODULE is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

S : in STD_LOGIC;

M : out STD_LOGIC);

end MUX2X1_MODULE;
architecture Behavioral of MUX2X1_MODULE is

begin

M<=(A AND (NOT S)) OR (B AND S);

end Behavioral;

4X1 MULTIPLEXER VHDL CODE:


library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity MUXSTRUCT4X1_MODULE is

Port ( I1 : in STD_LOGIC;

I2 : in STD_LOGIC;

I3 : in STD_LOGIC;

S0 : in STD_LOGIC;

S1 : in STD_LOGIC;
I0 : in STD_LOGIC;

Y : out STD_LOGIC);

end MUXSTRUCT4X1_MODULE;

architecture Behavioral of MUXSTRUCT4X1_MODULE is

COMPONENT MUX2X1_MODULE is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

S : in STD_LOGIC;

M : out STD_LOGIC);

end COMPONENT;

SIGNAL X1,X2:STD_LOGIC;

begin

IC1: MUX2X1_MODULE PORT MAP(I0,I1,S0,X1);

IC2: MUX2X1_MODULE PORT MAP(I2,I3,S0,X2);

IC3: MUX2X1_MODULE PORT MAP(X1,X2,S1,Y);

end Behavioral;

4X1 TEST BENCH CODE:


LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY MUX4X1_TEST IS
END MUX4X1_TEST;

ARCHITECTURE behavior OF MUX4X1_TEST IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT MUXSTRUCT4X1_MODULE

PORT(

I1 : IN std_logic;

I2 : IN std_logic;

I3 : IN std_logic;

S0 : IN std_logic;

S1 : IN std_logic;

I0 : IN std_logic;

Y : OUT std_logic

);

END COMPONENT;

--Inputs

signal I1 : std_logic := '0';

signal I2 : std_logic := '0';

signal I3 : std_logic := '0';

signal S0 : std_logic := '0';

signal S1 : std_logic := '0';

signal I0 : std_logic := '0';

--Outputs

signal Y : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name


--constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: MUXSTRUCT4X1_MODULE PORT MAP (

I1 => I1,

I2 => I2,

I3 => I3,

S0 => S0,

S1 => S1,

I0 => I0,

Y => Y

);

-- Clock process definitions

-- <clock>_process :process

-- begin

-- <clock> <= '0';

-- wait for <clock>_period/2;

-- <clock> <= '1';

-- wait for <clock>_period/2;

-- end process;

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;

I0<='1';

I1<='0';

I2<='1';

I3<='0';

S0<='0';
S1<='0';

WAIT FOR 100 NS;

S0<='1';

S1<='0';

WAIT FOR 100 NS;

S0<='0';

S1<='1';

WAIT FOR 100 NS;

S0<='1';

S1<='1';

WAIT FOR 100 NS;

--wait for <clock>_period*10;

-- insert stimulus here

wait;

end process;

END;

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