Multiformat SDTV Video Decoder

ADV7181
FEATURES
Multiformat video decoder supports NTSC-(J, M, 4.43), Differential phase: 0.6° typ
PAL-(B/D/G/H/I/M/N), SECAM Programmable video controls:
Integrates three 54 MHz, 9-bit ADCs Peak-white/hue/brightness/saturation/contrast
Clocked from a single 27 MHz crystal Integrated on-chip video timing generator
Line-locked clock-compatible (LLC) Free run mode (generates stable video ouput with no I/P)
Adaptive Digital Line Length Tracking (ADLLT™) VBI decode support for
5-line adaptive comb filters Close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
Proprietary architecture for locking to weak, noisy, and Power-down mode
unstable video sources such as VCRs and tuners 2-wire serial MPU interface (I2C®-compatible)
Subcarrier frequency lock and status information output 3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Integrated AGC with adaptive peak white mode Temperature grade: –40°C to +85°C
Macrovision® copy protection detection 64-lead LQFP Pb-free package
CTI (chroma transient improvement)
DNR (digital noise reduction) APPLICATIONS
Multiple programmable analog input formats: DVD recorders
CVBS (composite video) PC video
S-Video (Y/C) HDD-based PVRs/DVDRs
YPrPb component (VESA, MII, SMPTE, and Betacam)
LCD TVs
6 analog video input channels
Set-top boxes
Automatic NTSC/PAL/SECAM identification
Security systems
Digital output formats (8-bit or16-bit):
Digital televisions
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
Portable video devices
0.5 V to 1.6 V analog signal input range
Automotive entertainment
Differential gain: 0.6% typ
AVR receiver

GENERAL DESCRIPTION
The ADV7181 integrated video decoder automatically detects The fixed 54 MHz clocking of the ADCs and datapath for all
and converts a standard analog baseband television signal modes allow very precise, accurate sampling and digital
compatible with worldwide standards NTSC, PAL, and SECAM filtering. The line-locked clock output allows the output data
into 4:2:2 component video data compatible with 16-/8-bit rate, timing signals, and output clock signals to be synchronous,
CCIR601/CCIR656. asynchronous, or line locked even with ±5% line length
variation. The output control signals allow glueless interface
The advanced, highly flexible digital output interface enables connections in almost any application. The ADV7181 modes
performance video decoding and conversion in line-locked are set up over a 2-wire, serial, bidirectional port (I2C-
clock-based systems. This makes the device ideally suited for a compatible).
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources, The ADV7181 is fabricated in a 3.3 V CMOS process. Its
security/surveillance cameras, and professional systems. monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The six analog input channels accept standard composite,
S-Video, YPrPb video signals in an extensive number of The ADV7181 is packaged in a small 64-lead LFCSP and LQFP
combinations. AGC and clamp restore circuitry allow an input and Pb-free packages.
video signal peak-to-peak range of 0.5 V up to 1.6 V.
Alternatively, these can be bypassed for manual settings.

Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
ADV7181

TABLE OF CONTENTS
Introduction ...................................................................................... 4 Luma Filter.................................................................................. 27
Analog Front End......................................................................... 4 Chroma Filter ............................................................................. 30
Standard Definition Processor ................................................... 4 Gain Operation........................................................................... 31
Functional Block Diagram .............................................................. 5 Chroma Transient Improvement (CTI) .................................. 35
Specifications..................................................................................... 6 Digital Noise Reduction (DNR)............................................... 36
Electrical Characteristics............................................................. 6 Comb Filters ............................................................................... 36
Video Specifications..................................................................... 7 AV Code Insertion and Controls ............................................. 39
Timing Specifications .................................................................. 8 Synchronization Output Signals .............................................. 41
Analog Specifications .................................................................. 8 Sync Processing .......................................................................... 49
Thermal Specifications ................................................................ 8 VBI Data Decode ....................................................................... 50
Timing Diagrams ......................................................................... 9 Pixel Port Configuration ............................................................... 61
Absolute Maximum Ratings.......................................................... 10 MPU Port Description................................................................... 62
ESD Caution................................................................................ 10 Register Accesses........................................................................ 63
Pin Configuration and Function Descriptions........................... 11 Register Programming .............................................................. 63
Analog Front End ........................................................................... 13 I2C Sequencer.............................................................................. 63
Analog Input Muxing ................................................................ 13
I2C Control Register Map.......................................................... 64
Global Control Registers ............................................................... 15
I2C Register Map Details ........................................................... 67
Power-Save Modes ..................................................................... 15
I2C Programming Examples.......................................................... 93
Reset Control .............................................................................. 15
Mode 1—CVBS Input (Composite Video on AIN6) ............ 93
Global Pin Control..................................................................... 16
Mode 2—S-Video Input (Y on AIN1 and C on AIN4)......... 94
Global Status Registers................................................................... 18
Mode 3—525i/625i YPrPb Input (Y on AIN1, Pr on AIN3,
Identification............................................................................... 18 and Pb on AIN5) ........................................................................ 94
Status 1 ......................................................................................... 18 Mode 4—CVBS Tuner Input CVBS PAL on AIN6 ............... 95
Status 2 ......................................................................................... 19 PCB Layout Recommendations.................................................... 96
Status 3 ......................................................................................... 19 Analog Interface Inputs............................................................. 96
Standard Definition Processor (SDP).......................................... 20 Power Supply Decoupling ......................................................... 96
SD Luma Path ............................................................................. 20 PLL ............................................................................................... 96
SD Chroma Path......................................................................... 20 Digital Outputs (Both Data and Clocks) ................................ 96
Sync Processing .......................................................................... 21 Digital Inputs .............................................................................. 97
VBI Data Recovery..................................................................... 21 XTAL and Load Capacitor Value Selection ............................ 97
General Setup.............................................................................. 21 Typical Circuit Connection........................................................... 98
Color Controls ............................................................................ 24 Outline Dimensions ..................................................................... 100
Clamp Operation........................................................................ 26 Ordering Guide ........................................................................ 101

Rev. B | Page 2 of 104

 ADV7181
REVISION HISTORY
3/05—Rev. A to Rev. B 7/04—Rev. 0 to Rev. A

Changes to the Analog Specifications Section ..............................8 Addition to Applications List ..........................................................1
Changes to Table 20 and Table 21 ................................................17 Changes to Table 3 ............................................................................8
Changes to Table 27 and Table 28 ................................................19 Changes to Table 5 ............................................................................8
Change to Table 50..........................................................................25 Replaced Figure 3 ..............................................................................9
Addition to the Clamp Operation Section...................................26 Changes to Global Pin Control Section .......................................16
Changes to Figures 11.....................................................................29 Changes to Table 202 ......................................................................91
Changes to Figures 12, 13, 14 ........................................................30 Changes to Table 203 ......................................................................92
Changes to Chroma Filter Section ................................................30 Added package in Outline Dimensions Section .......................103
Deleted YPM Section and Renumbered Subsequent Tables .....30 Changes to Ordering Guide.........................................................104
Changes to Figure 15 ......................................................................31
Change to the Luma Gain Section ................................................32 5/04—Revision 0: Initial Version
Changes to Table 103 and Table 104............................................42
Deleted Table 172 and Renumbered Subsequent Tables............68
Changes to Table 176......................................................................71
Changes to Table 185......................................................................78
Changes to Table 192......................................................................83
Changes to Table 193......................................................................84
Changes to Table 194......................................................................85
Added XTAL and Load Capacitor Value Selection Section ......97
Change to Figure 41 ........................................................................98

Rev. B | Page 3 of 104

ADV7181

INTRODUCTION
The ADV7181 is a high quality, single chip, multiformat video STANDARD DEFINITION PROCESSOR
decoder that automatically detects and converts PAL, NTSC, The ADV7181 is capable of decoding a large selection of
and SECAM standards in the form of composite, S-Video, and baseband video signals in composite, S-Video, and component
component video into a digital ITU-R BT.656 format. formats. The video standards supported by the ADV7181
The advanced, highly flexible digital output interface enables include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc,
performance video decoding and conversion in line-locked NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The
clock-based systems. This makes the device ideally suited for a ADV7181 can automatically detect the video standard and
broad range of applications with diverse analog video charac- process it accordingly.
teristics, including tape-based sources, broadcast sources, The ADV7181 has a 5-line, superadaptive, 2D comb filter that
security/surveillance cameras, and professional systems. gives superior chrominance and luminance separation when
ANALOG FRONT END decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
The ADV7181 analog front end comprises three 9-bit ADCs standard and signal quality with no user intervention required.
that digitize the analog video signal before applying it to the Video user controls such as brightness, contrast, saturation, and
standard definition processor. The analog front end employs hue are also available within the ADV7181.
differential channels to each ADC to ensure high performance
in mixed-signal applications. The ADV7181 implements a patented adaptive digital line-
length tracking (ADLLT) algorithm to track varying video line
The front end also includes a 6-channel input mux that enables lengths from sources such as a VCR. ADLLT enables the
multiple video signals to be applied to the ADV7181. Current ADV7181 to track and decode poor quality video sources such
and voltage clamps are positioned in front of each ADC to as VCRs, noisy sources from tuner outputs, VCD players, and
ensure that the video signal remains within the range of the camcorders. The ADV7181 contains a chroma transient
converter. Fine clamping of the video signals is performed improvement (CTI) processor that sharpens the edge rate of
downstream by digital fine clamping within the ADV7181. The chroma transitions, resulting in sharper vertical transitions.
ADCs are configured to run in 4× oversampling mode.
The ADV7181 can process a variety of VBI data services such as
closed captioning (CC), wide screen signaling (WSS), copy gen-
eration management system (CGMS), EDTV, Gemstar 1×/2×,
and extended data service (XDS). The ADV7181 is fully
Macrovision certified; detection circuitry enables Type I, II, and
III protection levels to be identified and reported to the user.
The decoder is also fully robust to all Macrovision signal inputs.

Rev. B | Page 4 of 104

 9
6 DATA STANDARD DEFINITION PROCESSOR
CLAMP A/D
AIN1–AIN6 PREPROCESSOR 9
9 LUMA LUMA
INPUT DIGITAL LUMA GAIN LUMA
MUX CLAMP A/D 9 2D COMB
CVBS FINE FILTER CONTROL RESAMPLE
DECIMATION AND (4H MAX)
S-VIDEO CLAMP 8
YPrPb 9 DOWNSAMPLING
CLAMP A/D FILTERS
FUNCTIONAL BLOCK DIAGRAM

PIXEL
8 DATA

L-DNR

SYNC AND
CLK CONTROL 16
SYNC PROCESSING AND LINE AV
SYNC RESAMPLE
CLOCK GENERATION LENGTH CODE
EXTRACT CONTROL
PREDICTOR INSERTION
HS
VS
FIELD

Figure 1.
FSC CTI
RECOVERY C-DNR
OUTPUT FORMATTER

Rev. B | Page 5 of 104

ADV7181
LLC
CHROMA CHROMA
DIGITAL CHROMA CHROMA GAIN CHROMA SFL
2D COMB
FINE DEMOD FILTER CONTROL RESAMPLE
(4H MAX)
CLAMP
CONTROL
SCLK AND DATA
SERIAL INTERFACE SYNTHESIZED
SDA VBI DATA RECOVERY GLOBAL CONTROL
CONTROL AND VBI DATA LLC CONTROL
ALSB

MACROVISION STANDARD FREE RUN

DETECTION AUTODETECTION OUTPUT CONTROL
04820-001
ADV7181
ADV7181

SPECIFICATIONS
Temperature range: TMIN to TMAX, –40°C to +85°C. The min/max specifications are guaranteed over this range.

ELECTRICAL CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating temperature range, unless
otherwise noted.
Table 1.
Parameter Symbol Test Conditions Min Typ Max Unit
STATIC PERFORMANCE
Resolution (Each ADC) N 9 Bits
Integral Nonlinearity INL BSL at 54 MHz –0.475/+0.6 –1.5/+2 LSB
Differential Nonlinearity DNL BSL at 54 MHz –0.25/+0.5 –0.7/+2 LSB
DIGITAL INPUTS
Input High Voltage VIH 2 V
Input Low Voltage VIL 0.8 V
Input Current IIN Pin 29 –50 +50 µA
All other pins –10 +10 µA
Input Capacitance CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage VOH ISOURCE = 0.4 mA 2.4 V
Output Low Voltage VOL ISINK = 3.2 mA 0.4 V
High Impedance Leakage Current ILEAK 10 µA
Output Capacitance COUT 20 pF
POWER REQUIREMENTS1
Digital Core Power Supply DVDD 1.65 1.8 2 V
Digital I/O Power Supply DVDDIO 3.0 3.3 3.6 V
PLL Power Supply PVDD 1.65 1.8 2.0 V
Analog Power Supply AVDD 3.15 3.3 3.45 V
Digital Core Supply Current IDVDD 80 mA
Digital I/O Supply Current IDVDDIO 2 mA
PLL Supply Current IPVDD 10.5 mA
Analog Supply Current IAVDD CVBS input2 85 mA
YPrPb input3 180 mA
Power-Down Current IPWRDN 1.5 mA
Power-Up Time tPWRUP 20 ms
1
Guaranteed by characterization.
2
ADC1 and ADC2 powered down.
3
All three ADCs powered on.

Rev. B | Page 6 of 104

 ADV7181
VIDEO SPECIFICATIONS
Guaranteed by characterization. AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating
temperature range, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions Min Typ Max Unit
NONLINEAR SPECIFICATIONS
Differential Phase DP CVBS I/P, modulate 5-step 0.6 0.7 °
Differential Gain DG CVBS I/P, modulate 5-step 0.6 0.7 %
Luma Nonlinearity LNL CVBS I/P, 5-step 0.6 0.7 %
NOISE SPECIFICATIONS
SNR Unweighted Luma ramp 54 dB
Luma flat field 58 dB
Analog Front End Crosstalk 60 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range –5 +5 %
Vertical Lock Range 40 70 Hz
Fsc Subcarrier Lock Range ±1.3 kHz
Color Lock In Time 60 Lines
Sync Depth Range 20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 Fields
Autodetection Switch Speed 100 lines
CHROMA SPECIFICATIONS
Hue Accuracy HUE 1 °
Color Saturation Accuracy CL_AC 1 %
Color AGC Range 5 400 %
Chroma Amplitude Error 0.5 %
Chroma Phase Error 0.5 °
Chroma Luma Intermodulation 0.2 %
LUMA SPECIFICATIONS
Luma Brightness Accuracy CVBS, 1 V I/P 1 %
Luma Contrast Accuracy CVBS, 1 V I/P 1 %

Rev. B | Page 7 of 104

ADV7181
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating
temperature range, unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency 27.00 MHz
Frequency Stability ±50 ppm
I2C PORT
SCLK Frequency 400 kHz
SCLK Min Pulse Width High t1 0.6 µs
SCLK Min Pulse Width Low t2 1.3 µs
Hold Time (Start Condition) t3 0.6 µs
Setup Time (Start Condition) t4 0.6 µs
SDA Setup Time t5 100 ns
SCLK and SDA Rise Time t6 300 ns
SCLK and SDA Fall Time t7 300 ns
Setup Time for Stop Condition t8 0.6 µs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio t9:t10 45:55 55:45 % Duty Cycle
DATA AND CONTROL OUTPUTS
Data Output Transitional Time t11 Negative clock edge to start of valid data. 6 ns
(tACCESS = t10 – t11)
Data Output Transitional Time t12 End of valid data to negative clock edge. 0.6 ns
(tHOLD = t9 + t12)

ANALOG SPECIFICATIONS
Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V;
operating temperature range, unless otherwise noted. Recommended analog input video signal range: 0.5 V – 1.6 V, typically 1 V p-p.
Table 4.
Parameter Symbol Test Conditions Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 µF
Input Impedance Clamps switched off 10 MΩ
Large Clamp Source Current 0.75 mA
Large Clamp Sink Current 0.75 mA
Fine Clamp Source Current 60 µA
Fine Clamp Sink Current 60 µA

THERMAL SPECIFICATIONS
Table 5.
Parameter Symbol Test Conditions Min Typ Max Unit
THERMAL CHARACTERISTICS
Junction-to-Ambient Thermal θJA 4-layer PCB with solid ground plane, 64-lead LFCSP 45.5 °C/W
Resistance (Still Air)
Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane, 64-lead LFCSP 9.2 °C/W
Junction-to-Ambient Thermal θJA 4-layer PCB with solid ground plane, 64-lead LQFP 47 °C/W
Resistance (Still Air)
Junction-to-Case Thermal Resistance θJC 4-layer PCB with solid ground plane, 64-lead LQFP 11.1 °C/W

Rev. B | Page 8 of 104

 ADV7181
TIMING DIAGRAMS
t3 t5 t3

SDA

t6 t1
SCLK

04820-002
t2 t7 t4 t8

Figure 2. I2C Timing

t9 t10

OUTPUT LLC1

t11
t12

04820-003
OUTPUTS P0–P15, VS,
HS, FIELD, SFL

Figure 3. Pixel Port and Control Output Timing

Rev. B | Page 9 of 104

ADV7181

ABSOLUTE MAXIMUM RATINGS

Table 6. Stresses above those listed under Absolute Maximum Ratings
Parameter Rating may cause permanent damage to the device. This is a stress
AVDD to GND 4V rating only; functional operation of the device at these or any
AVDD to AGND 4V other conditions above those indicated in the operational
DVDD to DGND 2.2 V sections of this specification is not implied. Exposure to
PVDD to AGND 2.2 V absolute maximum rating conditions for extended periods may
DVDDIO to DGND 4V affect device reliability.
DVDDIO to AVDD –0.3 V to +0.3 V
PVDD to DVDD –0.3 V to +0.3 V
DVDDIO – PVDD –0.3 V to +2 V
DVDDIO – DVDD –0.3 V to +2 V
AVDD – PVDD –0.3 V to +2 V
AVDD – DVDD –0.3 V to +2 V
Digital Inputs Voltage to DGND –0.3 V to DVDDIO + 0.3 V
Digital Output Voltage to DGND –0.3 V to DVDDIO + 0.3 V
Analog Inputs to AGND AGND – 0.3 V to AVDD + 0.3 V
Maximum Junction Temperature 150°C
(TJ max)
Storage Temperature Range –65°C to +150°C
Infrared Reflow Soldering (20 s) 260°C

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 10 of 104

 ADV7181

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SDATA

RESET
DGND
FIELD

DVDD

SCLK

ALSB

AIN6
P12
P13
P14
P15

NC
NC

NC
VS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

NC 1 48 AIN5
PIN 1
HS 2 INDICATOR 47 AIN4
DGND 3 46 AIN3
DVDDIO 4 45 AGND
P11 5 44 CAPC2
P10 6 43 AGND
P9 7 42 CML
P8 8 ADV7181 41 REFOUT
SFL 9 TOP VIEW 40 AVDD
(Not to Scale)
DGND 10 39 CAPY2
DVDDIO 11 38 CAPY1
NC 12 37 AGND
NC 13 36 AIN2
P7 14 35 AIN1
P6 15 34 DGND
P5 16 33 NC

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

ELPF
P4
P3
P2

P1
P0
LLC

XTAL
DVDD
DGND

NC
NC

PVDD
AGND
XTAL1

PWRDN

04820-004
NC = NO CONNECT

Figure 4. 64-Lead LFCSP/LQFP Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type Function
3, 10, 24, 34, 57 DGND G Digital Ground.
32, 37, 43, 45 AGND G Analog Ground.
4, 11 DVDDIO P Digital I/O Supply Voltage (3.3 V).
23, 58 DVDD P Digital Core Supply Voltage (1.8 V).
40 AVDD P Analog Supply Voltage (3.3 V).
31 PVDD P PLL Supply Voltage (1.8 V).
35, 36, 46–49 AIN1–AIN6 I Analog Video Input Channels.
1, 12, 13, 27, 28, 33, NC No Connect Pins.
50, 55, 56
26, 25, 19, 18, 17, P0–P15 O Video Pixel Output Port.
16, 15, 14, 8, 7, 6, 5,
62, 61, 60, 59
2 HS O Horizontal Synchronization Output Signal.
64 VS O Vertical Synchronization Output Signal.
63 FIELD O Field Synchronization Output Signal.
53 SDA I/O I2C Port Serial Data Input/Output Pin.
54 SCLK I I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).
52 ALSB I This pin selects the I2C address for the ADV7181. ALSB set to a Logic 0 sets the address for a
write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
51 RESET I System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7181 circuitry.
20 LLC O This is a line-locked output clock for the pixel data output by the ADV7181. Nominally
27 MHz, but varies up or down according to video line length.
22 XTAL I This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

Rev. B | Page 11 of 104

ADV7181
Pin No. Mnemonic Type Function
21 XTAL1 O This pin should be connected to the 27 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7181. In crystal mode, the
crystal must be a fundamental crystal.
29 PWRDN I A logic low on this pin places the ADV7181 in a power-down mode. Refer to the I2C Control
Register Map section for more options on power-down modes for the ADV7181.
30 ELPF I The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 42.
9 SFL O Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital
video encoder.
41 REFOUT O Internal Voltage Reference Output. Refer to Figure 42 for a recommended capacitor
network for this pin.
42 CML O Common-Mode Level for the Internal ADCs. Refer to Figure 42 for a recommended
capacitor network for this pin.
38, 39 CAPY1, CAPY2 I ADC’s Capacitor Network. Refer to Figure 42 for a recommended capacitor network for
this pin.
44 CAPC2 I ADC’s Capacitor Network. Refer to Figure 42 for a recommended capacitor network for
this pin.

Rev. B | Page 12 of 104

 ADV7181

ANALOG FRONT END

ADC_SW_MAN_EN

AIN2
AIN1
AIN4
AIN3
AIN6
AIN5
AIN2
AIN1 ADC0_SW[3:0]
AIN4
AIN3
AIN6 ADC0
AIN5

AIN4
AIN3
AIN6 ADC1_SW[3:0]
AIN5

ADC1

AIN6
AIN5 ADC0_SW[3:0]

04820-005
ADC2

Figure 5. Internal Pin Connections

There are two key steps to configure the ADV7181 to correctly

SETADC_sw_man_en, Manual Input Muxing Enable,
decode the input video. Descriptions of these steps follow.
Address C4 [7]
• The analog input muxing section must be configured to ADC0_sw[3:0], ADC0 mux configuration, Address C3 [3:0]
correctly route the video from the analog input pins to the ADC1_sw[3:0], ADC1 mux configuration, Address C3 [7:4]
correct set of ADCs. ADC2_sw[3:0], ADC2 mux configuration, Address C4 [3:0]

• The standard definition processor block, which decodes To configure the ADV7181 analog muxing section, the user
the digital data, should be configured to process either must select the analog input (AIN1–AIN6) that is to be
CVBS, YC, or YPrPb. processed by each ADC. SETADC_sw_man_en must be set to 1
to enable the muxing blocks to be configured. The three mux
ANALOG INPUT MUXING sections are controlled by the signal buses ADC0/1/2_sw[3:0].
The ADV7181 has an integrated analog muxing section that Table 8 explains the control words used.
allows more than one source of video signal to be connected to
the decoder. Figure 5 outlines the overall structure of the input The input signal that contains the timing information (H/V
muxing provided in the ADV7181. syncs) must be processed by ADC0. For example, in YC input
configuration, ADC0 should be connected to the Y channel and
A maximum of six CVBS inputs can be connected and decoded ADC1 to the C channel. In cases where one or more ADCs are
by the ADV7181. As seen in the Pin Configuration and not used to process video, for example, CVBS input, the idle
Function Description section, these analog input pins lie in ADCs should be powered down, (see the ADC Power-Down
close proximity to one another. This calls for a careful design of Control section).
the PCB layout, for example, ground shielding between all
signals routed through tracks that are physically close together. Restrictions are imposed on the channel routing by the analog
It is strongly recommended to connect any unused analog input signal routing inside the IC; every input pin cannot be routed to
pins to AGND to act as a shield. each ADC. Refer to Table 8 for an overview on the routing
capabilities inside the chip.

Rev. B | Page 13 of 104

ADV7181
Table 8. Manual Mux Settings for All ADCs
SETADC_sw_man_en = 1
ADC0_sw[3:0] ADC0 Connected To: ADC1_sw[3:0] ADC1 Connected To: ADC2_sw[3:0] ADC2 Connected To:
0000 No Connection 0000 No Connection 0000 No Connection
0001 AIN2 0001 No Connection 0001 No Connection
0010 No Connection 0010 No Connection 0010 No Connection
0011 No Connection 0011 No Connection 0011 No Connection
0100 AIN4 0100 AIN4 0100 No Connection
0101 AIN6 0101 AIN6 0101 AIN6
0110 No Connection 0110 No Connection 0110 No Connection
0111 No Connection 0111 No Connection 0111 No Connection
1000 No Connection 1000 No Connection 1000 No Connection
1001 AIN1 1001 No Connection 1001 No Connection
1010 No Connection 1010 No Connection 1010 No Connection
1011 No Connection 1011 No Connection 1011 No Connection
1100 AIN3 1100 AIN3 1100 No Connection
1101 AIN5 1101 AIN5 1101 AIN5
1110 No Connection 1110 No Connection 1110 No Connection
1111 No Connection 1111 No Connection 1111 No Connection

CONNECTING
ANALOG SIGNALS INSEL[3:0] Input Selection, Address 0x00 [3:0]
TO ADV7181
The INSEL bits allow the user to select the input format. It
configures the Standard Definition Processor core to process
SET INSEL[3:0] TO
CONFIGURE ADV7181 TO
DECODE VIDEO FORMAT:
CVBS (Comp), S-Video (Y/C), or Component (YPbPr) format.
CVBS: 0000
YC: 0110 Table 9. Standard Definition Processor Format Selection,
YPrPb: 1001
INSEL[3:0]
INSEL[3:0] Video Format
CONFIGURE ADC INPUTS USING
MUXING CONTROL BITS 0000 Composite
04820-006

(ADC_sw_man_en,
ADC0_sw,adc1_sw, ADC2_sw) 0110 YC
1001 YPrPb
Figure 6. Input Muxing Overview

Rev. B | Page 14 of 104

 ADV7181

GLOBAL CONTROL REGISTERS

Register control bits listed in this section affect the whole chip. PWRDN_ADC_0, Address 0x3A [3]
Table 12. PWRDN_ADC_0 Function
POWER-SAVE MODES PWRDN_ADC_0 Description
Power-Down
0 (default) ADC normal operation.
PDBP, Address 0x0F [2] 1 Power down ADC 0.

There are two ways to shut down the digital core of the
ADV7181: a pin (PWRDN) and a bit (PWRDN see below). The PWRDN_ADC_1, Address 0x3A [2]
PDBP controls which of the two has the higher priority. The Table 13. PWRDN_ADC_1 Function
default is to give the pin (PWRDN) priority. This allows the PWRDN_ADC_1 Description
user to have the ADV7181 powered down by default. 0 (default) ADC normal operation.
Table 10. PDBP Function 1 Power down ADC 1.
PDBP Description
0 (default) Digital core power controlled by the PWRDN pin PWRDN_ADC_2, Address 0x3A [1]
(bit is disregarded).
Table 14. PWRDN_ADC_2 Function
1 Bit has priority (pin is disregarded).
PWRDN_ADC_2 Description
0 (default) ADC normal operation.
PWRDN, Address 0x0F [5] 1 Power down ADC 2.

Setting the PWRDN bit switches the ADV7181 into a chip-wide

power-down mode. The power-down stops the clock from RESET CONTROL
entering the digital section of the chip, thereby freezing its
Chip Reset (RES), Address 0x0F [7]
operation. No I2C bits are lost during power-down. The
PWRDN bit also affects the analog blocks and switches them Setting this bit, equivalent to controlling the RESET pin on the
into low current modes. The I2C interface itself is unaffected, ADV7181, issues a full chip reset. All I2C registers are reset to
and remains operational in power-down mode. their default values. (Some register bits do not have a reset value
specified. They keep their last written value. Those bits are
The ADV7181 leaves the power-down state if the PWRDN bit is marked as having a reset value of x in the register table.) After
set to 0 (via I2C), or if the overall part is reset using the RESET the reset sequence, the part immediately starts to acquire the
pin. incoming video signal.
PDBP must be set to 1 for the PWRDN bit to power down the Notes
ADV7181.
• After setting the RES bit (or initiating a reset via the pin),
Table 11. PWRDN Function
the part returns to the default mode of operation with
PWRDN Description
respect to its primary mode of operation. All I2C bits are
0 (default) Chip operational.
loaded with their default values, making this bit self-
1 ADV7181 in chip-wide power-down.
clearing.
ADC Power-Down Control • Executing a software reset takes approximately 2 ms.
The ADV7181 contains three 9-bit ADCs (ADC 0, ADC 1, and However, it is recommended to wait 5 ms before further
ADC 2). If required, it is possible to power down each ADC I2C writes are performed.
individually.
• The I2C master controller receives a no acknowledge
When should the ADCs be powered down? condition on the ninth clock cycle when chip reset is
implemented. See the MPU Port Description section.
• CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
Table 15. RES Function
• S-Video mode. ADC 2 should be powered down to save on RES Description
power consumption. 0 (default) Normal operation.
1 Start reset sequence.

Rev. B | Page 15 of 104

ADV7181
GLOBAL PIN CONTROL Timing Signals Output Enable
Three-State Output Drivers
TIM_OE, Address 0x04 [3]
TOD, Address 0x03 [6] The TIM_OE bit should be regarded as an addition to the TOD
This bit allows the user to three-state the output drivers of the bit. Setting it high forces the output drivers for HS, VS, and
ADV7181. FIELD into the active (that is, driving) state even if the TOD bit
is set. If set to low, the HS, VS, and FIELD pins are three-stated
Upon setting the TOD bit, the P15–P0, HS, VS, FIELD, and SFL depending on the TOD bit. This functionality is useful if the
pins are three-stated. decoder is to be used as a timing generator only. This may be
The timing pins (HS/VS/FIELD) can be forced active via the the case if only the timing signals are to be extracted from an
TIM_OE bit. For more information on three-state control, refer incoming signal, or if the part is in free-run mode where a
to the following sections: separate chip can output, for instance, a company logo.

For more information on three-state control, refer to the

• Three-State LLC Driver
following sections:
• Timing Signals Output Enable
• Three-State Output Drivers
Individual drive strength controls are provided via the
DR_STR_XX bits. • Three-State LLC Driver

Individual drive strength controls are provided via the

Table 16. TOD Function DR_STR_XX bits.
TOD Description
Table 18. TIM_OE Function
0 (default) Output drivers enabled.
TIM_OE Description
1 Output drivers three-stated.
0 (default) HS, VS, FIELD three-stated according to the
TOD bit.
Three-State LLC Driver 1 HS, VS, FIELD are forced active all the time. The
DR_STR_S[1:0] setting determines drive
strength.
TRI_LLC, Address 0x0E [6]
This bit allows the output drivers for the LLC pin of the Drive Strength Selection (Data)
ADV7181 to be three-stated. For more information on three-
state control, refer to the following sections: DR_STR[1:0] Address 0x04 [5:4]
For EMC and crosstalk reasons, it may be desirable to
• Three-State Output Drivers
strengthen or weaken the drive strength of the output drivers.
• Timing Signals Output Enable The DR_STR[1:0] bits affect the P[15:0] output drivers.

Individual drive strength controls are provided via the For more information on three-state control, refer to the
DR_STR_XX bits. following sections:
Table 17. TRI_LLC Function • Drive Strength Selection (Clock)
TRI_LLC Description
0 (default) LLC pin drivers working according to the • Drive Strength Selection (Sync)
DR_STR_C[1:0] setting (pin enabled).
1 LLC pin drivers three-stated. Table 19. DR_STR Function
DR_STR[1:0] Description
00 Low drive strength (1×).
01 (default) Medium low drive strength (2×).
10 Medium high drive strength (3×).
11 High drive strength (4×).

Rev. B | Page 16 of 104

 ADV7181
Drive Strength Selection (Clock) Enable Subcarrier Frequency Lock Pin

DR_STR_C[1:0] Address 0x0E [3:2] EN_SFL_PIN Address 0x04 [1]

The DR_STR_C[1:0] bits can be used to select the strength of The EN_SFL_PIN bit enables the output of subcarrier lock
the clock signal output driver (LLC pin). For more information, information (also known as GenLock) from the ADV7181 to an
refer to the following sections: encoder in a decoder-encoder back-to-back arrangement.
Table 22. EN_SFL_PIN
• Drive Strength Selection (Sync)
EN_SFL_PIN Description
• Drive Strength Selection (Data) 0 (default) Subcarrier frequency lock output is disabled.
1 Subcarrier frequency lock information is
presented on the SFL pin.
Table 20. DR_STR_C Function
DR_STR_C[1:0] Description
00 Low drive strength (1×). Polarity LLC Pin
01 (default) Medium low drive strength (2×).
10 Medium high drive strength (3×). PCLK Address 0x37 [0]
11 High drive strength (4×). The polarity of the clock that leaves the ADV7181 via the LLC
pin can be inverted using the PCLK bit.
Drive Strength Selection (Sync) Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
DR_STR_S[1:0] Address 0x0E [1:0] follow-on chips.
The DR_STR_S[1:0] bits allow the user to select the strength of Table 23. PCLK Function
the synchronization signals with which HS, VS, and F are
PCLK Description
driven. For more information, refer to the following sections:
0 Invert LLC output polarity.
• Drive Strength Selection (Clock) 1 (default) LLC output polarity normal (as per the Timing
Diagrams).
• Drive Strength Selection (Data)

Table 21. DR_STR_S Function

DR_STR_S[1:0] Description
00 Low drive strength (1×).
01 (default) Medium low drive strength (2×).
10 Medium high drive strength (3×).
11 High drive strength (4×).

Rev. B | Page 17 of 104

ADV7181

GLOBAL STATUS REGISTERS

Four registers provide summary information about the video Depending on the setting of the FSCLE bit, the Status[0] and
decoder. The IDENT register allows the user to identify the Status[1] are based solely on horizontal timing info or on the
revision code of the ADV7181. The other three registers contain horizontal timing and lock status of the color subcarrier. See the
status bits from the ADV7181. FSCLE Fsc Lock Enable, Address 0x51 [7] section.

IDENTIFICATION Autodetection Result

IDENT[7:0] Address 0x11 [7:0] AD_RESULT[2:0] Address 0x10 [6:4]

Provides identification of the revision of the ADV7181. Review The AD_RESULT[2:0] bits report back on the findings from the
the list of IDENT code readback values for the various versions autodetection block. Consult the General Setup sec-tion for
shown in Table 24. more information on enabling the autodetection block, and the
Autodetection of SD Modes section to find out how to
Table 24. IDENT Function configure it.
IDENT[7:0] Description
Table 25. AD_RESULT Function
0x0D ADV7181-ES1
AD_RESULT[2:0] Description
0x0E ADV7181-ES2
0x0F or 0x10 ADV7181-FT 000 NTSM-MJ
0x11 ADV7181 (Version 2) 001 NTSC-443
010 PAL-M
011 PAL-60
STATUS 1 100 PAL-BGHID
101 SECAM
STATUS_1[7:0] Address 0x10 [7:0]
110 PAL-Combination N
This read-only register provides information about the internal 111 SECAM 525
status of the ADV7181.

See CIL[2:0] Count Into Lock, Address 0x51 [2:0] and COL[2:0]
Count Out of Lock, Address 0x51 [5:3] for information on the
timing.

Table 26. STATUS 1 Function

STATUS 1 [7:0] Bit Name Description
0 IN_LOCK In lock (right now).
1 LOST_LOCK Lost lock (since last read of this register).
2 FSC_LOCK Fsc locked (right now).
3 FOLLOW_PW AGC follows peak white algorithm.
4 AD_RESULT.0 Result of autodetection.
5 AD_RESULT.1 Result of autodetection.
6 AD_RESULT.2 Result of autodetection.
7 COL_KILL Color kill active.

Rev. B | Page 18 of 104

 ADV7181
STATUS 2
STATUS_2[7:0], Address 0x12 [7:0]
Table 27. STATUS 2 Function
STATUS 2 [7:0] Bit Name Description
0 MVCS DET Detected Macrovision color striping.
1 MVCS T3 Macrovision color striping protection. Conforms to Type 3 (if high), and Type 2 (if low).
2 MV_PS DET Detected Macrovision pseudo sync pulses.
3 MV_AGC DET Detected Macrovision AGC pulses.
4 LL_NSTD Line length is nonstandard.
5 FSC_NSTD Fsc frequency is nonstandard.
6 Reserved
7 Reserved
STATUS 3
STATUS_3[7:0], Address 0x13 [7:0]
Table 28. STATUS 3 Function
STATUS 3 [7:0] Bit Name Description
0 INST_HLOCK Horizontal lock indicator (instantaneous).
1 Reserved
2 Reserved
3 Reserved
4 FREE_RUN_ACT ADV7181 outputs a blue screen (see the DEF_VAL_AUTO_EN Default Value Automatic
Enable, Address 0x0C [1] section).
5 STD_FLD_LEN Field length is correct for currently selected video standard.
6 INTERLACED Interlaced video detected (field sequence found).
7 PAL_SW_LOCK Reliable sequence of swinging bursts detected.

Rev. B | Page 19 of 104

ADV7181

STANDARD DEFINITION PROCESSOR (SDP)

STANDARD DEFINITION PROCESSOR

MACROVISION VBI DATA STANDARD SLLC

DETECTION RECOVERY AUTODETECTION CONTROL

LUMA
DIGITIZED CVBS DIGITAL LUMA GAIN LUMA LUMA
DIGITIZED Y (YC) FINE FILTER CONTROL RESAMPLE 2D COMB
CLAMP

LINE AV
SYNC RESAMPLE VIDEO DATA
LENGTH CODE
EXTRACT CONTROL OUTPUT
PREDICTOR INSERTION

CHROMA
DIGITIZED CVBS DIGITAL CHROMA CHROMA GAIN CHROMA CHROMA MEASUREMENT
DIGITIZED C (YC) FINE DEMOD FILTER CONTROL RESAMPLE 2D COMB BLOCK (= >12C)
CLAMP
VIDEO DATA
PROCESSING
BLOCK
FSC
RECOVERY

04820-007
Figure 7. Block Diagram of the Standard Definition Processor

A block diagram of the ADV7181’s standard definition SD CHROMA PATH

processor is shown in Figure 7. The input signal is processed by the following blocks:
The SDP block can handle standard definition video in CVBS, • Digital Fine Clamp. This block uses a high precision
YC, and YPrPb formats. It can be divided into a luminance and algorithm to clamp the video signal.
chrominance path. If the input video is of a composite type
(CVBS), both processing paths are fed with the CVBS input. • Chroma Demodulation. This block uses a color subcarrier
(Fsc) recovery unit to regenerate the color subcarrier for
SD LUMA PATH any modulated chroma scheme. The demodulation block
The input signal is processed by the following blocks: then performs an AM demodulation for PAL and NTSC,
and an FM demodulation for SECAM.
• Digital Fine Clamp. This block uses a high precision
algorithm to clamp the video signal. • Chroma Filter Block. This block contains a chroma
decimation filter (CAA) with a fixed response, and some
• Luma Filter Block. This block contains a luma decimation shaping filters (CSH) that have selectable responses.
filter (YAA) with a fixed response, and some shaping filters
(YSH) that have selectable responses. • Gain Control. Automatic gain control (AGC) can operate
on several different modes, including gain based on the
• Luma Gain Control. The automatic gain control (AGC) color subcarrier’s amplitude, gain based on the depth of the
can operate on a variety of different modes, including gain- horizontal sync pulse on the luma channel, or fixed manual
based on the depth of the horizontal sync pulse, peak white gain.
mode, and fixed manual gain.
• Chroma Resample. The chroma data is digitally resampled
• Luma Resample. To correct for line-length errors as well as to keep it perfectly aligned with the luma data. The
dynamic line-length changes, the data is digitally resampling is done to correct for static and dynamic line-
resampled. length errors of the incoming video signal.
• Luma 2D Comb. The two-dimensional comb filter • Chroma 2D Comb. The two-dimensional, 5-line,
provides YC separation. superadaptive comb filter provides high quality YC
• AV Code Insertion. At this point, the decoded luma (Y) separation in case the input signal is CVBS.
signal is merged with the retrieved chroma values. AV • AV Code Insertion. At this point, the demodulated chroma
codes (as per ITU-R. BT-656) can be inserted. (Cr and Cb) signal is merged with the retrieved luma
values. AV codes (as per ITU-R. BT-656) can be inserted.

Rev. B | Page 20 of 104

 ADV7181
SYNC PROCESSING GENERAL SETUP
The ADV7181 extracts syncs embedded in the video data Video Standard Selection
stream. There is currently no support for external HS/VS The VID_SEL[3:0] register allows the user to force the digital
inputs. The sync extraction has been optimized to support core into a specific video standard. Under normal circumstances,
imperfect video sources, for example, videocassette recorders this should not be necessary. The VID_SEL[3:0] bits default to
with head switches. The actual algorithm used employs a coarse an autodetection mode that supports PAL, NTSC, SECAM, and
detection based on a threshold crossing followed by a more variants thereof.
detailed detection using an adaptive interpolation algorithm.
Refer to the Autodetection of SD Modes section for more
The raw sync information is sent to a line-length measurement
information on the autodetection system.
and prediction block. The output is then used to drive the
digital resampling section to ensure that the ADV7181 outputs Autodetection of SD Modes
720 active pixels per line. In order to guide the autodetect system of the ADV7181,
individual enable bits are provided for each of the supported
The sync processing on the ADV7181 includes two specialized
video standards. Setting the relevant bit to 0 inhibits the
postprocessing blocks that filter and condition the raw sync
standard from being detected automatically. Instead, the system
information retrieved from the digitized analog video.
picks the closest of the remaining enabled standards. The results
• VSYNC processor. This block provides extra filtering of the of the autodetection can be read back via the status registers.
detected VSYNCs to give improved vertical lock. See the Global Status Registers section for more information.

• HSYNC processor. The HSYNC processor is designed to

filter incoming HSYNCs that have been corrupted by Table 29. VID_SEL Function
noise, providing much improved performance for video VID_SEL[3:0]
Address 0x00 [7:4] Description
signals with stable time base but poor SNR.
0000 (default) Autodetect (PAL BGHID) <–> NTSC J
VBI DATA RECOVERY (no pedestal), SECAM.
0001 Autodetect (PAL BGHID) <–> NTSC M
The ADV7181 can retrieve the following information from the (pedestal), SECAM.
input video: 0010 Autodetect (PAL N) <–> NTSC J (no
pedestal), SECAM.
• Wide-screen signaling (WSS)
0011 Autodetect (PAL N) <–> NTSC M
(pedestal), SECAM.
• Copy generation management system (CGMS)
0100 NTSC J (1)
• Closed caption (CC) 0101 NTSC M (1).
0110 PAL60.
• Macrovision protection presence 0111 NTSC4.43 (1).
1000 PAL BGHID.
• EDTV data
1001 PAL N (= PAL BGHID (with pedestal)).
• Gemstar-compatible data slicing 1010 PAL M (without pedestal).
1011 PAL M.
The ADV7181 is capable of automatically detecting the 1100 PAL combination N.
incoming video standard with respect to color subcarrier 1101 PAL combination N (with pedestal).
frequency, field rate, and line rate. 1110 SECAM.
1111 SECAM (with pedestal).
It can configure itself to support PAL-BGHID, PAL-M/N,
PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz,
NTSC4.43, and PAL60.

Rev. B | Page 21 of 104

ADV7181
AD_SEC525_EN Enable Autodetection of SECAM 525 AD_NTSC_EN Enable Autodetection of NTSC,
Line Video, Address 0x07 [7] Address 0x07 [1]
Table 30. AD_SEC525_EN Function Table 36. AD_NTSC_EN Function
AD_SEC525_EN Description AD_NTSC_EN Description
0 (default) Disable the autodetection of a 525-line 0 Disable the detection of standard NTSC.
system with a SECAM style, FM-modulated 1 (default) Enable the detection.
color component.
1 Enable the detection.
AD_PAL_EN Enable Autodetection of PAL,
Address 0x07 [0]
AD_SECAM_EN Enable Autodetection of SECAM, Table 37. AD_PAL_EN Function
Address 0x07 [6] AD_PAL_EN Description
Table 31. AD_SECAM_EN Function
0 Disable the detection of standard PAL.
AD_SECAM_EN Description 1 (default) Enable the detection.
0 Disable the autodetection of SECAM.
1 (default) Enable the detection. SFL_INV Subcarrier Frequency Lock Inversion
This bit controls the behavior of the PAL switch bit in the SFL
AD_N443_EN Enable Autodetection of NTSC443, (GenLock Telegram) data stream. It was implemented to solve
Address 0x07 [5] some compatibility issues with video encoders. It solves two
Table 32. AD_N443_EN Function problems:
AD_N443_EN Description
• The PAL switch bit is only meaningful in PAL. Some
0 Disable the autodetection of NTSC style
encoders (including Analog Devices encoders) also look
systems with a 4.43 MHz color subcarrier.
at the state of this bit in NTSC.
1 (default) Enable the detection.
• There was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the
AD_P60_EN Enable Autodetection of PAL60,
SFL (GenLock Telegram) bit directly, while the later ones
Address 0x07 [4]
invert the bit prior to using it. This is because the inversion
Table 33. AD_P60_EN Function
compensated for the 1-line delay of an SFL (GenLock
AD_P60_EN Description
Telegram) transmission.
0 Disable the autodetection of PAL systems
with a 60 Hz field rate. As a result:
1 (default) Enable the detection.
• ADV717x encoders need the PAL switch bit in the SFL
(GenLock Telegram) to be 1 for NTSC to work.
AD_PALN_EN Enable Autodetection of PAL N,
Address 0x07 [3] • ADV7190/ADV7191/ADV7194 encoders need the PAL
Table 34. AD_PALN_EN Function switch bit in the SFL to be 0 to work in NTSC.
AD_PALN_EN Description
If the state of the PAL switch bit is wrong, a 180°phase shift
0 Disable the detection of the PAL N standard.
occurs.
1 (default) Enable the detection.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
AD_PALM_EN Enable Autodetection of PAL M,
Address 0x07 [2] Table 38. SFL_INV Function
Table 35. AD_PALM_EN Function SFL_INV
AD_PALM_EN Description Address 0x41 [6] Description
0 Disable the autodetection of PAL M. 0 SFL-compatible with ADV7190/ADV7191/
ADV7194 encoders.
1 (default) Enable the detection.
1 (default) SFL-compatible with ADV717x/ADV7173x
encoders.

Rev. B | Page 22 of 104

 ADV7181
Lock Related Controls CIL[2:0] Count Into Lock, Address 0x51 [2:0]
Lock information is presented to the user through Bits [1:0] of CIL[2:0] determine the number of consecutive lines for which
the Status 1 register. See the STATUS_1[7:0] Address 0x10 [7:0] the into lock condition must be true before the system switches
section. Figure 8 outlines the signal flow and the controls into the locked state, and reports this via Status 0 [1:0].
available to influence the way the lock status information is Table 41. CIL Function
generated.
CIL[2:0] Description (Count Value in Lines of Video)
000 1
SRLS Select Raw Lock Signal, Address 0x51 [6] 001 2
Using the SRLS bit, the user can choose between two sources for 010 5
determining the lock status (per Bits [1:0] in the Status 1 register). 011 10
100 (default) 100
• The time_win signal is based on a line-to-line evaluation of 101 500
the horizontal synchronization pulse of the incoming 110 1000
video. It reacts quite quickly. 111 100000
• The free_run signal evaluates the properties of the
incoming video over several fields, and takes vertical COL[2:0] Count Out of Lock, Address 0x51 [5:3]
synchronization information into account.
COL[2:0] determine the number of consecutive lines for which
the out of lock condition must be true before the system switches
Table 39. SRLS Function into the unlocked state, and reports this via Status 0 [1:0].
SRLS Description
Table 42. COL Function
0 (default) Select the free_run signal.
COL[2:0] Description (Count Value in Lines of Video)
1 Select the time_win signal.
000 1
001 2
FSCLE Fsc Lock Enable, Address 0x51 [7] 010 5
011 10
The FSCLE bit allows the user to choose whether or not the
100 (default) 100
status of the color subcarrier loop is taken into account when
101 500
the overall lock status is determined and presented via Bits [1:0]
110 1000
in Status Register 1. This bit must be set to 0 when operating the
111 100000
ADV7181 in YPrPb component mode in order to generate a
reliable HLOCK status bit.
Table 40. FSCLE Function
FSCLE Description
0 Overall lock status only dependent on
horizontal sync lock.
1 (default) Overall lock status dependent on horizontal
sync lock and Fsc Lock.

SELECT THE RAW LOCK SIGNAL

SRLS FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]

TIME_WIN 1
0
FREE_RUN 0 COUNTER INTO LOCK STATUS 1 [0]
COUNTER OUT OF LOCK
1
FSC LOCK MEMORY STATUS 1 [1]
04820-008

TAKE FSC LOCK INTO ACCOUNT

FSCLE

Figure 8. Lock Related Signal Path

Rev. B | Page 23 of 104

ADV7181
COLOR CONTROLS
The following registers provide user control over the picture
SD_SAT_Cr[7:0] SD Saturation Cr Channel,
appearance, including control of the active data in the event of
Address 0xE4 [7:0]
video being lost. They are independent of any other controls.
For instance, brightness control is independent from picture This register allows the user to control the gain of the Cr
clamping, although both controls affect the signal’s dc level. channel only.

For this register to be active, SAT[7:0] must be programmed

CON[7:0] Contrast Adjust, Address 0x08 [7:0] with its default value of 0x80. If SAT[7:0] is programmed with a
This register allows the user to adjust the contrast of the picture. different value, SD_SAT_Cb[7:0] and SD_SAT_Cr[7:0] are
Table 43. CON Function inactive.
CON[7:0] Description Table 46. SD_SAT_Cr Function
(Adjust Contrast of the Picture) Description
0x80 (default) Gain on luma channel = 1. SD_SAT_Cr[7:0] (Adjust Saturation of the Picture)
0x00 Gain on luma channel = 0. 0x80 (default) Gain on Cr channel = 0 dB.
0xFF Gain on luma channel = 2. 0x00 Gain on Cr channel = –42 dB.
0xFF Gain on Cr channel = +6 dB.

SAT[7:0] Saturation Adjust, Address 0x09 [7:0]

The user can adjust the saturation of the color output using this SD_OFF_Cb[7:0] SD Offset Cb Channel, Address 0xE1 [7:0]
register. This register allows the user to select an offset for the Cb
channel only. There is a functional overlap with the Hue [7:0]
ADI encourages users not to use the SAT[7:0] register, which register.
may be removed in future revisions of the ADV7181. Instead,
the SD_SAT_Cb and SD_SAT_Cr registers should be used. Table 47.SD_OFF_Cb Function
Description
Table 44. SAT Function (Adjust Hue of the Picture by Selecting
SAT[7:0] Description SD_OFF_Cb[7:0] an Offset for Data on the Cb Channel)
(Adjust Saturation of the Picture) 0x80 (default) 0 offset applied to the Cb channel.
0x80 (default) Chroma gain = 0 dB. 0x00 –312 mV offset applied to the Cb channel.
0x00 Chroma gain = –42 dB. 0xFF +312 mV offset applied to the Cb channel.
0xFF Chroma gain = 6 dB.

SD_OFF_Cr [7:0] SD Offset Cr Channel, Address 0xE2 [7:0]

SD_SAT_Cb[7:0] SD Saturation Cb Channel,
This register allows the user to select an offset for the Cr
Address 0xE3 [7:0]
channel only. There is a functional overlap with the Hue [7:0]
This register allows the user to control the gain of the Cb register.
channel only.
Table 48. SD_OFF_Cr Function
For this register to be active, SAT[7:0] must be programmed Description
with its default value of 0x80. If SAT[7:0] is programmed with a (Adjust Hue of the Picture by Selecting
SD_OFF_Cr[7:0] an Offset for Data on Cr Channel)
different value, SD_SAT_Cb[7:0] and SD_SAT_Cr[7:0] are
inactive. 0x80 (default) 0 offset applied to the Cb channel.
0x00 –312 mV offset applied to the Cr channel.
Table 45. SD_SAT_Cb Function 0xFF +312 mV offset applied to the Cr channel.
Description
SD_SAT_Cb[7:0] (Adjust Saturation of the Picture)
0x80 (defualt) Gain on Cb channel = 0 dB.
0x00 Gain on Cb channel = –42 dB.
0xFF Gain on Cb channel = +6 dB.

Rev. B | Page 24 of 104

 ADV7181
BRI[7:0] Brightness Adjust, Address 0x0A [7:0] Table 51. DEF_Y Function
This register controls the brightness of the video signal through DEF_Y[5:0] Description
the ADV7181. 0x0D (blue) (default) Default value of Y.

Table 49. BRI Function

BRI[7:0] Description DEF_C[7:0] Default Value C, Address 0x0D [7:0]
(Adjust Brightness of the Picture)
The DEF_C[7:0] register complements the DEF_Y[5:0] value.
0x00 (default) Offset of the luma channel = 0IRE.
It defines the 4 MSBs of Cr and Cb values to be output if
0x7F Offset of the luma channel = 100IRE.
0x80 Offset of the luma channel = –100IRE. • The DEF_VAL_AUTO_EN bit is set to high and the
ADV7181 can’t lock to the input video (automatic mode).
HUE[7:0] Hue Adjust, Address 0x0B [7:0] • DEF_VAL_EN bit is set to high (forced output).
This register contains the value for the color hue adjustment.
The data that is finally output from the ADV7181 for the
HUE[7:0] has a range of ±90°, with 0x00 equivalent to an chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] =
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°. {DEF_C[3:0], 0, 0, 0, 0}.

The hue adjustment value is fed into the AM color demodulation Table 52. DEF_C Function
block. Therefore, it only applies to video signals that contain DEF_C[7:0] Description
chroma information in the form of an AM modulated carrier 0x7C (blue) (default) Default values for Cr and Cb.
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM and
does not work on component video inputs (YPrPb).
DEF_VAL_EN Default Value Enable, Address 0x0C [0]
Table 50. HUE Function
This bit forces the use of the default values for Y, Cr, and Cb.
HUE[7:0] Description (Adjust Hue of the Picture)
Refer to the descriptions for DEF_Y and DEF_C for additional
0x00 (default) Phase of the chroma signal = 0°. information. The decoder also outputs a stable 27 MHz clock,
0x7F Phase of the chroma signal = +90°. HS, and VS in this mode.
0x80 Phase of the chroma signal = –90°.
Table 53. DEF_VAL_EN Function
DEF_VAL_EN Description
DEF_Y[5:0] Default Value Y, Address 0x0C [7:2] 0 (default) Don't force the use of default Y, Cr, and
Cb values. Output colors dependent on
When the ADV7181 loses lock on the incoming video signal or
DEF_VAL_AUTO_EN.
when there is no input signal, the DEF_Y[5:0] register allows
1 Always use default Y, Cr, and Cb values.
the user to specify a default luma value to be output. Override picture data even if the video
decoder is locked.
This value is used under the following conditions:

• If DEF_VAL_AUTO_EN bit is set to high and the

DEF_VAL_AUTO_EN Default Value Automatic Enable,
ADV7181 lost lock to the input video signal. This is the
Address 0x0C [1]
intended mode of operation (automatic mode).
This bit enables the automatic usage of the default values for Y,
• The DEF_VAL_EN bit is set, regardless of the lock status of Cr, and Cb when the ADV7181 cannot lock to the video signal.
the video decoder. This is a forced mode that may be useful Table 54. DEF_VAL_AUTO_EN Function
during configuration.
DEF_VAL_AUTO_EN Description
The DEF_Y[5:0] values define the 6 MSBs of the output video. 0 Don't use default Y, Cr, and Cb values. If
unlocked, output noise.
The remaining LSBs are padded with 0s. For example, in 8-bit
1 (default) Use default Y, Cr, and Cb values when
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.
the decoder loses lock.

Rev. B | Page 25 of 104

ADV7181
CLAMP OPERATION
FINE COARSE
CURRENT CURRENT
SOURCES SOURCES

ANALOG DATA
SDP
VIDEO PRE
ADC PROCESSOR WITH DIGITAL
INPUT FINE CLAMP
(DPP)

04820-009
CLAMP CONTROL

Figure 9. Clamping Overview

The input video is ac-coupled into the ADV7181 through a The clamping scheme has to complete two tasks: it must be able
0.1 µF capacitor. It is recommended that the range of the input to acquire a newly connected video signal with a completely
video signal is 0.5 V to 1.6 V (typically 1 V p-p). If the signal unknown dc level, and it must maintain the dc level during
exceeds this range, it cannot be processed correctly in the normal operation.
decoder. Since the input signal is ac-coupled into the decoder,
its dc value needs to be restored. This process is referred to as For a fast acquiring of an unknown video signal, the large
clamping the video. This section explains the general process of current clamps may be activated. (It is assumed that the
clamping on the ADV7181 and shows the different ways in amplitude of the video signal at this point is of a nominal
which a user can configure its behavior. value.) Control of the coarse and fine current clamp parameters
is performed automatically by the decoder.
The ADV7181 uses a combination of current sources and a
digital processing block for clamping, as shown in Figure 9. Standard definition video signals may have excessive noise on
The analog processing channel shown is replicated three times them. In particular, CVBS signals transmitted by terrestrial
inside the IC. While only one single channel (and only one broadcast and demodulated using a tuner usually show very
ADC) would be needed for a CVBS signal, two independent large levels of noise (>100 mV). A voltage clamp would be
channels are needed for YC (S-VHS) type signals, and three unsuitable for this type of video signal. Instead, the ADV7181
independent channels are needed to allow component signals employs a set of four current sources that can cause coarse
(YPrPb) to be processed. (>0.5 mA) and fine (<0.1 mA) currents to flow into and away
from the high impedance node that carries the video signal (see
The clamping can be divided into two sections: Figure 9).

• Clamping before the ADC (analog domain): current The following sections describe the I2C signals that can be used
sources. to influence the behavior of the clamping.

• Clamping after the ADC (digital domain): digital Previous revisions of the ADV7181 had controls (FACL/FICL,
processing block. fast and fine clamp length) to allow configuration of the length
for which the coarse (fast) and fine current sources are switched
The ADCs can digitize an input signal only if it resides within on. These controls were removed on the ADV7181-FT and
the ADC’s 1.6 V input voltage range. An input signal with a dc replaced by an adaptive scheme.
level that is too large or too small is clipped at the top or bottom
of the ADC range. CCLEN Current Clamp Enable, Address 0x14 [4]
The primary task of the analog clamping circuits is to ensure The current clamp enable bit allows the user to switch off the
that the video signal stays within the valid ADC input window current sources in the analog front end altogether. This may be
so the analog-to-digital conversion can take place. It is not nec- useful if the incoming analog video signal is clamped externally.
essary to clamp the input signal with a very high accuracy in the Table 55. CCLEN Function
analog domain as long as the video signal fits the ADC range.
CCLEN Description
After digitization, the digital fine clamp block corrects for any 0 Current sources switched off.
remaining variations in dc level. Since the dc level of an input 1 (default) Current sources enabled.
video signal refers directly to the brightness of the picture
transmitted, it is important to perform a fine clamp with high
accuracy; otherwise, brightness variations may occur. Further-
more, dynamic changes in the dc level almost certainly lead to
visually objectionable artifacts, and must therefore be prohibited.

Rev. B | Page 26 of 104

 ADV7181
DCT[1:0] Digital Clamp Timing, Address 0x15 [6:5] video signal bandwidth (needed prior to scaling, for
The Clamp Timing register determines the time constant of the example). For some video sources that contain high
digital fine clamp circuitry. It is important to realize that the frequency noise, reducing the bandwidth of the luma
digital fine clamp reacts very fast since it is supposed to signal improves visual picture quality. A follow-on video
immediately correct any residual dc level error for the active compression stage may work more efficiently if the video is
line. The time constant of the digital fine clamp must be much low-pass filtered.
quicker than the one from the analog blocks.
The ADV7181 allows selection of two responses for the
By default, the time constant of the digital fine clamp is adjusted shaping filter: one that is used for good quality CVBS,
dynamically to suit the currently connected input signal. component, and S-VHS type sources, and a second for
Table 56. DCT Function nonstandard CVBS signals.
DCT[1:0] Description The YSH filter responses also include a set of notches for
00 Slow (TC = 1 sec). PAL and NTSC. However, it is recommended to use the
01 Medium (TC = 0.5 sec). comb filters for YC separation.
10 (default) Fast (TC = 0.1 sec).
11 Determined by ADV7181 depending on video • Digital resampling filter. This block is used to allow dynamic
parameters. resampling of the video signal to alter parameters such as
the time base of a line of video. Fundamentally, the resam-
pler is a set of low-pass filters. The actual response is chosen
DCFE Digital Clamp Freeze Enable, Address 0x15 [4] by the system with no requirement for user intervention.
This register bit allows the user to freeze the digital clamp loop
at any time. It is intended for users who would like to do their Figure 11 through Figure 14 show the overall response of all
own clamping. Users should disable the current sources for filters together. Unless otherwise noted, the filters are set into a
analog clamping via the appropriate register bits, wait until the typical wideband mode.
digital clamp loop settles, and then freeze it via the DCFE bit. Y Shaping Filter
Table 57. DCFE Function For input signals in CVBS format, the luma shaping filters play
DCFE Description an essential role in removing the chroma component from a
0 (default) Digital clamp operational. composite signal. YC separation must aim for best possible
1 Digital clamp loop frozen. crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
LUMA FILTER YC separation can be achieved by using the internal comb filters
of the ADV7181. Comb filtering, however, relies on the
Data from the digital fine clamp block is processed by three sets frequency relationship of the luma component (multiples of the
of filters. The data format at this point is CVBS for CVBS input video line rate) and the color subcarrier (Fsc). For good quality
or luma only for Y/C and YPrPb input formats. CVBS signals, this relationship is known; the comb filter
• Luma antialias filter (YAA). The ADV7181 receives video algorithms can be used to separate out luma and chroma with
at a rate of 27 MHz. (In the case of 4× oversampled video, high accuracy.
the ADCs sample at 54 MHz, and the first decimation is In the case of nonstandard video signals, the frequency
performed inside the DPP filters. Therefore, the data rate relationship may be disturbed and the comb filters may not be
into the ADV7181 is always 27 MHz.) The ITU-R BT.601 able to remove all crosstalk artifacts in an optimum fashion
recommends a sampling frequency of 13.5 MHz. The luma without the assistance of the shaping filter block.
antialias filter decimates the oversampled video using a
high quality, linear phase, low-pass filter that preserves the An automatic mode is provided. Here, the ADV7181 evaluates
luma signal while at the same time attenuating out-of-band the quality of the incoming video signal and selects the filter
components. The luma antialias filter (YAA) has a fixed responses in accordance with the signal quality and video
response. standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.
• Luma shaping filters (YSH). The shaping filter block is a
programmable low-pass filter with a wide variety of
responses. It can be used to selectively reduce the luma

Rev. B | Page 27 of 104

ADV7181
The luma shaping filter has three control registers: selections, for example, detected video standard, as well as
properties extracted from the incoming video itself, for example,
• YSFM[4:0] allows the user to manually select a shaping quality, time base stability. The automatic selection always picks
filter mode (applied to all video signals) or to enable an the widest possible bandwidth for the video input encountered.
automatic selection (depending on video quality and video
standard). • If the YSFM settings specify a filter (that is, YSFM is set to
values other than 00000 or 00001), the chosen filter is
• WYSFMOVR allows the user to manually override the applied to all video, regardless of its quality.
WYSFM decision.
• In automatic selection mode, the notch filters are only used
• WYSFM[4:0] allows the user to select a different shaping for bad quality video signals. For all other video signals,
filter mode for good quality CVBS, component (YPrPb), wideband filters are used.
and S-VHS (YC) input signals.
WYSFMOVR Wideband Y Shaping Filter Override,
In automatic mode, the system preserves the maximum possible
Address 0x18 [7]
bandwidth for good CVBS sources (since they can successfully
be combed) as well as for luma components of YPrPb and YC Setting the WYSFMOVR bit enables the use of the
sources, since they need not be combed. For poor quality WYSFM[4:0] settings for good quality video signals. For more
signals, the system selects from a set of proprietary shaping information, refer to the general discussion of the luma shaping
filter responses that complements comb filter operation in order filters in the Y Shaping Filter section and the flowchart shown
to reduce visual artifacts. in Figure 10.
Table 58. WYSFMOVR Function
The decisions of the control logic are shown in Figure 10.
WYSFMOVR Description
0 Automatic selection of shaping filter for good
YSFM[4:0] Y Shaping Filter Mode, Address 0x17 [4:0] quality video signals.
The Y shaping filter mode bits allow the user to select from a 1 (default) Enable manual override via WYSFM[4:0].
wide range of low-pass and notch filters. When switched in
automatic mode, the filter is selected based on other register

SET YSFM

YES YSFM IN AUTO MODE? NO

00000 OR 00001

VIDEO
QUALITY
BAD GOOD
USE YSFM SELECTED
FILTER REGARDLESS FOR
GOOD AND BAD VIDEO
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB WYSFMOVR

1 0

SELECT WIDEBAND
04820-010

SELECT AUTOMATIC
FILTER AS PER WIDEBAND FILTER
WYSFM[4:0]

Figure 10. YSFM and WYSFM Control Flowchart

Rev. B | Page 28 of 104

 ADV7181
Table 59. YSFM Function Table 60. WYSFM Function
YSFM[4:0] Description WYSFM[4:0] Description
0'0000 Automatic selection including a wide notch 0'0000 Do not use
response (PAL/NTSC/SECAM) 0'0001 Do not use
0'0001 Automatic selection including a narrow notch 0'0010 SVHS 1
(default) response (PAL/NTSC/SECAM) 0'0011 SVHS 2
0'0010 SVHS 1 0'0100 SVHS 3
0'0011 SVHS 2 0'0101 SVHS 4
0'0100 SVHS 3 0'0110 SVHS 5
0'0101 SVHS 4 0'0111 SVHS 6
0'0110 SVHS 5 0'1000 SVHS 7
0'0111 SVHS 6 0'1001 SVHS 8
0'1000 SVHS 7 0'1010 SVHS 9
0'1001 SVHS 8 0'1011 SVHS 10
0'1010 SVHS 9 0'1100 SVHS 11
0'1011 SVHS 10 0'1101 SVHS 12
0'1100 SVHS 11 0'1110 SVHS 13
0'1101 SVHS 12 0'1111 SVHS 14
0'1110 SVHS 13 1'0000 SVHS 15
0'1111 SVHS 14 1'0001 SVHS 16
1'0000 SVHS 15 1'0010 SVHS 17
1'0001 SVHS 16 1'0011 (default) SVHS 18 (CCIR 601)
1'0010 SVHS 17 1'0100–1’1111 Do not use
1'0011 SVHS 18 (CCIR 601)
1'0100 PAL NN 1 COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS,
Y RESAMPLE
1'0101 PAL NN 2
1'0110 PAL NN 3 0

1'0111 PAL WN 1
–10
1'1000 PAL WN 2
1'1001 NTSC NN 1 –20
AMPLITUDE (dB)

1'1010 NTSC NN 2
–30
1'1011 NTSC NN 3
1'1100 NTSC WN 1 –40
1'1101 NTSC WN 2
–50
1'1110 NTSC WN 3
1'1111 Reserved. –60

04820-011
–70
0 2 4 6 8 10 12
WYSFM[4:0] Wide Band Y Shaping Filter Mode, FREQUENCY (MHz)
Address 0x18 [4:0]
Figure 11. Y S-VHS Combined Responses
The WYSFM[4:0] bits allow the user to manually select a shaping
filter for good quality video signals, for example, CVBS with The filter plots in Figure 11 and Figure 22 show the
stable time base, luma component of YPrPb, luma component S-VHS 1 (narrowest) to S-VHS 18 (widest) shaping filter
of YC. The WYSFM bits are only active if the WYSFMOVR bit settings. Figure 13 shows the PAL notch filter responses.
is set to 1. See the general discussion of the shaping filter The NTSC-compatible notches are shown in Figure 14.
settings in the Y Shaping Filter section.

Rev. B | Page 29 of 104

ADV7181
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,
Y RESAMPLE CHROMA FILTER
0
Data from the digital fine clamp block is processed by three sets
of filters. The data format at this point is CVBS for CVBS
–20
inputs, chroma only for Y/C, or U/V interleaved for YPrPb
input formats.
AMPLITUDE (dB)

–40

• Chroma Anti-alias Filter (CAA). The ADV7181 over-

–60
samples the CVBS by a factor of 2 and the Chroma/PrPb
by a factor of 4. A decimating filter (CAA) is used to
–80
preserve the active video band and remove any out-of-
–100
band components. The CAA filter has a fixed response.

04820-012
• Chroma Shaping Filters (CSH). The shaping filter block
–120
0 2 4 6 8 10 12 (CSH) can be programmed to perform a variety of low-
FREQUENCY (MHz)
pass responses. It can be used to selectively reduce the
Figure 12. Y S-VHS 18 Extra Wideband Filter (CCIR 601-Compliant) bandwidth of the chroma signal for scaling or compression.

• Digital Resampling Filter. This block is used to allow

COMBINED Y ANTIALIAS, PAL NOTCH FILTERS,
Y RESAMPLE dynamic resampling of the video signal to alter parameters
0 such as the time base of a line of video. Fundamentally, the
resampler is a set of low-pass filters. The actual response is
–10
chosen by the system with no requirement for user
–20 intervention.
AMPLITUDE (dB)

–30 The plots in Figure 15 show the overall response of all filters
together.
–40

–50 CSFM[2:0] C Shaping Filter Mode, Address 0x17 [7]

–60
The C shaping filter mode bits allow the user to select from a
04820-013

range of low-pass filters for the chrominance signal. When

–70 switched into automatic mode, the widest filter is selected based
0 2 4 6 8 10 12
FREQUENCY (MHz) on the video standard/format and on user choice (see settings
000 and 001 in Table 61).
Figure 13. Pal Notch Filter Response
Table 61. CSFM Function
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
CSFM[2:0] Description
Y RESAMPLE
000 (default) Autoselect 1.5 MHz bandwidth
0 001 Autoselect 2.17 MHz bandwidth
010 SH1
–10
011 SH2
–20 100 SH3
AMPLITUDE (dB)

101 SH4
–30
110 SH5
–40 111 Wideband mode

–50
Figure 15 shows the responses of SH1 (narrowest) to SH5
–60 (widest) in addition to the wideband mode (in red).
04820-014

–70
0 2 4 6 8 10 12
FREQUENCY (MHz)

Figure 14. NTSC Notch Filter Response

Rev. B | Page 30 of 104

 ADV7181
COMBINED C ANTIALIAS, C SHAPING FILTER,
C RESAMPLER to this: the amplitude of the input signal and the dc level it
0 resides on. The dc level is set by the clamping circuitry (see the
Clamp Operation section).
–10
If the amplitude of the analog video signal is too high, clipping
ATTENUATION (dB)

–20 may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
–30 maximum supported amplitude of the video signal.

–40 The minimum supported amplitude of the input video is

determined by the ADV7181’s ability to retrieve horizontal and
–50 vertical timing and to lock to the color burst (if present).

04820-015
–60
There are two gain control units, one each for luma and chroma
0 1 2 3 4 5 6 data. Both can operate independently of each other. The
FREQUENCY (MHz)
chroma unit, however, can also take its gain value from the
Figure 15. Chroma Shaping Filter Responses luma path.
GAIN OPERATION Several AGC modes are possible; Table 62 summarizes them.
The gain control within the ADV7181 is done on a purely
digital basis. The input ADCs support a 9-bit range, mapped It is possible to freeze the automatic gain control loops. This
into a 1.6 V analog voltage range. Gain correction takes place causes the loops to stop updating. The AGC determined gain
after the digitization in the form of a digital multiplier. at the time of the freeze stays active until the loop is either
unfrozen or the gain mode of operation is changed.
There are several advantages of this architecture over the
commonly used PGA (programmable gain amplifier) before the The currently active gain from any of the modes can be read
ADCs; among them is the fact that the gain is now completely back. Refer to the description of the dual-function manual gain
independent of supply, temperature, and process variations. registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in
the Luma Gain and Chroma Gain sections.
As shown in Figure 16, the ADV7181 can decode a video signal
as long as it fits into the ADC window. There are two components
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7181)
MAXIMUM
VOLTAGE

SDP
DATA (GAIN SELECTION ONLY)
PRE
ADC
PROCESSOR
(DPP)
GAIN
04820-016

CONTROL
MINIMUM CLAMP
VOLTAGE LEVEL

Figure 16. Gain Control Overview

Table 62. AGC Modes
Input Video Type Luma Gain Chroma Gain
Any Manual gain luma. Manual gain chroma.
CVBS Dependent on horizontal sync depth. Dependent on color burst amplitude.
Taken from luma path.
Peak White Dependent on color burst amplitude.
Taken from luma path.
Y/C Dependent on horizontal sync depth. Dependent on color burst amplitude.
Taken from luma path.
Peak White. Dependent on color burst amplitude.
Taken from luma path.
YPrPb Dependent on horizontal sync depth. Taken from luma path.

Rev. B | Page 31 of 104

ADV7181
Luma Gain LG[11:0] Luma Gain, Address 0x2F [3:0]; Address 0x30 [7:0];
LMG[11:0] Luma Manual Gain, Address 0x2F [3:0];
LAGC[2:0] Luma Automatic Gain Control, Address 0x30 [7:0]
Address 0x2C [7:0]
Luma gain [11:0] is a dual-function register:
The luma automatic gain control mode bits select the mode of
operation for the gain control in the luma path. • If written to, a desired manual luma gain can be
programmed. This gain becomes active if the LAGC[2:0]
There are ADI internal parameters to customize the peak white mode is switched to manual fixed gain.
gain control. Contact ADI for more information.
Table 63. LAGC Function • Equation 1 shows how to calculate a desired gain.
LAGC[2:0] Description • If read back, this register returns the current gain value.
000 Manual fixed gain (use LMG[11:0]). Depending on the setting in the LAGC [2:0] bits, this is
001 AGC (blank level to sync tip). No override one of the following values:
through white peak.
010 (default) AGC (blank level to sync tip). Automatic o Luma manual gain value (LAGC [2:0] set to luma
override through white peak. manual gain mode).
011 Reserved.
100 Reserved. o Luma automatic gain value (LAGC [2:0] set to any of
101 Reserved. the automatic modes).
110 Reserved.
111 Freeze gain. Table 65. LG/LMG Function
LG[11:0]/LMG[11:0] Read/Write Description
LAGT[1:0] Luma Automatic Gain Timing, Address 0x2F [7:6] LMG[11:0] = X Write Manual gain for luma
path
The luma automatic gain timing register allows the user to LG[11:0] Read Actually used gain
influence the tracking speed of the luminance automatic gain
(0 < LG ≤ 4095)
control. This register has an effect only if the LAGC[2:0] Luma _ Gain = = 0...2 (1)
register is set to 001, 010, 011, or 100 (automatic gain control 2048
modes).
Example
If peak white AGC is enabled and active (see the
Program the ADV7181 into manual fixed gain mode with a
STATUS_1[7:0] Address 0x10 [7:0] section), the actual gain
desired gain of 0.89
update speed is dictated by the peak white AGC loop and, as a
result, the LAGT settings have no effect. As soon as the part 1. Use Equation 1 to convert the gain:
leaves peak white AGC, LAGT becomes relevant again. 0.89 × 2048 = 1822.72

The update speed for the peak white algorithm can be 2. Truncate to integer value:
customized by the use of internal parameters. Contact ADI 1822.72 = 1822
for more information. 3. Convert to hexadecimal:
Table 64. LAGT Function 1822d = 0x71E
LAGT[1:0] Description
4. Split into two registers and program:
00 Slow (TC = 2 s)
Luma Gain Control 1 [3:0] = 0x7
01 Medium (TC = 1 s) Luma Gain Control 2 [7:0] = 0x1E
10 Fast (TC = 0.2 s)
11 (default) Adaptive 5. Enable Manual Fixed Gain Mode:
Set LAGC[2:0] to 000

Rev. B | Page 32 of 104

 ADV7181
BETACAM Enable Betacam Levels, Address 0x01 [5] Table 67. PW_UPD Function
If YPrPb data is routed through the ADV7181, the automatic PW_UPD Description
gain control modes can target different video input levels, as 0 Update gain once per video line.
outlined in Table 70. The BETACAM bit is valid only if the 1 (default) Update gain once per field.
input mode is YPrPb (component). The BETACAM bit sets
the target value for AGC operation.
Chroma Gain
A review of the following sections is useful:
CAGC[1:0] Chroma Automatic Gain Control,
• SETADC_sw_man_en, Manual Input Muxing Enable, Address 0x2C [1:0]
Address C4 [7] to find how component video (YPrPb) can
The two bits of Color Automatic Gain Control mode select
be routed through the ADV7181.
the basic mode of operation for automatic gain control in the
• Video Standard Selection to select the various standards, chroma path.
for example, with and without pedestal. Table 68. CAGC Function
The automatic gain control (AGC) algorithms adjust the levels CAGC[1:0] Description
based on the setting of the BETACAM bit (see Table 66.). 00 Manual fixed gain (use CMG[11:0]).
01 Use luma gain for chroma.
Table 66. BETACAM Function 10 (default) Automatic gain (based on color burst).
BETACAM Description 11 Freeze chroma gain.
0 (default) Assuming YPrPb is selected as input format.
Selecting PAL with pedestal selects MII.
Selecting PAL without pedestal selects SMPTE. CAGT[1:0] Chroma Automatic Gain Timing,
Selecting NTSC with pedestal selects MII. Address 0x2D [7:6]
Selecting NTSC without pedestal selects SMPTE. The Chroma Automatic Gain Timing register allows the user
1 Assuming YPrPb is selected as input format. to influence the tracking speed of the chroma automatic gain
Selecting PAL with pedestal selects BETACAM. control. This register has an effect only if the CAGC[1:0]
Selecting PAL without pedestal selects BETACAM register is set to 10 (automatic gain).
variant.
Selecting NTSC with pedestal selects BETACAM. Table 69. CAGT Function
Selecting NTSC without pedestal selects BETACAM CAGT[1:0] Description
variant. 00 Slow (TC = 2 s)
01 Medium (TC = 1 s)
10 Fast (TC = 0.2 s)
PW_UPD Peak White Update, Address 0x2B [0] 11 (default) Adaptive
The peak white and average video algorithms determine the
gain based on measurements taken from the active video. The
PW_UPD bit determines the rate of gain change. LAGC[2:0]
must be set to the appropriate mode to enable the peak white or
average video mode in the first place. For more information,
refer to the LAGC[2:0] Luma Automatic Gain Control,
Address 0x2C [7:0] section.

Table 70. Betacam Levels

Name Betacam (mV) Betacam Variant (mV) SMPTE (mV) MII (mV)
Y Range 0 to 714 (incl. 7.5% pedestal) 0 to 714 0 to 700 0 to 700 (incl. 7.5% pedestal)
Pb and Pr Range –467 to +467 –505 to +505 –350 to +350 –324 to +324
Sync Depth 286 286 300 300

Rev. B | Page 33 of 104

ADV7181
CKE Color Kill Enable, Address 0x2B [6]
CG[11:0] Chroma Gain, Address 0x2D [3:0];
The Color Kill Enable bit allows the optional color kill function
Address 0x2E [7:0] CMG[11:0] Chroma Manual Gain,
to be switched on or off.
Address 0x2D [3:0]; Address 0x2E [7:0]
Chroma gain [11:0] is a dual-function register: For QAM-based video standards (PAL and NTSC) as well as
FM-based systems (SECAM), the threshold for the color kill
• If written to, a desired manual chroma gain can be decision is selectable via the CKILLTHR[2:0] bits.
programmed. This gain becomes active if the CAGC[1:0]
mode is switched to manual fixed gain. If color kill is enabled, and if the color carrier of the incoming
video signal is less than the threshold for 128 consecutive video
• Refer to Equation 2 for calculating a desired gain. lines, color processing is switched off (black and white output).
To switch the color processing back on, another 128 consecutive
• If read back, this register returns the current gain value. lines with a color burst greater than the threshold are required.
Depending on the setting in the CAGC[1:0] bits, this is one
of the following values: The color kill option only works for input signals with a modu-
lated chroma part. For component input (YPrPb), there is no
o Chroma manual gain value (CAGC[1:0] set to chroma color kill.
manual gain mode).
Table 72. CKE Function
o Chroma automatic gain value (CAGC[1:0] set to any CKE Description
of the automatic modes). 0 Color kill disabled.
1 (default) Color kill enabled.
Table 71. CG/CMG Function
CG[11:0]/CMG[11:0] Read/Write Description
CKILLTHR[2:0] Color Kill Threshold, Address 0x3D [6:4]
CMG[11:0] Write Manual gain for chroma
path. The CKILLTHR[2:0] bits allow the user to select a threshold
CG[11:0] Read Currently active gain. for the color kill function. The threshold only applies to QAM-
based (NTSC and PAL) or FM modulated (SECAM) video
standards.
(0 < CG ≤ 4095)
Chroma _ Gain = = 0...4 (2)
1024 To enable the color kill function, the CKE bit must be set. For
settings 000, 001, 010, and 011, chroma demodulation inside
Example the ADV7181 may not work satisfactorily for poor input video
signals.
Freezing the automatic gain loop and reading back the
CG[11:0] register results in a value of 0x47A. Table 73. CKILLTHR Function
Description
1. Convert the read back value to decimal: CKILLTHR[2:0] SECAM NTSC, PAL
0x47A = 1146d 000 No color kill Kill at < 0.5%
001 Kill at < 5% Kill at < 1.5%
2. Apply Equation 2 to convert the readback value:
010 Kill at < 7% Kill at < 2.5%
1146/1024 = 1.12
011 Kill at < 8% Kill at < 4.0%
100 (default) Kill at < 9.5% Kill at < 8.5%
101 Kill at < 15% Kill at < 16.0%
110 Kill at < 32% Kill at < 32.0%
111 Reserved for ADI internal use only. Do not
select.

Rev. B | Page 34 of 104

 ADV7181
CHROMA TRANSIENT IMPROVEMENT (CTI)
The signal bandwidth allocated for chroma is typically much CTI_AB_EN Chroma Transient Improvement Alpha Blend
smaller than that of luminance. In the past, this was a valid way Enable, Address 0x4D [1]
to fit a color video signal into a given overall bandwidth because The CTI_AB_EN bit enables an alpha-blend function within
the human eye is less sensitive to chrominance than to the CTI block. If set to 1, the alpha blender mixes the transient
luminance. improved chroma with the original signal. The sharpness of the
The uneven bandwidth, however, can lead to some visual alpha blending can be configured via the CTI_AB[1:0] bits.
artifact when it comes to sharp color transitions. At the border For the alpha blender to be active, the CTI block must be
of two bars of color, both components (luma and chroma) enabled via the CTI_EN bit.
change at the same time (see Figure 17). Due to the higher
bandwidth, the signal transition of the luma component is Table 75. CTI_AB_EN Function
usually a lot sharper than that of the chroma component. The CTI_AB_EN Description
color edge is not sharp but blurred, in the worst case, over 0 Disable CTI alpha blender.
several pixels. 1 (default) Enable CTI alpha-blend mixing function.

CTI_AB[1:0] Chroma Transient Improvement Alpha Blend,

LUMA SIGNAL WITH A
LUMA TRANSITION, ACCOMPANIED Address 0x4D [3:2]
SIGNAL BY A CHROMA TRANSITION
The CTI_AB[1:0] controls the behavior of alpha-blend circuitry
that mixes the sharpened chroma signal with the original one. It
thereby controls the visual impact of CTI on the output data.
ORIGINAL, "SLOW" CHROMA
DEMODULATED TRANSITION PRIOR TO CTI
CHROMA For CTI_AB[1:0] to become effective, the CTI block must be
04820-017

SIGNAL SHARPENED CHROMA

TRANSITION AT THE
OUTPUT OF CTI
enabled via the CTI_EN bit, and the alpha blender must be
switched on via CTI_AB_EN.
Figure 17. CTI Luma/Chroma Transition
Sharp blending maximizes the effect of CTI on the picture, but
The chroma transient improvement block examines the input can also increase the visual impact of small amplitude, high
video data. It detects transitions of chroma, and can be frequency chroma noise.
programmed to “steepen” the chroma edges in an attempt to
Table 76. CTI_AB Function
artificially restore lost color bandwidth. The CTI block,
however, only operates on edges above a certain threshold to CTI_AB[1:0] Description
ensure that noise is not emphasized. Care has been taken to 00 Sharpest mixing between sharpened and
original chroma signal.
ensure that edge ringing and undesirable saturation or hue
01 Sharp mixing.
distortion are avoided.
10 Smooth mixing.
Chroma transient improvements are needed primarily for 11 (default) Smoothest alpha blend function.
signals that experienced severe chroma bandwidth limitations.
For those types of signals, it is strongly recommended to enable
CTI_C_TH[7:0] CTI Chroma Threshold, Address 0x4E [7:0]
the CTI block via CTI_EN.
The CTI_C_TH[7:0] value is an unsigned, 8-bit number speci-
CTI_EN Chroma Transient Improvement Enable, fying how big the amplitude step in a chroma transition has to
Address 0x4D [0] be in order to be steepened by the CTI block. Programming a
small value into this register causes even smaller edges to be
The CTI_EN bit enables the CTI function. If set to 0, the CTI
steepened by the CTI block. Making CTI_C_TH[7:0] a large
block is inactive and the chroma transients are left untouched.
value causes the block to improve large transitions only.
Table 74. CTI_EN Function
Table 77. CTI_C_TH Function
CTI_EN Description
CTI_C_TH[7:0] Description
0 (default) Disable CTI.
0x08 (default) Threshold for chroma edges prior to CTI.
1 Enable CTI block.

Rev. B | Page 35 of 104

ADV7181
DIGITAL NOISE REDUCTION (DNR) COMB FILTERS
Digital noise reduction is based on the assumption that high The comb filters of the ADV7181 have been greatly improved to
frequency signals with low amplitude are probably noise, and automatically handle video of all types, standards, and levels of
that their removal therefore improves picture quality. quality. Two user registers are available to customize comb filter
operation.
DNR_EN Digital Noise Reduction Enable, Address 0x4D [5]
Depending on whichever video standard has been detected (by
The DNR_EN bit enables the DNR block or bypasses it.
autodetection) or selected (by manual programming), the
Table 78. DNR_EN Function NTSC or PAL configuration registers are used. In addition to
DNR_EN Description the bits listed in this section, there are some further ADI
0 Bypass DNR (disable). internal controls; contact ADI for more information.
1 (default) Enable digital noise reduction on the luma data. NTSC Comb Filter Settings
Used for NTSC-M/J CVBS inputs.
DNR_TH[7:0] DNR Noise Threshold, Address 0x50 [7:0]
NSFSEL[1:0] Split Filter Selection NTSC, Address 0x19 [3:2]
The DNR_TH[7:0] value is an unsigned 8-bit number used to
determine the maximum edge that is interpreted as noise and The NSFSEL[1:0] control selects how much of the overall signal
therefore blanked from the luma data. Programming a large bandwidth is fed to the combs. A narrow split filter selection
value into DNR_TH[7:0] causes the DNR block to interpret gives better performance on diagonal lines, but leaves more dot
even large transients as noise and remove them. The effect on crawl in the final output image. The opposite is true for selecting
the video data is therefore more visible. a wide bandwidth split filter.
Table 80. NSFSEL Function
Programming a small value causes only small transients to be
NSFSEL[1:0] Description
seen as noise and to be removed.
00 (default) Narrow
The recommended DNR_TH[7:0] setting for A/V inputs is 01 Medium
0x04, and the recommended DNR_TH[7:0] setting for tuner 10 Medium
inputs is 0x0A. 11 Wide
Table 79. DNR_TH Function
DNR_TH[7:0] Description CTAPSN[1:0] Chroma Comb Taps NTSC, Address 0x38 [7:6]
0x08 (default) Threshold for maximum luma edges to be Table 81. CTAPSN Function
interpreted as noise.
CTAPSN[1:0] Description
00 Do not use.
01 NTSC chroma comb adapts 3 lines (3 taps)
to 2 lines (2 taps).
10 (default) NTSC chroma comb adapts 5 lines (5 taps)
to 3 lines (3 taps).
11 NTSC chroma comb adapts 5 lines (5 taps)
to 4 lines (4 taps).

Rev. B | Page 36 of 104

 ADV7181
CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38 [5:3]
Table 82. CCMN Function
CCMN[2:0] Description
0xx (default) Adaptive comb mode. Adaptive 3-line chroma comb for CTAPSN = 01.
Adaptive 4-line chroma comb for CTAPSN = 10.
Adaptive 5-line chroma comb for CTAPSN = 11.
100 Disable chroma comb.
101 Fixed chroma comb (top lines of line memory). Fixed 2-line chroma comb for CTAPSN = 01.
Fixed 3-line chroma comb for CTAPSN = 10.
Fixed 4-line chroma comb for CTAPSN = 11.
110 Fixed chroma comb (all lines of line memory). Fixed 3-line chroma comb for CTAPSN = 01.
Fixed 4-line chroma comb for CTAPSN = 10.
Fixed 5-line chroma comb for CTAPSN = 11.
111 Fixed chroma comb (bottom lines of line memory). Fixed 2-line chroma comb for CTAPSN = 01.
Fixed 3-line chroma comb for CTAPSN = 10.
Fixed 4-line chroma comb for CTAPSN = 11.

YCMN[2:0] Luma Comb Mode NTSC, Address 0x38 [2:0]

Table 83. YCMN Function
YCMN[2:0] Description
0xx (default) Adaptive comb mode. Adaptive 3-line (3 taps) luma comb.
100 Disable luma comb. Use low-pass/notch filter; see the Y Shaping Filter section.
101 Fixed luma comb (top lines of line memory). Fixed 2-line (2 taps) luma comb.
110 Fixed luma comb (all lines of line memory). Fixed 3-line (3 taps) luma comb.
111 Fixed luma comb (bottom lines of line memory). Fixed 2-line (2 taps) luma comb.

Rev. B | Page 37 of 104

ADV7181
PAL Comb Filter Settings CTAPSP[1:0] Chroma Comb Taps PAL, Address 0x39 [7:6]
Used for PAL-B/G/H/I/D, PAL-M, PAL-Combinational N, Table 85. CTAPSP Function
PAL-60, and NTSC443 CVBS inputs. CTAPSP[1:0] Description
00 Do not use.
PSFSEL[1:0] Split Filter Selection PAL, Address 0x19 [1:0] 01 PAL chroma comb adapts 5 lines (3 taps) to
3 lines (2 taps); cancels cross luma only.
The NSFSEL[1:0] control selects how much of the overall signal 10 PAL chroma comb adapts 5 lines (5 taps) to
bandwidth is fed to the combs. A wide split filter selection 3 lines (3 taps); cancels cross luma and hue error
eliminates dot crawl, but shows imperfections on diagonal lines. less well.
The opposite is true for selecting a narrow bandwidth split filter. 11 (default) PAL chroma comb adapts 5 lines (5 taps) to
4 lines (4 taps); cancels cross luma and hue error
Table 84. PSFSEL Function well.
PSFSEL[1:0] Description
00 Narrow
01 (default) Medium
10 Wide
11 Widest

CCMP[2:0] Chroma Comb Mode PAL, Address 0x39 [5:3]

Table 86. CCMP Function
CCMP[2:0] Description
0xx (default) Adaptive comb mode. Adaptive 3-line chroma comb for CTAPSP = 01.
Adaptive 4-line chroma comb for CTAPSP = 10.
Adaptive 5-line chroma comb for CTAPSP = 11.
100 Disable chroma comb.
101 Fixed chroma comb (top lines of line memory). Fixed 2-line chroma comb for CTAPSP = 01.
Fixed 3-line chroma comb for CTAPSP = 10.
Fixed 4-line chroma comb for CTAPSP = 11.
110 Fixed chroma comb (all lines of line memory). Fixed 3-line chroma comb for CTAPSP = 01.
Fixed 4-line chroma comb for CTAPSP = 10.
Fixed 5-line chroma comb for CTAPSP = 11.
111 Fixed chroma comb (bottom lines of line memory). Fixed 2-line chroma comb for CTAPSP = 01.
Fixed 3-line chroma comb for CTAPSP = 10.
Fixed 4-line chroma comb for CTAPSP = 11.

YCMP[2:0] Luma Comb Mode PAL, Address 0x39 [2:0]

Table 87. YCMP Function
YCMP[2:0] Description
0xx (default) Adaptive comb mode. Adaptive 5 lines (3 taps) luma comb.
100 Disable luma comb. Use low-pass/notch filter; see the Y Shaping Filter section.
101 Fixed luma comb (top lines of line memory). Fixed 3 lines (2 taps) luma comb.
110 Fixed luma comb (all lines of line memory). Fixed 5 lines (3 taps) luma comb.
111 Fixed luma comb (bottom lines of line memory). Fixed 3 lines (2 taps) luma comb.

Rev. B | Page 38 of 104

 ADV7181
AV CODE INSERTION AND CONTROLS
This section describes the I2C-based controls that affect SD_DUP_AV Duplicate AV Codes, Address 0x03 [0]
Depending on the output interface width, it may be necessary to
• Insertion of AV codes into the data stream
duplicate the AV codes from the luma path into the chroma path.
• Data blanking during the vertical blank interval (VBI)
In an 8-bit-wide output interface (Cb/Y/Cr/Y interleaved data),
• The range of data values permitted in the output data the AV codes are defined as FF/00/00/AV, with AV being the
stream transmitted word that contains information about H/V/F.

• The relative delay of luma vs. chroma signals In this output interface mode, the following assignment takes
place: Cb = FF, Y = 00, Cr = 00, and Y = AV.
Some of the decoded VBI data is being inserted during the
horizontal blanking interval. See the Gemstar Data Recovery In a 16-bit output interface where Y and Cr/Cb are delivered via
section for more information. separate data buses, the AV code is over the whole 16 bits. The
SD_DUP_AV bit allows the user to double up the AV codes, so
the full sequence can be found on the Y bus as well as
BT656-4 ITU Standard BT-R.656-4 Enable, Address 0x04 [7]
(= duplicated) the Cr/Cb bus. See Figure 18.
The ITU has changed the position for toggling of the V bit
Table 89. SD_DUP_AV Function
within the SAV EAV codes for NTSC between revisions 3 and 4.
The BT656-4 standard bit allows the user to select an output SD_DUP_AV Description
mode that is compliant with either the previous or the new 0 AV codes in single fashion (to suit 8-bit
interleaved data output).
standard. For further information, review the standard at
1 AV codes duplicated (for 16-bit interfaces).
http://www.itu.int.

The standard change affects NTSC only and has no bearing on

VBI_EN Vertical Blanking Interval Data Enable,
PAL.
Address 0x03 [7]
Table 88. BT656-4 Function
The VBI enable bit allows data such as intercast and closed
BT656-4 Description
caption data to be passed through the luma channel of the
0 (default) BT656-3 Spec: V bit goes low at EAV of Lines 10
and 273. decoder with only a minimal amount of filtering. All data for
1 BT656-4 Spec: V bit goes low at EAV of Lines 20 Lines 1 to 21 is passed through and available at the output port.
and 283. The ADV7181 does not blank the luma data, and automatically
switches all filters along the luma data path into their widest
bandwidth. For active video, the filter settings for YSH and YPK
are restored.

Refer to the BL_C_VBI Blank Chroma during VBI section for

information on the chroma path.
Table 90. VBI_En Function
VBI_EN Description
0 (default) All video lines are filtered/scaled.
1 Only active video region is filtered/scaled.

SD_DUP_AV = 1 SD_DUP_AV = 0

16-BIT INTERFACE 16-BIT INTERFACE 8-BIT INTERFACE

Y DATA BUS FF 00 00 AV Y 00 AV Y
Cb/Y/Cr/Y
INTERLEAVED FF 00 00 AV Cb
04820-018

Cr/Cb DATA BUS FF 00 00 AV Cb FF 00 Cb

AV CODE SECTION

AV CODE SECTION AV CODE SECTION

Figure 18. AV Code Duplication Control

Rev. B | Page 39 of 104

ADV7181
BL_C_VBI Blank Chroma during VBI, Address 0x04 [2] LTA[1:0] Luma Timing Adjust, Address 0x27 [1:0]
Setting BL_C_VBI high, the Cr and Cb values of all VBI lines The Luma Timing Adjust register allows the user to specify a
get blanked. This is done so any data that comes during VBI is timing difference between chroma and luma samples.
not decoded as color and output through Cr and Cb. As a result,
it should be possible to send VBI lines into the decoder, then There is a certain functionality overlap with the CTA[2:0]
output them through an encoder again, undistorted. Without register.
this blanking, any wrongly decoded color is encoded by the For manual programming, use the following defaults:
video encoder; therefore, the VBI lines are distorted.
• CVBS input LTA[1:0] = 00
Table 91. BL_C_VBI Function
BL_C_VBI Description • YC input LTA[1:0] = 01
0 Decode and output color during VBI.
1 (default) Blank Cr and Cb values during VBI (no color, 0x80). • YPrPb input LTA[1:0] = 01

Table 94. LTA Function

RANGE Range Selection, Address 0x04 [0]
LTA[1:0] Description
AV codes (as per ITU-R BT-656, formerly known as CCIR-656) 00 (default) No delay.
consist of a fixed header made up of 0xFF and 0x00 values. 01 Luma 1 clk (37 ns) delayed.
These two values are reserved and therefore are not to be used 10 Luma 2clk (74 ns) early.
for active video. Additionally, the ITU also specifies that the 11 Luma 1 clk (37 ns) early.
nominal range for video should be restricted to values between
16 and 235 for luma and 16 to 240 for chroma.
CTA[2:0] Chroma Timing Adjust, Address 0x27 [5:3]
The RANGE bit allows the user to limit the range of values
output by the ADV7181 to the recommended value range. In The Chroma Timing Adjust register allows the user to specify a
any case, it is ensured that the reserved values of 255d (0xFF) timing difference between chroma and luma samples. This can
and 00d (0x00) are not presented on the output pins unless they be used to compensate for external filter group delay differences
are part of an AV code header. in the luma vs. chroma path, and to allow a different number of
pipeline delays while processing the video down-stream. Review
Table 92. RANGE Function this functionality together with the LTA[1:0] register.
RANGE Description
0 16 ≤ Y ≤ 235 16 ≤ C/P ≤ 240 The chroma can only be delayed/advanced in chroma pixel
1 (default) 1 ≤ Y ≤ 254 1 ≤ C/P ≤ 254 steps. One chroma pixel step is equal to two luma pixels. The
programmable delay occurs after demodulation, where one can
no longer delay by luma pixel steps.
AUTO_PDC_EN Automatic Programmed Delay Control,
Address 0x27 [6] For manual programming, use the following defaults:
Enabling the AUTO_PDC_EN function activates a function • CVBS input CTA[2:0] = 011
within the ADV7181 that automatically programs the LTA[1:0]
and CTA[2:0] to have the chroma and luma data match delays • YC input CTA[2:0] = 101
for all modes of operation. If set, manual registers LTA[1:0] and
• YPrPb input CTA[2:0] = 110
CTA[2:0] are not used by the ADV7181. If the automatic mode
is disabled (via setting the AUTO_PDC_EN bit to 0), the values
programmed into LTA[1:0] and CTA[2:0] registers take effect. Table 95. CTA Function
CTA[2:0] Description
Table 93. AUTO_PDC_EN Function
000 Not used.
AUTO_PDC_EN Description
001 Chroma + 2 chroma pixel (early).
0 Use LTA[1:0] and CTA[2:0] values for delaying
010 Chroma + 1 chroma pixel (early).
luma and chroma samples. Refer to the
LTA[1:0] Luma Timing Adjust, Address 0x27 011 (default) No delay.
[1:0] and CTA[2:0] Chroma Timing Adjust, 100 Chroma – 1 chroma pixel (late).
Address 0x27 [5:3] sections. 101 Chroma – 2 chroma pixel (late).
1 (default) The ADV7181 automatically determines the 110 Chroma – 3 chroma pixel (late).
LTA and CTA values to have luma and chroma 111 Not used.
aligned at the output.

Rev. B | Page 40 of 104

 ADV7181
SYNCHRONIZATION OUTPUT SIGNALS The position of this edge is controlled by placing a binary
HS Configuration number into HSE[10:0]. The number applied offsets the edge
The following controls allow the user to configure the behavior with respect to an internal counter that is reset to 0 immediately
of the HS output pin only: after EAV code FF,00,00,XY (see Figure 19). HSE is set to
00000000000b, which is 0 LLC1 clock cycles from count[0].
• Beginning of HS signal via HSB[10:0]
Table 97. HSE Function
• End of HS signal via HSE[10:0] HSE[9:0] Description
000 (default) HS pulse ends after HSE[10:0] pixel after falling
• Polarity of HS using PHS edge of HS.

HSB[10:0] HS Begin, Address 0x34 [6:4], Address 0x35 [7:0]

Example
The HS Begin and HS End registers allow the user to freely
1. To shift the HS towards active video by 20 LLC1s, add
position the HS output (pin) within the video line. The values
20 LLC1s to both HSB and HSE, that is, HSB[10:0] =
in HSB[10:0] and HSE[10:0] are measured in pixel units from
[00000010110], HSE[10:0] = [00000010100]
the falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal. 2. To shift the HS away from active video by 20 LLC1s, add
1696 LLC1s to both HSB and HSE (for NTSC), that is,
The position of this edge is controlled by placing a binary
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
number into HSB[10:0]. The number applied offsets the edge
(1696 is derived from the NTSC total number of pixels =
with respect to an internal counter that is reset to 0 immediately
1716)
after EAV code FF,00,00,XY (see Figure 19). HSB is set to
00000000010b, which is 2 LLC1 clock cycles from count[0]. To move 20 LLC1s away from active video is equal to sub-
Table 96. HSB Function tracting 20 from 1716 and adding the result in binary to both
HSB[10:0] Description HSB[10:0] and HSE[10:0].
0x002 The HS pulse starts after the HSB[10:0] pixel after
falling edge of HS. PHS Polarity HS, Address 0x37 [7]
The polarity of the HS pin can be inverted using the PHS bit.
HSE[10:0] HS End, Address 0x34 [2:0], Address 0x36 [7:0]
Table 98. PHS Function
The HS Begin and HS End registers allow the user to freely PHS Description
position the HS output (pin) within the video line. The values 0 (default) HS active high.
in HSB[10:0] and HSE[10:0] are measured in pixel units from 1 HS active low.
the falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal.
Table 99. HS Timing Parameters (see Figure 19)
HS to Active Video Active Video Total LLC1
HS Begin Adjust HS End Adjust (LLC1 Clock Cycles) Samples/Line Clock Cycles
Standard (HSB[10:0])1 (HSE[10:0])1 (C in Figure 19)1 (D in Figure 19) (E in Figure 19)
NTSC 00000000010b 00000000000b 272 720Y + 720C = 1440 1716
NTSC Square Pixel 00000000010b 00000000000b 276 640Y + 640C = 1280 1560
PAL 00000000010b 00000000000b 284 720Y + 720C = 1440 1728
1
Default.

LLC1

PIXEL Cr Y FF 00 00 XY 80 10 80 10 80 10 FF 00 00 XY Cb Y Cr Y Cb Y Cr
BUS
ACTIVE
VIDEO EAV H BLANK SAV ACTIVE VIDEO

HS

HSE[10:0] HSB[10:0]

4 LLC1 C D
04820-019

D
E E

Figure 19. HS Timing

Rev. B | Page 41 of 104

ADV7181
VS and FIELD Configuration
The following controls allow the user to configure the behavior HVSTIM Horizontal VS Timing, Address 0x31 [3]
of the VS and FIELD output pins, as well as the generation of The HVSTIM bit allows the user to select where the VS signal is
embedded AV codes: asserted within a line of video. Some interface circuitry may
require VS to go low while HS is low.
• ADV encoder-compatible signals via NEWAVMODE
Table 101. HVSTIM Function
• PVS, PF HVSTIM Description
0 (default) Start of line relative to HSE.
• HVSTIM
1 Start of line relative to HSB.
• VSBHO, VSBHE

• VSEHO, VSEHE VSBHO VS Begin Horizontal Position Odd, Address 0x32 [7]
The VSBHO and VSBHE bits select the position within a line at
• For NTSC control:
which the VS pin (not the bit in the AV code) becomes active.
o NVBEGDELO, NVBEGDELE, NVBEGSIGN, Some follow-on chips require the VS pin to change state only
NVBEG[4:0] when HS is high/low.
Table 102. VSBHO Function
o NVENDDELO, NVENDDELE, NVENDSIGN,
VSBHO Description
NVEND[4:0]
0 (default) VS pin goes high at the middle of a line of video
o NFTOGDELO, NFTOGDELE, NFTOGSIGN, (odd field).
NFTOG[4:0] 1 VS pin changes state at the start of a line (odd
field).
• For PAL control:

o PVBEGDELO, PVBEGDELE, PVBEGSIGN, VSBHE VS Begin Horizontal Position Even, Address 0x32 [6]
PVBEG[4:0] The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
o PVENDDELO, PVENDDELE, PVENDSIGN,
Some follow-on chips require the VS pin to change state only
PVEND[4:0]
when HS is high/low.
o PFTOGDELO, PFTOGDELE, PFTOGSIGN, Table 103. VSBHE Function
PFTOG[4:0] VSBHE Description
0 VS pin goes high at the middle of a line of video
NEWAVMODE New AV Mode, Address 0x31 [4] (even field).
Table 100. NEWAVMODE Function 1 (default) VS pin changes state at the start of a line (even
NEWAVMODE Description field).
0 EAV/SAV codes generated to suit ADI
encoders. No adjustments possible.
1 (default) Enable Manual Position of VSYNC, Field, and VSEHO VS End Horizontal Position Odd, Address 0x33 [7]
AV codes using 0x34 to 0x37 and 0xE5 to 0xEA. The VSEHO and VSEHE bits select the position within a line at
Default register settings are CCIR656 which the VS pin (not the bit in the AV code) becomes active.
compliant; see Figure 20 for NTSC and
Figure 25 for PAL. For recommended manual
Some follow-on chips require the VS pin to change state only
user settings, see Table 108 and Figure 21 for when HS is high/low.
NTSC; see Table 121 and Figure 26 for PAL. Table 104. VSEHO Function
VSEHO Description
0 VS pin goes low (inactive) at the middle of a line
of video (odd field).
1 (default) VS pin changes state at the start of a line (odd
field).

Rev. B | Page 42 of 104

 ADV7181
VSEHE VS End Horizontal Position Even, PVS Polarity VS, Address 0x37 [5]
Address 0x33 [6] The polarity of the VS pin can be inverted using the PVS bit.
The VSEHO and VSEHE bits select the position within a line at Table 106. PVS Function
which the VS pin (not the bit in the AV code) becomes active.
PVS Description
Some follow-on chips require the VS pin to change state only
0 (default) VS active high.
when HS is high/low.
1 VS active low.
Table 105. VSEHE Function
VSEHE Description
0 VS pin goes low (inactive) at the middle of a line of PF Polarity FIELD, Address 0x37 [3]
(default) video (even field). The polarity of the FIELD pin can be inverted using the PF bit.
1 VS pin changes state at the start of a line (even field).
Table 107. PF Function
PF Description
0 (default) FIELD active high.
1 FIELD active low.

FIELD 1

525 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 21 22
OUTPUT
VIDEO

NVBEG[4:0] = 0x5 NVEND[4:0] = 0x4 *BT.656-4

REG 0x04. BIT 7 = 1

NFTOG[4:0] = 0x3

FIELD 2
262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 283 284 285

OUTPUT
VIDEO

NVBEG[4:0] = 0x5 NVEND[4:0] = 0x4 *BT.656-4

REG 0x04. BIT 7 = 1

NFTOG[4:0] = 0x3
04820-020

*APPLIES IF NEMAVMODE = 0.
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.

Figure 20. NTSC Default (BT.656). The polarity of H, V, and F is embedded in the data.

Rev. B | Page 43 of 104

ADV7181
FIELD 1
525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 21 22
OUTPUT
VIDEO

HS
OUTPUT

VS
OUTPUT

FIELD NVBEG[4:0] = 0x0 NVEND[4:0] = 0x3

OUTPUT
NFTOG[4:0] = 0x5

FIELD 2
262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 284 285

OUTPUT
VIDEO

HS
OUTPUT

VS
OUTPUT

NVBEG[4:0] = 0x0 NVEND[4:0] = 0x3

FIELD

04820-021
OUTPUT
NFTOG[4:0] = 0x5

Figure 21. NTSC Typical VSync/Field Positions Using Register Writes in Table 108

Table 108. Recommended User Settings for NTSC (See Figure 21)
Register Register Name Write
0x31 VSync Field Control 1 0x12
0x32 VSync Field Control 2 0x81
0x33 VSync Field Control 3 0x84
0x37 Polarity 0x29
0xE5 NTSV_V_Bit_Beg 0x0
0xE6 NTSC_V_Bit_End 0x3
0xE7 NTSC_F_Bit_Tog 0x85

Rev. B | Page 44 of 104

 ADV7181
NVBEGSIGN NTSC VSync Begin Sign, Address 0xE5 [5]
1 NVBEGSIGN 0 Table 111. NVBEGSIGN Function
NVBEGSIGN Description
ADVANCE BEGIN OF DELAY BEGIN OF 0 Delay start of VSync. Set for user manual
VSYNC BY NVBEG[4:0] VSYNC BY NVBEG[4:0]
programming.
1 (default) Advance start of VSync. Not recommended
NOT VALID FOR USER
PROGRAMMING
for user programming.
ODD FIELD?
YES NO
NVBEG[4:0] NTSC VSync Begin, Address 0xE5 [4:0]
Table 112. NVBEG Function
NVBEGDELO NVBEGDELE NVBEG Description
00101 (default) NTSC VSync begin position.
1 0 0 1

For all NTSC/PAL VSync timing controls, both the V bit in the
ADDITIONAL ADDITIONAL
DELAY BY DELAY BY AV code and the VSync on the VS pin are modified.
1 LINE 1 LINE

1 NVENDSIGN 0

VSBHO VSBHE
ADVANCE END OF DELAY END OF VSYNC
VSYNC BY NVEND[4:0] BY NVEND[4:0]

1 0 0 1

NOT VALID FOR USER

ADVANCE BY ADVANCE BY PROGRAMMING
0.5 LINE 0.5 LINE
ODD FIELD?
YES NO
04820-022

VSYNC BEGIN
NVENDDELO NVENDDELE

Figure 22. NTSC VSync Begin

1 0 0 1
NVBEGDELO NTSC VSync Begin Delay on Odd Field,
Address 0xE5 [7] ADDITIONAL ADDITIONAL
DELAY BY DELAY BY
Table 109. NVBEGDELO Function 1 LINE 1 LINE

NVBEGDELO Description
0 (default) No delay.
1 Delay VSync going high on an odd field by a line VSEHO VSEHE
relative to NVBEG.
1 0 0 1

NVBEGDELE NTSC Vsync Begin Delay on Even Field,

ADVANCE BY ADVANCE BY
Address 0xE5 [6] 0.5 LINE 0.5 LINE
Table 110. NVBEGDELE Function
NVBEGDELE Description
04820-023

0 (default) No delay. VSYNC END

1 Delay VSync going high on an even field by a
line relative to NVBEG. Figure 23. NTSC VSync End

Rev. B | Page 45 of 104

ADV7181
NVENDDELO NTSC VSync End Delay on Odd Field,
Address 0xE6 [7] 1 NFTOGSIGN 0

Table 113. NVENDDELO Function

NVENDDELO Description ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
DELAY TOGGLE OF
FIELD BY NFTOG[4:0]
0 (default) No delay.
1 Delay VSync going low on an odd field by a
NOT VALID FOR USER
line relative to NVEND. PROGRAMMING

ODD FIELD?
YES NO
NVENDDELE NTSC VSync End Delay on Even Field,
Address 0xE6 [6]
Table 114. NVENDDELE Function NFTOGDELO NFTOGDELE

NVENDDELE Description
0 (default) No delay. 1 0 0 1

1 Delay VSync going low on an even field by a

line relative to NVEND ADDITIONAL ADDITIONAL
DELAY BY DELAY BY
1 LINE 1 LINE

NVENDSIGN NTSC VSync End Sign, Address 0xE6 [5]

Table 115. NVENDSIGN Function

04820-024
FIELD
NVENDSIGN Description TOGGLE

0 (default) Delay end of VSync. Set for user manual

Figure 24. NTSC FIELD Toggle
programming.
1 Advance end of VSync. Not recommended for
user programming. NFTOGSIGN NTSC Field Toggle Sign, Address 0xE7 [5]
Table 119. NFTOGSIGN Function
NFTOGSIGN Description
NVEND NTSC[4:0] VSync End, Address 0xE6 [4:0] 0 Delay field transition. Set for user manual
Table 116. NVEND Function programming.
NVEND Description 1 (default) Advance field transition. Not recommended
00100 (default) NTSC VSync end position. for user programming.

For all NTSC/PAL VSync timing controls, both the V bit in the NFTOG[4:0] NTSC Field Toggle, Address 0xE7 [4:0]
AV code and the VSync on the VS pin are modified. Table 120. NFTOG Function
NFTOG Description
NFTOGDELO NTSC Field Toggle Delay on Odd Field, 00011 (default) NTSC Field toggle position.
Address 0xE7 [7]
Table 117. NFTOGDELO Function For all NTSC/PAL Field timing controls, both the F bit in the
NFTOGDELO Description AV code and the Field signal on the FIELD/DE pin are modified.
0 (default) No delay.
Table 121. Recommended User Settings for PAL
1 Delay Field toggle/transition on an odd field
by a line relative to NFTOG. (see Figure 26)
Register Register Name Write
0x31 VSync Field Control 1 0x12
NFTOGDELE NTSC Field Toggle Delay on Even Field, 0x32 VSync Field Control 2 0x81
Address 0xE7 [6] 0x33 VSync Field Control 3 0x84
Table 118. NFTOGDELE Function 0x37 Polarity 0x29
NFTOGDELE Description
0xE8 PAL_V_Bit_Beg 0x1
0 No delay.
0xE9 PAL_V_Bit_End 0x4
1 (default) Delay Field toggle/transition on an even field by
0xEA PAL_F_Bit_Tog 0x6
a line relative to NFTOG.

Rev. B | Page 46 of 104

 ADV7181
FIELD 1

622 623 624 625 1 2 3 4 5 6 7 8 9 10 22 23 24

OUTPUT
VIDEO

PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4

F
PFTOG[4:0] = 0x3

FIELD 2
310 311 312 313 314 315 316 317 318 319 320 321 322 335 336 337
OUTPUT
VIDEO

PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4

04820-025
PFTOG[4:0] = 0x3

Figure 25. PAL Default (BT.656). The polarity of H, V, and F is embedded in the data.

FIELD 1
622 623 624 625 1 2 3 4 5 6 7 8 9 10 11 23 24
OUTPUT
VIDEO

HS
OUTPUT

VS
OUTPUT

PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4

FIELD
OUTPUT

PFTOG[4:0] = 0x6
FIELD 2
310 311 312 313 314 315 316 317 318 319 320 321 322 323 336 337

OUTPUT
VIDEO

HS
OUTPUT

VS
OUTPUT

PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4

FIELD
04820-026

OUTPUT
PFTOG[4:0] = 0x6

Figure 26. PAL Typical VSync/Field Positions Using Register Writes in Table 121

Rev. B | Page 47 of 104

ADV7181
PVBEG[4:0] PAL VSync Begin, Address 0xE8 [4:0]
1 PVBEGSIGN 0 Table 125. PVBEG Function
PVBEG Description
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
00101 (default) PAL VSync begin position.

NOT VALID FOR USER

For all NTSC/PAL VSync timing controls, both the V bit in the
PROGRAMMING AV code and the VSync on the VS pin are modified.
ODD FIELD?
YES NO
1 PVENDSIGN 0

PVBEGDELO PVBEGDELE ADVANCE END OF DELAY END OF VSYNC

VSYNC BY PVEND[4:0] BY PVEND[4:0]

1 0 0 1
NOT VALID FOR USER
PROGRAMMING
ADDITIONAL ADDITIONAL
DELAY BY DELAY BY ODD FIELD?
1 LINE 1 LINE
YES NO

PVENDDELO PVENDDELE
VSBHO VSBHE

1 0 0 1
1 0 0 1

ADDITIONAL ADDITIONAL
ADVANCE BY ADVANCE BY DELAY BY DELAY BY
0.5 LINE 0.5 LINE 1 LINE 1 LINE
04820-027

VSYNC BEGIN
VSEHO VSEHE

Figure 27. PAL VSync Begin

1 0 0 1

PVBEGDELO PAL VSync Begin Delay on Odd Field,

ADVANCE BY ADVANCE BY
Address 0xE8 [7] 0.5 LINE 0.5 LINE
Table 122. PVBEGDELO Function
PVBEGDELO Description

04820-028
0 (default) No delay. VSYNC END
1 Delay VSync going high on an odd field by a line
relative to PVBEG. Figure 28. PAL VSync End

PVBEGDELE PAL VSync Begin Delay on Even Field, PVENDDELO PAL VSync End Delay on Odd Field,
Address 0xE8 [6] Address 0xE9 [7]
Table 123. PVBEGDELE Function Table 126. PVENDDELO Function
PVBEGDELE Description PVENDDELO Description
0 No delay. 0 (default) No delay.
1 (default) Delay VSync going high on an even field by a line 1 Delay VSync going low on an odd field by a
relative to PVBEG. line relative to PVEND.

PVBEGSIGN PAL VSync Begin Sign, Address 0xE8 [5] PVENDDELE PAL VSync End Delay on Even Field,
Table 124. PVBEGSIGN Function Address 0xE9 [6]
PVBEGSIGN Description Table 127. PVENDDELE Function
0 Delay begin of VSync. Set for user manual PVENDDELE Description
programming. 0 (default) No delay.
1 (default) Advance begin of VSync. Not recommended for 1 Delay VSync going low on an even field by a line
user programming. relative to PVEND.

Rev. B | Page 48 of 104

 ADV7181
PVENDSIGN PAL VSync End Sign, Address 0xE9 [5]
Table 128. PVENDSIGN Function 1 PFTOGSIGN 0

PVENDSIGN Description
0 (default) Delay end of VSync. Set for user manual ADVANCE TOGGLE OF
FIELD BY PTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
programming.
1 Advance end of VSync. Not recommended
for user programming. NOT VALID FOR USER
PROGRAMMING

ODD FIELD?
YES NO
PVEND[4:0] PAL Vsync End, Address 0xE9,[4:0]
Table 129. PVEND Function
PVEND Description PFTOGDELO PFTOGDELE
10100 (default) PAL VSync end position.
1 0 0 1

For all NTSC/PAL VSync timing controls, both the V bit in the
ADDITIONAL ADDITIONAL
AV code and the VSync on the VS pin are modified. DELAY BY DELAY BY
1 LINE 1 LINE

PFTOGDELO PAL Field Toggle Delay on Odd Field,

Address 0xEA [7]

04820-029
Table 130. PFTOGDELO Function FIELD
TOGGLE
PFTOGDELO Description
0 (default) No delay. Figure 29. PAL F Toggle
1 Delay F toggle/transition on an odd field by SYNC PROCESSING
a line relative to PFTOG.
The ADV7181 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
PFTOGDELE PAL Field Toggle Delay on Even Field, from the digitized input video. If desired, the blocks can be
Address 0xEA [6] disabled via the following two I2C bits.
Table 131. PFTOGDELE Function
PFTOGDELE Description ENHSPLL Enable HSync Processor, Address 0x01 [6]
0 No delay.
The HSYNC processor is designed to filter incoming HSyncs
1 (default) Delay F toggle/transition on an even field by that have been corrupted by noise, providing improved per-
a line relative to PFTOG.
formance for video signals with stable time bases but poor SNR.

For CVBS PAL/NTSC, YC PAL/NTSC, enable the HSync

PFTOGSIGN PAL Field Toggle Sign, Address 0xEA [5]
processor. For SECAM, disable the HSync processor. For YPrPb
Table 132. PFTOGSIGN Function
signals, disable Hsync processor.
PFTOGSIGN Description
0 Delay Field transition. Set for user manual Table 134. ENHSPLL Function
programming. ENHSPLL Description
1 (default) Advance Field transition. Not recommended 0 Disable the HSync processor.
for user programming. 1 (default) Enable the HSync processor.

ENVSPROC Enable VSync Processor, Address 0x01 [3]

PFTOG PAL Field Toggle, Address 0xEA [4:0]
This block provides extra filtering of the detected VSyncs to
Table 133. PFTOG Function
give improved vertical lock.
PFTOG Description
00011 (default) PAL Field toggle position. Table 135. ENVSPROC Function
ENVSPROC Description
For all NTSC/PAL Field timing controls, the F bit in the AV 0 Disable VSync processor.
code and the Field signal on the FIELD/DE pin are modified. 1 (default) Enable VSync processor.

Rev. B | Page 49 of 104

ADV7181
VBI DATA DECODE CCAPD Closed Caption Detected, Address 0x90 [1]
The following low data rate VBI signals can be decoded by the Logic 1 for this bit indicates that the data in the CCAP1 and
ADV7181: CCAP2 registers is valid.

• Wide screen signaling (WSS) The CCAPD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
• Copy generation management systems (CGMS) bit matches the data transmitted.

• Closed captioning (CCAP) Table 137. CCAPD Function

CCAPD Description
• EDTV 0 No CCAP signals detected. Confidence in
decoded data is low.
• Gemstar 1×- and 2×-compatible data recovery 1 CCAP sequence detected. Confidence in
decoded data is high.
The presence of any of the above signals is detected and, if
applicable, a parity check is performed. The result of this testing EDTVD EDTV Sequence Detected, Address 0x90 [2]
is contained in a confidence bit in the VBI Info[7:0] register.
Users are encouraged to first examine the VBI Info register Logic 1 for this bit indicates that the data in the EDTV1, 2, 3
before reading the corresponding data registers. All VBI data registers is valid.
decode bits are read-only. The EDTVD bit goes high if the rising edge of the start bit is
All VBI data registers are double-buffered with the field signals. detected within a time window, and if the polarity of the parity
This means that data is extracted from the video lines and bit matches the data transmitted.
appears in the appropriate I2C registers with the next field Table 138. EDTVD Function
transition. They are then static until the next field. EDTVD Description
0 No EDTV sequence detected. Confidence in
The user should start an I2C read sequence with VS by first decoded data is low.
examining the VBI Info register. Then, depending on the data 1 EDTV sequence detected. Confidence in
detected, the appropriate data registers should be read. decoded data is high.

The data registers are filled with decoded VBI data even if their CGMSD CGMS-A Sequence Detected, Address 0x90 [3]
corresponding detection bits are low; it is likely that bits within
the decoded data stream are wrong. Logic 1 for this bit indicates that the data in the CGMS1, 2, 3
registers is valid. The CGMSD bit goes high if a valid CRC
Notes checksum has been calculated from a received CGMS packet.
Table 139. CGMSD Function
• The closed captioning data (CCAP) is available in the I2C
CGMSD Description
registers, and is also inserted into the output video data
stream during horizontal blanking. 0 No CGMS transmission detected, confidence
low.
• The Gemstar-compatible data is not available in the I2C 1 CGMS sequence decoded, confidence high.
registers, and is inserted into the data stream only during
horizontal blanking. CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2 [2]
For certain video sources, the CRC data bits may have an
WSSD Wide Screen Signaling Detected, Address 0x90 [0] invalid format. In such circumstances, the CRC checksum
validation procedure can be disabled. The CGMSD bit goes
Logic 1 for this bit indicates that the data in the WSS1 and
high if the rising edge of the start bit is detected within a time
WSS2 registers is valid.
window.
The WSSD bit goes high if the rising edge of the start bit is Table 140. CRC_ENABLE Function
detected within a time window, and if the polarity of the parity CRC_ENABLE Description
bit matches the data transmitted. 0 No CRC check performed. The CGMSD bit goes
Table 136. WSSD Function high if the rising edge of the start bit is detected
within a time window.
WSSD Description
1 (default) Use CRC checksum to validate the CGMS-A
0 No WSS detected. Confidence in decoded data is low. sequence. The CGMSD bit goes high for a valid
1 WSS detected. Confidence in decoded data is high. checksum. ADI recommended setting.

Rev. B | Page 50 of 104

 ADV7181
Wide Screen Signaling Data EDTV Data Registers

WSS1[7:0], Address 0x91 [7:0], EDTV1[7:0], Address 0x93 [7:0],

WSS2[7:0], Address 0x92 [7:0] EDTV2[7:0], Address 0x94 [7:0],
Figure 30 shows the bit correspondence between the analog EDTV3[7:0], Address 0x95 [7:0]
video waveform and the WSS1/WSS2 registers. WSS2[7:6] are Figure 31 shows the bit correspondence between the analog
undetermined and should be masked out by software. video waveform and the EDTV1/EDTV2/EDTV3 registers.

EDTV3[7:6] are undetermined and should be masked out by

software. EDTV3[5] is reserved for future use and, for now,
contains a 0. The three LSBs of the EDTV waveform are
currently not supported.

WSS1[7:0] WSS2[5:0]
0 1 2 3 4 5 6 7 0 1 2 3 4 5
RUN-IN START ACTIVE
SEQUENCE CODE VIDEO

11.0µs
38.4µs

04820-030
42.5µs

Figure 30. WSS Data Extraction

Table 141. WSS Access Information

Signal Name Register Location Address Register Default Value
WSS1 [7:0] WSS 1 [7:0] 145d 0x91 Readback Only
WSS2 [5:0] WSS 2 [5:0] 146d 0x92 Readback Only

EDTV1[7:0] EDTV2[7:0] EDTV3[5:0]

0 1 2

NOT SUPPORTED

3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5
04820-031

Figure 31. EDTV Data Extraction

Table 142. EDTV Access Information

Signal Name Register Location Address Register Default Value
EDTV1[7:0] EDTV 1 [7:0] 147d 0x93 Readback Only
EDTV2[7:0] EDTV 2 [7:0] 148d 0x94 Readback Only
EDTV3[7:0] EDTV 3 [7:0] 149d 0x95 Readback Only

Rev. B | Page 51 of 104

ADV7181
CGMS Data Registers Closed Caption Data Registers

CGMS1[7:0], Address 0x96 [7:0], CCAP1[7:0], Address 0x99 [7:0],

CGMS2[7:0], Address 0x97 [7:0], CCAP2[7:0], Address 0x9A [7:0]
CGMS3[7:0], Address 0x98 [7:0] Figure 33 shows the bit correspondence between the analog
Figure 32 shows the bit correspondence between the analog video waveform and the CCAP1/CCAP2 registers.
video waveform and the CGMS1/CGMS2/CGMS3 registers.
CGMS3[7:4] are undetermined and should be masked out by Notes
software. • CCAP1[7] contains the parity bit from the first word.
CCAP2[7] contains the parity bit from the second word.

• Refer to the GDECAD Gemstar Decode Ancillary Data

Format, Address 0x4C [0] section.

+100 IRE
REF CGMS1[7:0] CGMS2[7:0] CGMS3[3:0]
+70 IRE
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3

0 IRE
49.1µs ± 0.5µs
–40 IRE 11.2µs

04820-032
CRC SEQUENCE
2.235µs ± 20ns

Figure 32. CGMS Data Extraction

Table 143. CGMS Access Information

Signal Name Register Location Address Register Default Value
CGMS1[7:0] CGMS 1 [7:0] 150d 0x96 Readback Only
CGMS2[7:0] CGMS 2 [7:0] 151d 0x97 Readback Only
CGMS3[3:0] CGMS 3 [3:0] 152d 0x98 Readback Only

10.5 ± 0.25µs 12.91µs

7 CYCLES
OF 0.5035MHz
(CLOCK RUN-IN) CCAP1[7:0] CCAP2[7:0]

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
S
T P P
50 IRE A A A
R R R
T I I
T T
Y Y

BYTE 0 BYTE 1
40 IRE REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003µs
04820-033

27.382µs 33.764µs

Figure 33. Closed Caption Data Extraction

Table 144. CCAP Access Information

Signal Name Register Location Address Register Default Value
CCAP1[7:0] CCAP 1 [7:0] 153d 0x99 Readback Only
CCAP2[7:0] CCAP 2 [7:0] 154d 0x9A Readback Only

Rev. B | Page 52 of 104

 ADV7181
Letterbox Detection to come to a conclusion about the presence of letterbox
Incoming video signals may conform to different aspect ratios type video in software.
(16:9 wide screen of 4:3 standard). For certain transmissions in
LB_LCT[7:0] Letterbox Line Count Top, Address 0x9B [7:0];
the wide screen format, a digital sequence (WSS) is transmitted
LB_LCM[7:0] Letterbox Line Count Mid, Address 0x9C [7:0];
with the video signal. If a WSS sequence is provided, the aspect
LB_LCB[7:0] Letterbox Line Count Bottom,
ratio of the video can be derived from the digitally decoded bits
Address 0x9D [7:0]
WSS contains.
Table 145. LB_LCx Access Information
In the absence of a WSS sequence, letterbox detection can be Signal Name Address Register Default Value
used to find wide screen signals. The detection algorithm exam- LB_LCT[7:0] 0x9B Readback only
ines the active video content of lines at the start and end of a LB_LCM[7:0] 0x9C Readback only
field. The detection of black lines can indicate that the LB_LCB[7:0] 0x9D Readback only
currently shown picture is in wide screen format.
LB_TH[4:0] Letterbox Threshold Control, Address 0xDC [4:0]
The active video content (luminance magnitude) over a line of Table 146. LB_TH Function
video is summed together. At the end of a line, this accumulated LB_TH[4:0] Description
value is compared with a threshold, and a decision is made as to 01100 (default) Default threshold for detection of black lines.
whether or not a particular line is black. The threshold value 01101 to 10000 Increase threshold (need larger active video
needed may depend on the type of input signal; some control is content before identifying non-black lines).
provided via LB_TH[4:0]. 00000 to 01011 Decrease threshold (even small noise levels
can cause the detection of non-black lines).
Detection at the Start of a Field
The ADV7181 expects a section of at least six consecutive black LB_SL[3:0] Letterbox Start Line, Address 0xDD [7:4]
lines of video at the top of a field. Once those lines have been Table 147. LB_SL Function
detected, Register LB_LCT[7:0] reports back the number of
LB_SL[3:0] Description
black lines that were actually found. By default, the ADV7181
0100 (default) Letterbox detection is aligned with active
starts looking for those black lines in sync with the beginning of video. Window starts after the EDTV VBI data
active video, for example, straight after the last VBI video line. line. For example, 0100 = 23/286 (NTSC).
LB_SL[3:0] allows the user to set the start of letterbox detection 0001, 0010 For example, 0101 = 24/287 (NTSC).
from the beginning of a frame on a line-by-line basis. The
detection window closes in the middle of the field.
LB_EL[3:0] Letterbox End Line, Address 0xDD [3:0]
Detection at the End of a Field Table 148. LB_EL Function
LB_EL[3:0] Description
The ADV7181 expects at least six continuous lines of black
1101 (default) Letterbox detection ends with the last active
video at the bottom of a field before reporting back the number line of video on a field. For example, 1101 =
of lines actually found via the LB_LCB[7:0] value. The activity 262/ 525 (NTSC).
window for letterbox detection (end of field) starts in the mid- 0001,0010 For example, 1100 = 261/524 (NTSC).
dle of an active field. Its end is programmable via LB_EL[3:0].
Gemstar Data Recovery
Detection at the Midrange The Gemstar-compatible data recovery block (GSCD) supports
Some transmissions of wide screen video include subtitles 1× and 2× data transmissions. In addition, it can also serve as a
within the lower black box. If the ADV7181 finds at least two closed caption decoder. Gemstar-compatible data transmissions
black lines followed by some more nonblack video, for example, can only occur in NTSC. Closed caption data can be decoded in
the subtitle, and finally followed by the remainder of the bottom both PAL and NTSC.
black block, it reports back a midcount via LB_LCM[7:0].
When no subtitles are found, LB_LCM[7:0] reports the same The block is configured via I2C in the following way:
number as LB_LCB[7:0].
• GDECEL[15:0] allow data recovery on selected video lines
Notes on even fields to be enabled and disabled.
• There is a 2-field delay in the reporting of any line count • GDECOL[15:0] enable the data recovery on selected lines
parameters. for odd fields.
• There is no “letterbox detected” bit. The user is asked to
read the LB_LCT[7:0] and LB_LCB[7:0] register values and

Rev. B | Page 53 of 104

ADV7181
• GDECAD configures the way in which data is embedded Entries within the packet are as follows:
in the video data stream. The recovered data is not avail-
able through I2C, but is inserted into the horizontal • Fixed preamble sequence of 0x00, 0xFF, 0xFF.
blanking period of an ITU-R. BT656-compatible data
stream. The data format is intended to comply with the • Data identification word (DID). The value for the DID
recommendation by the International Telecommunications marking a Gemstar or CCAP data packet is 0x140
Union, ITU-R BT.1364. See Figure 34. For more informa- (10-bit value).
tion, see the ITU website at www.itu.ch.
• Secondary data identification word (SDID), which contains
The format of the data packet depends on the following criteria: information about the video line from which data was
retrieved, whether the Gemstar transmission was of 1× or
• Transmission is 1× or 2×. 2× format, and whether it was retrieved from an even or
• Data is output in 8-bit or 4-bit format (see the description odd field.
of the GDECAD Gemstar Decode Ancillary Data Format, • Data count byte, giving the number of user data-words that
Address 0x4C [0] bit). follow.
• Data is closed caption (CCAP) or Gemstar-compatible. • User data section.
Data packets are output if the corresponding enable bit is set
• Optional padding to ensure that the length of the user
(see the GDECEL and GDECOL descriptions) and if the
data-word section of a packet is a multiple of four bytes.
decoder detects the presence of data. This means that for video
(Requirement as set in ITU-R BT.1364.)
lines where no data has been decoded, no data packet is output
even if the corresponding line enable bit is set. • Checksum byte.
Each data packet starts immediately after the EAV code of the Table 149 lists the values within a generic data packet that is
preceding line. See Figure 34 and Table 149, which show the output by the ADV7181 in 8-bit format. In 8-bit systems,
overall structure of the data packet. Bits D1 and D0 in the data packets are disregarded.

DATA IDENTIFICATION SECONDARY DATA IDENTIFICATION

04820-034
DATA OPTIONAL PADDING CHECK
00 FF FF DID SDID USER DATA
COUNT BYTES SUM

PREAMBLE FOR ANCILLARY DATA USER DATA (4 OR 8 WORDS)

Figure 34. Gemstar and CCAP Embedded Data Packet (Generic)

Table 149. Generic Data Output Packet

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description
0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4 !EP EP EF 2X line[3:0] 0 0 SDID
5 !EP EP 0 0 0 0 DC[1] DC[0] 0 0 Data count (DC)
6 !EP EP 0 0 word1[7:4] 0 0 User data-words
7 !EP EP 0 0 word1[3:0] 0 0 User data-words
8 !EP EP 0 0 word2[7:4] 0 0 User data-words
9 !EP EP 0 0 word2[3:0] 0 0 User data-words
10 !EP EP 0 0 word3[7:4] 0 0 User data-words
11 !EP EP 0 0 word3[3:0] 0 0 User data-words
12 !EP EP 0 0 word4[7:4] 0 0 User data-words
13 !EP EP 0 0 word4[3:0] 0 0 User data-words
14 !CS[8] CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] 0 0 Checksum

Rev. B | Page 54 of 104

 ADV7181
Table 150. Data Byte Allocation
Raw Information Bytes User Data-Words
2× Retrieved from the Video Line GDECAD (Including Padding) Padding Bytes DC[1:0]
1 4 0 8 0 10
1 4 1 4 0 01
0 2 0 4 0 01
0 2 1 4 2 01

Notes • CS[8:2]. The checksum is provided to determine the

integrity of the ancillary data packet. It is calculated by
• DID. The data identification value is 0x140 (10-bit value). summing up D[8:2] of DID, SDID, the Data Count byte,
Care has been taken that in 8-bit systems, the 2 LSBs do and all UDWs, and ignoring any overflow during the
not carry vital information. summation. Since all data bytes that are used to calculate
• EP and !EP. The EP bit is set to ensure even parity on the the checksum have their 2 LSBs set to 0, the CS[1:0] bits
data-word D[8:0]. Even parity means there is always an are also always 0.
even number of 1s within the D[8:0] bit arrangement. This !CS[8] describes the logic inversion of CS[8]. The value
includes the EP bit. !EP describes the logic inverse of EP !CS[8] is included in the checksum entry of the data packet
and is output on D[9]. The !EP is output to ensure that the to ensure that the reserved values of 0x00 and 0xFF do not
reserved codes of 00 and FF cannot happen. occur.
• EF. Even field identifier. EF = 1 indicates that the data was Table 151 to Table 154 outline the possible data packages.
recovered from a video line on an even field.

• 2X. This bit indicates whether the data sliced was in Gemstar 2× Format, Half-Byte Output Mode
Gemstar 1× or 2× format. A high indicates 2× format. Half-byte output mode is selected by setting CDECAD = 0;
full-byte output mode is selected by setting CDECAD = 1.
• line[3:0]. This entry provides a code that is unique for each See the GDECAD Gemstar Decode Ancillary Data Format,
of the possible 16 source lines of video from which Address 0x4C [0] section.
Gemstar data may have been retrieved. Refer to Table 162
and Table 163. Gemstar 1× Format
• DC[1:0]. Data count value. The number of user data-words Half-byte output mode is selected by setting CDECAD = 0;
in the packet divided by 4. The number of user data-words full-byte output mode is selected by setting CDECAD = 1.
(UDW) in any packet must be an integral number of 4. See the GDECAD Gemstar Decode Ancillary Data Format,
Padding is required at the end, if necessary. (Requirement Address 0x4C [0] section.
as set in ITU-R BT.1364.) Refer to Table 150.

• The 2X bit determines whether the raw information

retrieved from the video line was 2 or 4 bytes. The state of
the GDECAD bit affects whether the bytes are transmitted
straight (that is, two bytes transmitted as two bytes) or
whether they are split into nibbles (that is, two bytes
transmitted as four half bytes). Padding bytes are then
added where necessary.

Rev. B | Page 55 of 104

ADV7181

Table 151. Gemstar 2× Data, Half-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description
0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4 !EP EP EF 1 line[3:0] 0 0 SDID
5 !EP EP 0 0 0 0 1 0 0 0 Data count
6 !EP EP 0 0 Gemstar word1[7:4] 0 0 User data-words
7 !EP EP 0 0 Gemstar word1[3:0] 0 0 User data-words
8 !EP EP 0 0 Gemstar word2[7:4] 0 0 User data-words
9 !EP EP 0 0 Gemstar word2[3:0] 0 0 User data-words
10 !EP EP 0 0 Gemstar word3[7:4] 0 0 User data-words
11 !EP EP 0 0 Gemstar word3[3:0] 0 0 User data-words
12 !EP EP 0 0 Gemstar word4[7:4] 0 0 User data-words
13 !EP EP 0 0 Gemstar word4[3:0] 0 0 User data-words
14 !CS[8] CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

Table 152. Gemstar 2× Data, Full-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description
0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4 !EP EP EF 1 line[3:0] 0 0 SDID
5 !EP EP 0 0 0 0 0 1 0 0 Data count
6 Gemstar word1[7:0] 0 0 User data-words
7 Gemstar word2[7:0] 0 0 User data-words
8 Gemstar word3[7:0] 0 0 User data-words
9 Gemstar word4[7:0] 0 0 User data-words
10 !CS[8] CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

Table 153. Gemstar 1× Data, Half-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description
0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4 !EP EP EF 0 line[3:0] 0 0 SDID
5 !EP EP 0 0 0 0 0 1 0 0 Data count
6 !EP EP 0 0 Gemstar word1[7:4] 0 0 User data-words
7 !EP EP 0 0 Gemstar word1[3:0] 0 0 User data-words
8 !EP EP 0 0 Gemstar word2[7:4] 0 0 User data-words
9 !EP EP 0 0 Gemstar word2[3:0] 0 0 User data-words
10 !CS[8] CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

Rev. B | Page 56 of 104

 ADV7181

Table 154. Gemstar 1× Data, Full-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description
0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4 !EP EP EF 0 line[3:0] 0 0 SDID
5 !EP EP 0 0 0 0 0 1 0 0 Data count
6 Gemstar word1[7:0] 0 0 User data-words
7 Gemstar word2[7:0] 0 0 User data-words
8 1 0 0 0 0 0 0 0 0 0 UDW padding 200h
9 1 0 0 0 0 0 0 0 0 0 UDW padding 200h
10 !CS[8] CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

Table 155. NTSC CCAP Data, Half-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description
0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4 !EP EP EF 0 1 0 1 1 0 0 SDID
5 !EP EP 0 0 0 0 0 1 0 0 Data count
6 !EP EP 0 0 CCAP word1[7:4] 0 0 User data-words
7 !EP EP 0 0 CCAP word1[3:0] 0 0 User data-words
8 !EP EP 0 0 CCAP word2[7:4] 0 0 User data-words
9 !EP EP 0 0 CCAP word2[3:0] 0 0 User data-words
10 !CS[8] CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

Table 156. NTSC CCAP Data, Full-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description
0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4 !EP EP EF 0 1 0 1 1 0 0 SDID
5 !EP EP 0 0 0 0 0 1 0 0 Data count
6 CCAP word1[7:0] 0 0 User data-words
7 CCAP word2[7:0] 0 0 User data-words
8 1 0 0 0 0 0 0 0 0 0 UDW padding 200h
9 1 0 0 0 0 0 0 0 0 0 UDW padding 200h
10 !CS[8] CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

NTSC CCAP Data Notes

Half-byte output mode is selected by setting CDECAD = 0; • NTSC closed caption data is sliced on line 21d on even and
the full-byte mode is enabled by CDECAD = 1. Refer to the odd fields. The corresponding enable bit has to be set high.
GDECAD Gemstar Decode Ancillary Data Format, See the GDECEL[15:0] Gemstar Decoding Even Lines,
Address 0x4C [0] section. The data packet formats are Address 0x48 [7:0]; Address 0x49 [7:0] and GDECOL[15:0]
shown in Table 155 and Table 156. Gemstar Decoding Odd Lines, Address 0x4A [7:0];
Address 0x4B [7:0] sections.

Rev. B | Page 57 of 104

ADV7181
PAL CCAP Data Notes

Half-Byte output mode is selected by setting CDECAD = 0, • PAL closed caption data is sliced from Lines 22 and 335.
full-byte output mode is selected by setting CDECAD = 1. The corresponding enable bits have to be set.
See the GDECAD Gemstar Decode Ancillary Data Format,
• See the GDECEL[15:0] Gemstar Decoding Even Lines,
Address 0x4C [0] section. Table 157 and Table 158 list the
Address 0x48 [7:0]; Address 0x49 [7:0] and GDECOL[15:0]
bytes of the data packet.
Gemstar Decoding Odd Lines, Address 0x4A [7:0];
Address 0x4B [7:0] sections.

Table 157. PAL CCAP Data, Half-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description
0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4 !EP EP EF 0 1 0 1 0 0 0 SDID
5 !EP EP 0 0 0 0 0 1 0 0 Data count
6 !EP EP 0 0 CCAP word1[7:4] 0 0 User data-words
7 !EP EP 0 0 CCAP word1[3:0] 0 0 User data-words
8 !EP EP 0 0 CCAP word2[7:4] 0 0 User data-words
9 !EP EP 0 0 CCAP word2[3:0] 0 0 User data-words
10 !CS[8] CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

Table 158. PAL CCAP Data, Full-Byte Mode

Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description
0 0 0 0 0 0 0 0 0 0 0 Fixed preamble
1 1 1 1 1 1 1 1 1 1 1 Fixed preamble
2 1 1 1 1 1 1 1 1 1 1 Fixed preamble
3 0 1 0 1 0 0 0 0 0 0 DID
4 !EP EP EF 0 1 0 1 0 0 0 SDID
5 !EP EP 0 0 0 0 0 1 0 0 Data Count
6 CCAP word1[7:0] 0 0 User data-words
7 CCAP word2[7:0] 0 0 User data-words
8 1 0 0 0 0 0 0 0 0 0 UDW padding 200h
9 1 0 0 0 0 0 0 0 0 0 UDW padding 200h
10 !CS[8] CS[8] CS[7] CS[6] CS[5] CS[4] CS[3] CS[2] CS[1] CS[0] Checksum

Rev. B | Page 58 of 104

 ADV7181
GDECEL[15:0] Gemstar Decoding Even Lines, GDECAD Gemstar Decode Ancillary Data Format,
Address 0x48 [7:0]; Address 0x49 [7:0] Address 0x4C [0]
The 16 bits of the GDECEL[15:0] are interpreted as a collection The decoded data from Gemstar-compatible transmissions or
of 16 individual line decode enable signals. Each bit refers to a closed caption is inserted into the horizontal blanking period of
line of video in an even field. Setting the bit enables the decoder the respective line of video. There is a potential problem if the
block trying to find Gemstar- or closed caption-compatible data retrieved data bytes have the value 0x00 or 0xFF. In an ITU-R
on that particular line. Setting the bit to 0 prevents the decoder BT.656-compatible data stream, those values are reserved and
from trying to retrieve data. See Table 162 and Table 163. used only to form a fixed preamble.

Notes The GDECAD bit allows the data to be inserted into the
horizontal blanking period in two ways:
• To retrieve closed caption data services on NTSC
(Line 284), GDECEL[11] must be set. • Insert all data straight into the data stream, even the
reserved values of 0x00 and 0xFF, if they occur. This
• To retrieve closed caption data services on PAL may violate the output data format specification ITU-R
(Line 335), GDECEL[14] must be set. BT.1364.

Table 159. GDECEL Function • Split all data into nibbles and insert the half-bytes over
double the number of cycles in a 4-bit format.
GDECEL[15:0] Description
0x0000 (default) Do not attempt to decode Gemstar-
compatible data or CCAP on any line (even Table 161. GDECAD Function
field). GDECAD Description
0 (default) Split data into half-bytes and insert.
1 Output data straight in 8-bit format.
GDECOL[15:0] Gemstar Decoding Odd Lines,
Address 0x4A [7:0]; Address 0x4B [7:0]
The 16 bits of the GDECOL[15:0] form a collection of 16
individual line decode enable signals. See Table 162 and
Table 163.

Notes

• To retrieve closed caption data services on NTSC (Line 21),

GDECOL[11] must be set.

• To retrieve closed caption data services on PAL (Line 22),

GDECOL[14] must be set.

Table 160. GDECOL Function

GDECOL[15:0] Description
0x0000 (default) Do not attempt to decode Gemstar-
compatible data or CCAP on any line (odd
field).

Rev. B | Page 59 of 104

ADV7181
Table 162. NTSC Line Enable Bits and Corresponding Table 163. PAL Line Enable Bits and Corresponding
Line Numbering Line Numbering
Line Number Line Number
line[3:0] (ITU-R BT.470) Enable Bit Comment line[3:0] (ITU-R BT.470) Enable Bit Comment
0 10 GDECOL[0] Gemstar 12 8 GDECOL[0] Not valid
1 11 GDECOL[1] Gemstar 13 9 GDECOL[1] Not valid
2 12 GDECOL[2] Gemstar 14 10 GDECOL[2] Not valid
3 13 GDECOL[3] Gemstar 15 11 GDECOL[3] Not valid
4 14 GDECOL[4] Gemstar 0 12 GDECOL[4] Not valid
5 15 GDECOL[5] Gemstar 1 13 GDECOL[5] Not valid
6 16 GDECOL[6] Gemstar 2 14 GDECOL[6] Not valid
7 17 GDECOL[7] Gemstar 3 15 GDECOL[7] Not valid
8 18 GDECOL[8] Gemstar 4 16 GDECOL[8] Not valid
9 19 GDECOL[9] Gemstar 5 17 GDECOL[9] Not valid
10 20 GDECOL[10] Gemstar 6 18 GDECOL[10] Not valid
11 21 GDECOL[11] Gemstar or 7 19 GDECOL[11] Not valid
closed caption 8 20 GDECOL[12] Not valid
12 22 GDECOL[12] Gemstar 9 21 GDECOL[13] Not valid
13 23 GDECOL[13] Gemstar 10 22 GDECOL[14] Closed caption
14 24 GDECOL[14] Gemstar 11 23 GDECOL[15] Not valid
15 25 GDECOL[15] Gemstar 12 321 (8) GDECEL[0] Not valid
0 273 (10) GDECEL[0] Gemstar 13 322 (9) GDECEL[1] Not valid
1 274 (11) GDECEL[1] Gemstar 14 323 (10) GDECEL[2] Not valid
2 275 (12) GDECEL[2] Gemstar 15 324 (11) GDECEL[3] Not valid
3 276 (13) GDECEL[3] Gemstar 0 325 (12) GDECEL[4] Not valid
4 277 (14) GDECEL[4] Gemstar 1 326 (13) GDECEL[5] Not valid
5 278 (15) GDECEL[5] Gemstar 2 327 (14) GDECEL[6] Not valid
6 279 (16) GDECEL[6] Gemstar 3 328 (15) GDECEL[7] Not valid
7 280 (17) GDECEL[7] Gemstar 4 329 (16) GDECEL[8] Not valid
8 281 (18) GDECEL[8] Gemstar 5 330 (17) GDECEL[9] Not valid
9 282 (19) GDECEL[9] Gemstar 6 331 (18) GDECEL[10] Not valid
10 283 (20) GDECEL[10] Gemstar 7 332 (19) GDECEL[11] Not valid
11 284 (21) GDECEL[11] Gemstar or 8 333 (20) GDECEL[12] Not valid
closed caption 9 334 (21) GDECEL[13] Not valid
12 285 (22) GDECEL[12] Gemstar 10 335 (22) GDECEL[14] Closed caption
13 286 (23) GDECEL[13] Gemstar 11 336 (23) GDECEL[15] Not valid
14 287 (24) GDECEL[14] Gemstar
15 288 (25) GDECEL[15] Gemstar

Rev. B | Page 60 of 104

 ADV7181

PIXEL PORT CONFIGURATION

The ADV7181 has a very flexible pixel port that can be config- SWPC Swap Pixel Cr/Cb, Address 0x27 [7]
ured in a variety of formats to accommodate downstream ICs. This bit allows Cr and Cb samples to be swapped.
Table 166 and Table 167 summarize the various functions that
the ADV7181’s pins can have in different modes of operation. Table 164. SWPC Function
SWPC Description
The ordering of components, for example, Cr vs. Cb, CHA/B/C, 0 (default) No swapping.
can be changed. Refer to the SWPC Swap Pixel Cr/Cb, Address 1 Swap Cr and Cb values.
0x27 [7] section. Table 166 indicates the default positions for
the Cr/Cb components.
LLC1 Output Selection, LLC_PAD_SEL[2:0],
OF_SEL[3:0] Output Format Selection, Address 0x03 [5:2] Address 0x8F [6:4]

There are several modes in which the ADV7181 pixel port The following I2C write allows the user to select between the
can be configured. These modes are under the control of LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
OF_SEL[3:0]. See Table 167 for details. The LLC2 signal is useful for LLC2-compatible wide bus
The default LLC frequency output on the LLC1 pin is approxi- (16-bit) output modes. See the OF_SEL[3:0] Output Format
mately 27 MHz. For modes that operate with a nominal data Selection, Address 0x03 [5:2] section for additional
rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 information. The LLC2 signal and data on the data bus are
pin stays at the higher rate of 27 MHz. For information on synchronized. By default, the rising edge of LLC1/LLC2 is
outputting the nominal 13.5 MHz clock on the LLC1 pin, see aligned with the Y data; the falling edge occurs when the data
the LLC1 Output Selection, LLC_PAD_SEL[2:0], bus holds C data. The polarity of the clock, and therefore the
Address 0x8F [6:4] section. Y/C assignments to the clock edges, can be altered by using the
Polarity LLC pin.
Table 165. LLC_PAD_SEL Function
LLC_PAD_SEL[2:0] Description
000 (default) Output nominal 27 MHz LLC on LLC1 pin.
101 Output nominal 13.5 MHz LLC on LLC1 pin.

Table 166. P15–P0 Output/Input Pin Mapping

Data Port Pins P[15:0]
Processor, Format, and Mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Video Out, 8-Bit, 4:2:2 YCrCb[7:0]OUT
Video Out, 16-Bit, 4:2:2 Y[7:0]OUT CrCb[7:0] OUT

Table 167. Standard Definition Pixel Port Modes

P[15: 0]
OF_SEL[3:0] Format P[15:8] P[7: 0]
0010 16-Bit @ LLC2 4:2:2 Y[7:0] CrCb[7:0]
0011 (default) 8-Bit @ LLC1 4:2:2 YCrCb[7:0] Three-State
0110-1111 Reserved. Reserved. Do not use.

Rev. B | Page 61 of 104

ADV7181

MPU PORT DESCRIPTION

The ADV7181 supports a 2-wire (I2C-compatible) serial inter- LSB of the first byte means that the master writes information
face. Two inputs, serial data SDA and serial clock SCLK, carry to the peripheral. Logic 1 on the LSB of the first byte means that
information between the ADV7181 and the system I2C master the master reads information from the peripheral.
controller. Each slave device is recognized by a unique address. The ADV7181 acts as a standard slave device on the bus. The
The ADV7181’s I2C port allows the user to set up and configure data on the SDA pin is eight bits long, supporting the 7-bit
the decoder and to read back captured VBI data. The ADV7181 addresses plus the R/W bit. The ADV7181 has 196 subaddresses
has four possible slave addresses for both read and write to enable access to the internal registers. It therefore interprets
operations, depending on the logic level on the ALSB pin. These the first byte as the device address and the second byte as the
four unique addresses are shown in Table 168. The ADV7181’s starting subaddress. The subaddresses auto-increment, allowing
ALSB pin controls Bit 1 of the slave address. By altering the data to be written to or read from the starting subaddress. A
ALSB, it is possible to control two ADV7181s in an application data transfer is always terminated by a stop condition. The user
without having a conflict with the same slave address. The LSB can also access any unique subaddress register on a one-by-one
(Bit 0) sets either a read or write operation. Logic 1 corresponds basis without updating all the registers.
to a read operation; Logic 0 corresponds to a write operation.
Table 168. I2C Address for ADV7181 Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
ALSB R/W Slave Address
sequence with normal read and write operations, they cause an
0 0 0x40
immediate jump to the idle condition. During a given SCLK
0 1 0x41
high period, the user should issue only one start condition, one
1 0 0x42
stop condition, or a single stop condition followed by a single
1 1 0x43
start condition. If an invalid subaddress is issued by the user,
the ADV7181 does not issue an acknowledge and returns to the
To control the device on the bus, a specific protocol must be idle condition.
followed. First, the master initiates a data transfer by establishing
a start condition, which is defined by a high-to-low transition If in auto-increment mode the user exceeds the highest
on SDA while SCLK remains high. This indicates that an subaddress, the following action is taken:
address/data stream follows. All peripherals respond to the start
1. In read mode, the highest subaddress register contents
condition and shift the next eight bits (7-bit address + R/W bit).
continue to be output until the master device issues a no-
The bits are transferred from MSB down to LSB. The peripheral
acknowledge. This indicates the end of a read. A no-
that recognizes the transmitted address responds by pulling the
acknowledge condition is when the SDA line is not pulled
data line low during the ninth clock pulse; this is known as an
low on the ninth pulse.
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is 2. In write mode, the data for the invalid byte is not loaded
where the device monitors the SDA and SCLK lines, waiting for into any subaddress register, a no acknowledge is issued by
the start condition and the correct transmitted address. The the ADV7181, and the part returns to the idle condition.
R/W bit determines the direction of the data. Logic 0 on the

SDATA

SCLOCK
04820-035

S 1–7 8 9 1–7 8 9 1–7 8 9 P

START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP

Figure 35. Bus Data Transfer

WRITE
SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P

LSB = 0 LSB = 1

READ
SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P
04820-036

S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) = NO-ACKNOWLEDGE BY SLAVE

P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER A(M) = NO-ACKNOWLEDGE BY MASTER

Figure 36. Read and Write Sequence

Rev. B | Page 62 of 104

 ADV7181
REGISTER ACCESSES I2C SEQUENCER
The MPU can write to or read from all of the ADV7181’s An I2C sequencer is used when a parameter exceeds eight bits,
registers, except those registers that are read-only or write-only. and is therefore distributed over two or more I2C registers, for
The Subaddress register determines which register the next read example, HSB [11:0].
or write operation accesses. All communications with the part
through the bus start with an access to the Subaddress register. When such a parameter is changed using two or more I2C write
Then a read/write operation is performed from/to the target operations, the parameter may hold an invalid value for the
address, which increments to the next address until a stop time between the first I2C finishing and the last I2C being
command on the bus is performed. completed. In other words, the top bits of the parameter may
already hold the new value while the remaining bits of the
REGISTER PROGRAMMING parameter still hold the previous value.
The following sections describe each register in terms of its
configuration. The Communications register is an 8-bit, write- To avoid this problem, the I2C sequencer holds the already
only register. After the part has been accessed over the bus and updated bits of the parameter in local memory; all bits of the
a read/write operation is selected, the subaddress is set up. The parameter are updated together once the last register write
Subaddress register determines to/from which register the operation has completed.
operation takes place. Table 170 lists the various operations The correct operation of the I2C sequencer relies on the
under the control of the Subaddress register for the control following:
port.
Register Select (SR7-SR0) • All I2C registers for the parameter in question must be
written to in order of ascending addresses, for example, for
These bits are set up to point to the required starting address.
HSB[10:0], write to Address 0x34 first, followed by 0x35.

• No other I2C taking place between the two (or more) I2C
writes for the sequence, for example, for HSB[10:0], write
to Address 0x34 first, immediately followed by 0x35.

Rev. B | Page 63 of 104

ADV7181
I2C CONTROL REGISTER MAP
Table 169. Control Port Register Map Details
Subaddress Subaddress
Register Name Reset Value rw Dec Hex Register Name Reset Value rw Dec Hex
Input Control 0000 0000 rw 0 00 Gemstar Ctrl 3 0000 0000 rw 74 4A
Video Selection 1100 1000 rw 1 01 Gemstar Ctrl 4 0000 0000 rw 75 4B
Reserved 0000 0100 rw 2 02 GemStar Ctrl 5 xxxx xxx0 rw 76 4C
Output Control 0000 1100 rw 3 03 CTI DNR Ctrl 1 1110 1111 rw 77 4D
Extended Output Control 0101 0101 rw 4 04 CTI DNR Ctrl 2 0000 1000 rw 78 4E
Reserved 0000 0000 rw 5 05 Reserved xxxx xxxx rw 79 4F
Reserved 0000 0010 rw 6 06 CTI DNR Ctrl 4 0000 1000 rw 80 50
Autodetect Enable 0111 1111 rw 7 07 Lock Count 1010 0100 rw 81 51
Contrast 1000 0000 rw 8 08 Reserved xxxx xxxx rw 82–142 52–8E
Reserved 1000 0000 rw 9 09 Free Run Line Length 1 0000 0000 w 143 8F
Brightness 0000 0000 rw 10 0A Reserved 0000 0000 w 144 90
Hue 0000 0000 rw 11 0B VBI Info xxxx xxxx r 144 90
Default Value Y 0011 0110 rw 12 0C WSS 1 xxxx xxxx r 145 91
Default Value C 0111 1100 rw 13 0D WSS 2 xxxx xxxx r 146 92
ADI Control 0000 0101 rw 14 0E EDTV 1 xxxx xxxx r 147 93
Power Management 0000 0000 rw 15 0F EDTV 2 xxxx xxxx r 148 94
Status 1 xxxx xxxx r 16 10 EDTV 3 xxxx xxxx r 149 95
Ident xxxx xxxx r 17 11 CGMS 1 xxxx xxxx r 150 96
Status 2 xxxx xxxx r 18 12 CGMS 2 xxxx xxxx r 151 97
Status 3 xxxx xxxx r 19 13 CGMS 3 xxxx xxxx r 152 98
Analog Clamp Control 0001 0010 rw 20 14 CCAP 1 xxxx xxxx r 153 99
Digital Clamp Control 1 0100 xxxx rw 21 15 CCAP 2 xxxx xxxx r 154 9A
Reserved xxxx xxxx rw 22 16 Letterbox 1 xxxx xxxx r 155 9B
Shaping Filter Control 0000 0001 rw 23 17 Letterbox 2 xxxx xxxx r 156 9C
Shaping Filter Control 2 1001 0011 rw 24 18 Letterbox 3 xxxx xxxx r 157 9D
Comb Filter Control 1111 0001 rw 25 19 Reserved xxxx xxxx rw 158-177 9E–B1
Reserved xxxx xxxx rw 26–38 1A–26 CRC Enable 0001 1100 w 178 B2
Pixel Delay Control 0101 1000 rw 39 27 Reserved xxxx xxxx rw 179–194 B2–C2
Reserved xxxx xxxx rw 40 28–2A ADC Switch 1 xxxx xxxx rw 195 C3
Misc Gain Control 1110 0011 rw 43 2B ADC Switch 2 0xxx xxxx rw 196 C4
AGC Mode Control 1010 1110 rw 44 2C Reserved xxxx xxxx rw 197–219 C5–DB
Chroma Gain Control 1 1111 0100 rw 45 2D Letterbox Control 1 1010 1100 rw 220 DC
Chroma Gain Control 2 0000 0000 rw 46 2E Letterbox Control 2 0100 1100 rw 221 DD
Luma Gain Control 1 1111 xxxx rw 47 2F Reserved 0000 0000 rw 222 DE
Luma Gain Control 2 xxxx xxxx rw 48 30 Reserved 0000 0000 rw 223 DF
VSync Field Control 1 0001 0010 rw 49 31 Reserved 0001 0100 rw 224 E0
VSync Field Control 2 0100 0001 rw 50 32 SD Offset Cb 1000 0000 rw 225 E1
VSync Field Control 3 1000 0100 51 33 SD Offset Cr 1000 0000 rw 226 E2
HSync Position Control 1 0000 0000 rw 52 34 SD Saturation Cb 1000 0000 rw 227 E3
HSync Position Control 2 0000 0010 rw 53 35 SD Saturation Cr 1000 0000 rw 228 E4
HSync Position Control 3 0000 0000 rw 54 36 NTSC V Bit Begin 0010 0101 rw 225 E5
Polarity 0000 0001 rw 55 37 NTSC V Bit End 0000 0100 rw 226 E6
NTSC Comb Control 1000 0000 rw 56 38 NTSC F Bit Toggle 0110 0011 rw 227 E7
PAL Comb Control 1100 0000 rw 57 39 PAL V Bit Begin 0110 0101 rw 225 E8
ADC Control 0001 0000 rw 58 3A PAL V Bit End 0001 0100 rw 226 E9
Reserved xxxx xxxx rw 59–60 3B–3C PAL F Bit Toggle 0110 0011 rw 227 EA
Manual Window Control 0100 0011 rw 61 3D
Reserved 0101 0000 rw 62–70 3E–47
Gemstar Ctrl 1 00000000 rw 72 48
Gemstar Ctrl 2 0000 0000 rw 73 49

Rev. B | Page 64 of 104

 ADV7181
Table 170. Control Port Register Map Bit Details
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Input Control VID_SEL.3 VID_SEL.2 VID_SEL.1 VID_SEL.0 INSEL.3 INSEL.2 INSEL.1 INSEL.0
Video Selection ENHSPLL BETACAM ENVSPROC
Reserved
Output Control VBI_EN TOD OF_SEL.3 OF_SEL.2 OF_SEL.1 OF_SEL.0 SD_DUP_AV
Extended Output BT656-4 DR_STR.1 DR_STR.0 TIM_OE BL_C_VBI EN_SFL_PI RANGE
Control
Reserved
Reserved
Autodetect Enable AD_SEC525_EN AD_SECAM_EN AD_N443_EN AD_P60_EN AD_PALN_EN AD_PALM_EN AD_NTSC_EN AD_PAL_EN
Contrast CON.7 CON.6 CON.5 CON.4 CON.3 CON.2 CON.1 CON.0
Reserved
Brightness BRI.7 BRI.6 BRI.5 BRI.4 BRI.3 BRI.2 BRI.1 BRI.0
Hue HUE.7 HUE.6 HUE.5 HUE.4 HUE.3 HUE.2 HUE.1 HUE.0
Default Value Y DEF_Y.5 DEF_Y.4 DEF_Y.3 DEF_Y.2 DEF_Y.1 DEF_Y.0 DEF_VAL_AUTO_EN DEF_VAL_EN
Default Value C DEF_C.7 DEF_C.6 DEF_C.5 DEF_C.4 DEF_C.3 DEF_C.2 DEF_C.1 DEF_C.0
ADI Control TRI_LLC DR_STR_C.1 DR_STR_C.0 DR_STR_S.1 DR_STR_S.0
Power Management PWRDN PDBP
Status 1 COL_KILL AD_RESULT.2 AD_RESULT.1 AD_RESULT.0 FOLLOW_PW FSC_LOCK LOST_LOCK IN_LOCK
Ident IDENT.7 IDENT.6 IDENT.5 IDENT.4 IDENT.3 IDENT.2 IDENT.1 IDENT.0
Status 2 FSC NSTD LL NSTD MV AGC DET MV PS DET MVCS T3 MVCS DET
Status 3 PAL SW LOCK INTERLACE STD FLD LEN FREE_RUN_ACT INST_HLOC K
Analog Clamp CCLEN
Control
Digital Clamp DCT.1 DCT.0
Control 1
Reserved
Shaping Filter CSFM.2 CSFM.1 CSFM.0 YSFM.4 YSFM.3 YSFM.2 YSFM.1 YSFM.0
Control
Shaping Filter WYSFMOVR WYSFM.4 WYSFM.3 WYSFM.2 WYSFM.1 WYSFM.0
Control 2
Comb Filter Control NSFSEL.1 NSFSEL.0 PSFSEL.1 PSFSEL.0
Reserved
Pixel Delay Control SWPC AUTO_PDC_EN CTA.2 CTA.1 CTA.0 LTA.1 LTA.0
Reserved
Misc Gain Control CKE PW_UPD
AGC Mode Control LAGC.2 LAGC.1 LAGC.0 CAGC.1 CAGC.0
Chroma Gain CAGT.1 CAGT.0 CMG.11 CMG.10 CMG.9 CMG.8
Control 1
Chroma Gain CMG.7 CMG.6 CMG.5 CMG.4 CMG.3 CMG.2 CMG.1 CMG.0
Control 2
Luma Gain LAGT.1 LGAT.0 LMG.11 LMG.10 LMG.9 LMG.8
Control 1
Luma Gain LMG.7 LMG.6 LMG.5 LMG.4 LMG.3 LMG.2 LMG.1 LMG.0
Control 2
VSync Field NEWAVMODE HVSTIM
Control 1
VSync Field VSBHO VSBHE
Control 2
VSync Field VSEHO VSEHE
Control 3
HSync Position HSB.10 HSB.9 HSB.8 HSE.10 HSE.9 HSE.8
Control 1
HSync Position HSB.7 HSB.6 HSB.5 HSB.4 HSB.3 HSB.2 HSB.1 HSB.0
Control 2
HSync Position HSE.7 HSE.6 HSE.5 HSE.4 HSE.3 HSE.2 HSE.1 HSE.0
Control 3
Polarity PHS PVS PF PCLK
NTSC Comb Control CTAPSN.1 CTAPSN.0 CCMN.2 CCMN.1 CCMN.0 YCMN.2 YCMN.1 YCMN.0
PAL Comb Control CTAPSP.1 CTAPSP.0 CCMP.2 CCMP.1 CCMP.0 YCMP.2 YCMP.1 YCMP.0
ADC Control PWRDN_AD C_0 PWRDN_AD C_1 PWRDN_ADC_2
Reserved
Manual Window CKILLTHR.2 CKILLTHR.1 CKILLTHR.0
Control
Reserved

Rev. B | Page 65 of 104

ADV7181
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Gemstar Ctrl 1 GDECEL.15 GDECEL.14 GDECEL.13 GDECEL.12 GDECEL.11 GDECEL.10 GDECEL.9 GDECEL.8
Gemstar Ctrl 2 GDECEL.7 GDECEL.6 GDECEL.5 GDECEL.4 GDECEL.3 GDECEL.2 GDECEL.1 GDECEL.0
Gemstar Ctrl 3 GDECOL.15 GDECOL.14 GDECOL.13 GDECOL.12 GDECOL.11 GDECOL.10 GDECOL.9 GDECOL.8
Gemstar Ctrl 4 GDECOL.7 GDECOL.6 GDECOL.5 GDECOL.4 GDECOL.3 GDECOL.2 GDECOL.1 GDECOL.0
Gemstar Ctrl 5 GDECAD
CTI DNR Ctrl 1 DNR_EN CTI_AB.1 CTI_AB.0 CTI_AB_EN CTI_EN
CTI DNR Ctrl 2 CTI_C_TH.7 CTI_C_TH.6 CTI_C_TH.5 CTI_C_TH.4 CTI_C_TH.3 CTI_C_TH.2 CTI_C_TH.1 CTI_C_TH.0
Reserved
CTI DNR Ctrl 4 DNR_TH.7 DNR_TH.6 DNR_TH.5 DNR_TH.4 DNR_TH.3 DNR_TH.2 DNR_TH.1 DNR_TH.0
Lock Count FSCLE SRLS COL.2 COL.1 COL.0 CIL.2 CIL.1 CIL.0
Reserved
Free Run Line LLC_PAD_SEL.2 LLC_PAD_SEL.1 LLC_PAD_SEL.0
Length 1
Reserved
VBI Info CGMSD EDTVD CCAPD WSSD
WSS 1 WSS1.7 WSS1.6 WSS1.5 WSS1.4 WSS1.3 WSS1.2 WSS1.1 WSS1.0
WSS 2 WSS2.7 WSS2.6 WSS2.5 WSS2.4 WSS2.3 WSS2.2 WSS2.1 WSS2.0
EDTV 1 EDTV1.7 EDTV1.6 EDTV1.5 EDTV1.4 EDTV1.3 EDTV1.2 EDTV1.1 EDTV1.0
EDTV 2 EDTV2.7 EDTV2.6 EDTV2.5 EDTV2.4 EDTV2.3 EDTV2.2 EDTV2.1 EDTV2.0
EDTV 3 EDTV3.7 EDTV3.6 EDTV3.5 EDTV3.4 EDTV3.3 EDTV3.2 EDTV3.1 EDTV3.0
CGMS 1 CGMS1.7 CGMS1.6 CGMS1.5 CGMS1.4 CGMS1.3 CGMS1.2 CGMS1.1 CGMS1.0
CGMS 2 CGMS2.7 CGMS2.6 CGMS2.5 CGMS2.4 CGMS2.3 CGMS2.2 CGMS2.1 CGMS2.0
CGMS 3 CGMS3.7 CGMS3.6 CGMS3.5 CGMS3.4 CGMS3.3 CGMS3.2 CGMS3.1 CGMS3.0
CCAP 1 CCAP1.7 CCAP1.6 CCAP1.5 CCAP1.4 CCAP1.3 CCAP1.2 CCAP1.1 CCAP1.0
CCAP 2 CCAP2.7 CCAP2.6 CCAP2.5 CCAP2.4 CCAP2.3 CCAP2.2 CCAP2.1 CCAP2.0
Letterbox 1 LB_LCT.7 LB_LCT.6 LB_LCT.5 LB_LCT.4 LB_LCT.3 LB_LCT.2 LB_LCT.1 LB_LCT.0
Letterbox 2 LB_LCM.7 LB_LCM.6 LB_LCM.5 LB_LCM.4 LB_LCM.3 LB_LCM.2 LB_LCM.1 LB_LCM.0
Letterbox 3 LB_LCB.7 LB_LCB.6 LB_LCB.5 LB_LCB.4 LB_LCB.3 LB_LCB.2 LB_LCB.1 LB_LCB.0
Reserved
CRC Enable CRC_ENABLE
Reserved
ADC Switch 1 ADC1_SW.3 ADC1_SW.2 ADC1_SW.1 ADC1_SW.0 ADC0_SW.3 ADC0_SW.2 ADC0_SW.1 ADC0_SW.0
ADC Switch 2 ADC_SW_M AN ADC2_SW.3 ADC2_SW.2 ADC2_SW.1 ADC2_SW.0
Reserved
Letterbox Control 1 LB_TH.4 LB_TH.3 LB_TH.2 LB_TH.1 LB_TH.0
Letterbox Control 2 LB_SL.3 LB_SL.2 LB_SL.1 LB_SL.0 LB_EL.3 LB_EL.2 LB_EL.1 LB_EL.0
Reserved
Reserved
Reserved
SD Offset Cb SD_OFF_CB.7 SD_OFF_CB.6 SD_OFF_CB.5 SD_OFF_CB.4 SD_OFF_CB.3 SD_OFF_CB.2 SD_OFF_CB.1 SD_OFF_CB.0
SD Offset Cr SD_OFF_CR.7 SD_OFF_CR.6 SD_OFF_CR.5 SD_OFF_CR.4 SD_OFF_CR.3 SD_OFF_CR.2 SD_OFF_CR .1 SD_OFF_CR.0
SD Saturation Cb SD_SAT_CB.7 SD_SAT_CB.6 SD_SAT_CB.5 SD_SAT_CB.4 SD_SAT_CB.3 SD_SAT_CB.2 SD_SAT_CB.1 SD_SAT_CB.0
SD Saturation Cr SD_SAT_CR.7 SD_SAT_CR.6 SD_SAT_CR.5 SD_SAT_CR.4 SD_SAT_CR.3 SD_SAT_CR.2 SD_SAT_CR.1 SD_SAT_CR.0
NTSC V Bit Begin NVBEGDEL O NVBEGDEL E NVBEGSIGN NVBEG.4 NVBEG.3 NVBEG.2 NVBEG.1 NVBEG.0
NTSC V Bit End NVENDDEL O NVENDDEL E NVENDSIGN NVEND.4 NVEND.3 NVEND.2 NVEND.1 NVEND.0
NTSC F Bit Toggle NFTOGDEL O NFTOGDEL E NFTOGSIGN NFTOG.4 NFTOG.3 NFTOG.2 NFTOG.1 NFTOG.0
PAL V Bit Begin PVBEGDEL O PVBEGDEL E PVBEGSIGN PVBEG.4 PVBEG.3 PVBEG.2 PVBEG.1 PVBEG.0
PAL V Bit End PVENDDEL O PVENDDEL E PVENDSIGN PVEND.4 PVEND.3 PVEND.2 PVEND.1 PVEND.0
PAL F Bit Toggle PFTOGDEL O PFTOGDEL E PFTOGSIGN PFTOG.4 PFTOG.3 PFTOG.2 PFTOG.1 PFTOG.0

Rev. B | Page 66 of 104

 ADV7181
I2C REGISTER MAP DETAILS
Grayed out sections mark the reset value of the register.
Table 171. Register 0x00
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting
0x00 Input INSEL [3:0]. The INSEL bits must be set to correctly
Control configure the ADV7181 to process the input video 0 0 0 0 Composite
format.
0 1 1 0 S-Video
1 0 0 1 YPrPb
VID_SEL [3:0]. The VID_SEL bits allow the user to 0 0 0 0 Autodetect PAL (BGHID),
select the input video standard. NTSC (without pedestal),
SECAM
0 0 0 1 Autodetect PAL (BGHID),
NTSC (M) (with pedestal),
SECAM
0 0 1 0 Autodetect PAL (N), NTSC
(M) (without pedestal),
SECAM
0 0 1 1 Autodetect PAL (N), NTSC
(M) (with pedestal), SECAM
0 1 0 0 NTSC(J)
0 1 0 1 NTSC(M)
0 1 1 0 PAL 60
0 1 1 1 NTSC 4.43
1 0 0 0 PAL BGHID
1 0 0 1 PAL N (BGHID without
pedestal)
1 0 1 0 PAL M (without pedestal)
1 0 1 1 PAL M
1 1 0 0 PAL combination N
1 1 0 1 PAL combination N (with
pedestal)
1 1 1 0 SECAM
1 1 1 1 SECAM (with pedestal)

Table 172. Register 0x01

Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Comments
0x01 Video Reserved.
Selection 0 0 0 Set to default
ENVSPROC
0 Disable VSync processor
1 Enable VSync processor
Reserved.
0 Set to default
BETACAM
0 Standard video input
1 Betacam input enable
ENHSPLL
0 Disable HSync processor SECAM standard. YPrPb signals.
1 Enable HSync processor
Reserved.
1 Set to default

Rev. B | Page 67 of 104

ADV7181
Table 173. Register 0x03
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Comments
0x03 Output SD_DUP_AV. Duplicates the AV codes
Control from the Luma into the chroma path. 0 AV codes to suit 8-bit
interleaved data
output
1 AV codes duplicated
(for 16-bit interfaces)
Reserved. 0 Set as default

OF_SEL [3:0]. Allows the user to choose

from a set of output formats. 0 0 0 0 Reserved
0 0 0 1 Reserved
0 0 1 0 16-bit @ LLC1 4:2:2
0 0 1 1 8-bit @ LLC1 4:2:2
ITU-R BT.656
0 1 0 0 Not used
0 1 0 1 Not used
0 1 1 0 Not used
0 1 1 1 Not used
1 0 0 0 Not used
1 0 0 1 Not used
1 0 1 0 Not used
1 0 1 1 Not used
1 1 0 0 Not used
1 1 0 1 Not used
1 1 1 0 Not used
1 1 1 1 Not used
TOD. Three-State Output Drivers. This bit See also
allows the user to three-state the output TIM_OE
drivers: P[19:0], HS, VS, FIELD, and SFL. (Table 174);
TRI_LLC
(Table 176)
0 Output pins enabled
1 Drivers three-stated
VBI_EN. Allows VBI data (Lines 1 to 21)
to be passed through with only a 0 All lines filtered and
minimum amount of filtering performed. scaled
1 Only active video
region filtered

Rev. B | Page 68 of 104

 ADV7181
Table 174. Register 0x04
Bit Register
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Setting Comments
0x04 Extended RANGE. Allows the user to select
Output the range of output values. Can 0 16 < Y < 235, ITU-R BT.656
Control be BT656 compliant, or can fill the 16 < C < 240
whole accessible number range.
1 1 < Y < 254, Extended range
1 < C < 254
EN_SFL_PIN. SFL output enables
0 SFL output is encoder and decoder to
disabled be connected directly
1 SFL information
output on the
SFL pin
BL_C_VBI. Blank Chroma during During VBI
VBI. If set, enables data in the VBI 0 Decode and
region to be passed through the output color
decoder undistorted.
1 Blank Cr and Cb
TIM_OE. Timing signals output Controlled by TOD
enable. 0 HS, VS, F three-
stated
1 HS, VS, F forced
active
DR_STR[1:0]. Drive strength of Recommended
output drivers can be increased or 0 0 Low drive, 1×
decreased for EMC or crosstalk
0 1 Medium-low, 2×
reasons.
1 0 Medium-high,
3×
1 1 High drive, 4×
Reserved.
1 Set to default
BT656-4. Allows the user to select
an output mode compatible with 0 BT656-3-
ITU- R BT656-3/4. compatible
1 BT656-4-
compatible

Rev. B | Page 69 of 104

ADV7181
Table 175. Registers 0x07 and 0x08
Bit Register
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Setting Comments
0x07 Autodetect AD_PAL_EN. PAL B/G/I/H autodetect
Enable enable. 0 Disable
1 Enable
AD_NTSC_EN. NTSC autodetect enable.
0 Disable
1 Enable
AD_PALM_EN. PAL M autodetect enable
0 Disable
1 Enable
AD_PALN_EN. PAL N autodetect enable.
0 Disable
1 Enable
AD_P60_EN. PAL 60 autodetect enable.
0 Disable
1 Enable
AD_N443_EN. NTSC443 autodetect enable.
0 Disable
1 Enable
AD_SECAM_EN. SECAM autodetect enable.
0 Disable
1 Enable
AD_SEC525_EN. SECAM 525 autodetect
enable. 0 Disable
1 Enable
0x08 Contrast CON[7:0]. Contrast adjust. This is the user 0x00 gain = 0
control for contrast adjustment. 1 0 0 0 0 0 0 0 Luma gain = 1 0x80 gain = 1
0xFF gain = 2

Rev. B | Page 70 of 104

 ADV7181
Table 176. Registers 0x09 to 0x0E
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Comments
0x09 Reserved. Reserved.
(Saturation) 1 0 0 0 0 0 0 0
0x0A Brightness BRI[7:0]. This register controls 0x00 = 0IRE
the brightness of the video 0 0 0 0 0 0 0 0 0x7F = 100IRE
signal. 0x80 = –100IRE
0x0B Hue HUE[7:0]. This register Hue range =
contains the value for the color 0 0 0 0 0 0 0 0 –90° to +90°
hue adjustment.
0x0C Default Value Y DEF_VAL_EN. Default value
enable. 0 Free Run mode
dependent on
DEF_VAL_AUTO_EN
1 Force Free Run mode
on and output blue
screen
DEF_VAL_AUTO_EN. Default
value. 0 Disable Free Run When lock is lost,
mode Free Run mode
1 Enable Automatic Free can be enabled
Run mode (blue to output stable
screen) timing, clock,
and a set color.
DEF_Y[5:0]. Default value Y. Default Y value
This register holds the Y 0 0 1 1 0 1 Y[7:0] = {DEF_Y[5:0], output in free-
default value. 0, 0, 0, 0} run mode.
0x0D Default Value C DEF_C[7:0]. Default value C. Cr[7:0] = {DEF_C[7:4], Default Cb/Cr
Cr and Cb default values are 0, 0, 0, 0, 0, 0} value output in
defined in this register. Cb[7:0] = {DEF_C[3:0], Free Run mode.
0, 0, 0, 0, 0, 0} Default values
0 1 1 1 1 1 0 0 give blue screen
output.
0x0E ADI Control DR_STR_S[1:0]. Select the
drive strength of the sync 0 0 Low drive strength
signals. HS, VS, and F can be (1×)
increased or decreased for
0 1 Medium-low (2×)
EMC or crosstalk reasons.
1 0 Medium-high (3×)
1 1 High drive strength
(4×)
DR_STR_C[1:0]. Select the
strength of the clock signal 0 0 Low drive strength
output driver. Can be (1×)
increased or decreased for
0 1 Medium-low (2×)
EMC or crosstalk reasons.
1 0 Medium-high (3×)
1 1 High drive strength
(4×)
Reserved.
0 0
TRI_LLC. Enables the LLC pin Set as default See TOD
to be three-stated. (Table 173);
TIM_OE
0 LLC pin active
(Table 174)
1 LLC pin drivers three-
stated
Reserved.
0 Set as default

Rev. B | Page 71 of 104

ADV7181
Table 177. Registers 0x0F to 0x11
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Comments
0x0F Power Reserved.
Management 0 0 Set to default
PDBP. Power-down bit
priority selects between 0 Chip power-down
PWRDN bit or PIN. controlled by pin
1 Bit has priority (pin
disregarded)
Reserved.
0 0 Set to default
PWRDN. Power-down
places the decoder in a full 0 System functional See PDBP, 0x0F,
power-down mode. Bit 2
1 Powered down
Reserved.
0 Set to default
RES. ChiprReset loads all I2C 0 Normal operation Executing reset
bits with default values. takes approx. 2 ms.
1 Start reset sequence This bit is self
clearing.
0x10 Status. Read- STATUS_1[7:0]. Provides
only information about the
internal status of the
decoder.
STATUS_1[3:0]. x In lock (right now) = 1
x Lost lock (since last
read)
x Fsc lock (right now) = 1
x Peak white AGC mode
active = 1
STATUS_1[6:4]
AD_RESULT[2:0]. 0 0 0 NTSM-MJ Detected standard
Autodetection result reports
0 0 1 NTSC-443
the findings.
0 1 0 PAL-M
0 1 1 PAL-60
1 0 0 PAL-BGHID
1 0 1 SECAM
1 1 0 PAL combination N
1 1 1 SECAM 525
STATUS_1[7]
COL_KILL. Color Kill. x Color kill is active = 1
0x11 Info. Read-only IDENT[7:0] Provides
identification on the x x x x x x x x
revision of the part.

Rev. B | Page 72 of 104

 ADV7181
Table 178. Registers 0x12 and 0x13
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Comments
0x12 Status Register 2. STATUS_2[7:0]. Provides
Read-only. information about the internal status
of the decoder.
STATUS_2[5:0]. x MV color striping 1 = Detected
detected
x MV color striping 0 = Type 2,
type 1 = Type 3
x MV pseudosync 1 = Detected
detected
x MV AGC pulses 1 = Detected
detected
x Nonstandard line 1 = Detected
length
x Fsc frequency 1 = Detected
nonstandard
Reserved.
x x
0x13 Status Register 3. STATUS_3[7:0]. Provides
Read-only. information about the internal status x 1 = Horizontal Unfiltered
of the decoder. lock achieved
x x x 1 = Reserved bits No function
x 1 = Free Run Blue screen
mode active output
x 1 = Field length
standard
x 1 = Swinging Reliable
burst detected sequence

Table 179. Register 0x14

Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting
0x14 Analog Clamp Reserved.
Control 0 0 1 0 Reserved. Set to default.
CCLEN. Current clamp enable allows the user to
switch off the current sources in the analog front. 0 I sources switched off.
1 I sources enabled.
Reserved.
0 Reserved. Set to default.
Reserved.
0 0 Reserved. Set to default.

Table 180. Register 0x15

Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting
0x15 Digital Clamp Reserved.
Control 1 x x x x x Set to default
DCT[1:0]. Digital clamp timing determines the
time constant of the digital fine clamp circuitry. 0 0 Slow (TC = 1 s)
0 1 Medium (TC = 0.5 s)
1 0 Fast (TC = 0.1 s)
1 1 TC dependent on video
Reserved.
0 Set to default

Rev. B | Page 73 of 104

ADV7181
Table 181. Register 0x17
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Comments
0x17 Shaping YSFM[4:0]. Selects Y Decoder selects
Filter Shaping Filter mode 0 0 0 0 0 Auto wide notch for poor optimum Y shaping
Control when in CVBS only quality sources or wide- filter depending on
mode. Allows the user to band filter with Comb for CVBS quality.
select a wide range of good quality input.
low-pass and notch
0 0 0 0 1 Auto narrow notch for poor
filters.
quality sources or wideband
If either auto mode is filter with comb for good
selected, the decoder quality input.
selects the optimum Y
0 0 0 1 0 SVHS 1 If one of these modes is
filter depending on the
0 0 0 1 1 SVHS 2 selected, the decoder
CVBS video source
quality (good vs. bad). does not change filter
0 0 1 0 0 SVHS 3
modes depending on
0 0 1 0 1 SVHS 4 video quality. A fixed
0 0 1 1 0 SVHS 5 filter response (the one
0 0 1 1 1 SVHS 6 selected) is used for
good and bad quality
0 1 0 0 0 SVHS 7 video.
0 1 0 0 1 SVHS 8
0 1 0 1 0 SVHS 9
0 1 0 1 1 SVHS 10
0 1 1 0 0 SVHS 11
0 1 1 0 1 SVHS 12
0 1 1 1 0 SVHS 13
0 1 1 1 1 SVHS 14
1 0 0 0 0 SVHS 15
1 0 0 0 1 SVHS 16
1 0 0 1 0 SVHS 17
1 0 0 1 1 SVHS 18 (CCIR601)
1 0 1 0 0 PAL NN1
1 0 1 0 1 PAL NN2
1 0 1 1 0 PAL NN3
1 0 1 1 1 PAL WN 1
1 1 0 0 0 PAL WN 2
1 1 0 0 1 NTSC NN1
1 1 0 1 0 NTSC NN2
1 1 0 1 1 NTSC NN3
1 1 1 0 0 NTSC WN1
1 1 1 0 1 NTSC WN2
1 1 1 1 0 NTSC WN3
1 1 1 1 1 Reserved
CSFM[2:0]. C Shaping Automatically selects a
Filter mode allows the 0 0 0 Auto selection 1.5 MHz C filter based on video
selection from a range of standard and quality.
0 0 1 Auto selection 2.17 MHz
low-pass chrominance
filters. 0 1 0 SH1 Selects a C filter for all
If either auto mode is 0 1 1 SH2 video standards and for
good and bad video.
selected, the decoder 1 0 0 SH3
selects the optimum C 1 0 1 SH4
filter depending on the
CVBS video source 1 1 0 SH5
quality (good vs. bad). 1 1 1 Wideband mode
Non-auto settings force
a C filter for all standards
and quality of CVBS
video.

Rev. B | Page 74 of 104

 ADV7181
Table 182. Register 0x18 to 0x19
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments
0x18 Shaping WYSFM[4:0] Wideband Y Shaping Filter mode allows
Filter the user to select which Y shaping filter is used for the Y 0 0 0 0 0 Reserved. Do not use.
Control 2 component of Y/C, YPbPr, B/W input signals; it is also
0 0 0 0 1 Reserved. Do not use.
used when a good quality input CVBS signal is
detected. For all other inputs, the Y shaping filter 0 0 0 1 0 SVHS 1
chosen is controlled by YSFM[4:0]. 0 0 0 1 1 SVHS 2
0 0 1 0 0 SVHS 3
0 0 1 0 1 SVHS 4
0 0 1 1 0 SVHS 5
0 0 1 1 1 SVHS 6
0 1 0 0 0 SVHS 7
0 1 0 0 1 SVHS 8
0 1 0 1 0 SVHS 9
0 1 0 1 1 SVHS 10
0 1 1 0 0 SVHS 11
0 1 1 0 1 SVHS 12
0 1 1 1 0 SVHS 13
0 1 1 1 1 SVHS 14
1 0 0 0 0 SVHS 15
1 0 0 0 1 SVHS 16
1 0 0 1 0 SVHS 17
1 0 0 1 1 SVHS 18 (CCIR 601)
1 0 1 0 0 Reserved. Do not use.
Reserved. Do not use.
1 1 1 1 1 Reserved. Do not use.
Reserved.
0 0 Set to default
WYSFMOVR. Enables the use of the automatic WYSFN
filter. 0 Auto selection of best
filter
1 Manual select filter
using WYSFM[4:0]
0x19 Comb PSFSEL[1:0]. Controls the signal bandwidth that is fed
Filter to the comb filters (PAL). 0 0 Narrow
Control
0 1 Medium
1 0 Wide
1 1 Widest
NSFSEL[1:0]. Controls the signal bandwidth that is fed
to the comb filters (NTSC). 0 0 Narrow
0 1 Medium
1 0 Medium
1 1 Wide
Reserved.
1 1 1 1 Set as default

Rev. B | Page 75 of 104

ADV7181
Table 183. Registers 0x27
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x27 Pixel LTA[1:0]. Luma timing adjust CVBS mode
Delay allows the user to specify a 0 0 No Delay LTA[1:0] = 00b;
Control timing difference between S-Video mode
0 1 Luma 1 clk (37 ns) delayed
chroma and luma samples. LTA[1:0]= 01b,
1 0 Luma 2 clk (72 ns) early YPrPb mode
0 1 Luma 1 clk (37 ns) early LTA[1:0] = 01b
Reserved.
0 Set to 0
CTA[2:0]. Chroma timing CVBS mode
adjust allows a specified 0 0 0 Not a valid setting CTA[2:0] = 011b,
timing difference between S-Video mode
0 0 1 Chroma + 2 pixels (early)
the luma and chroma CTA[2:0] = 101b,
samples. 0 1 0 Chroma + 1 pixel (early) YPrPb mode
0 1 1 No Delay CTA[2:0] = 110b
1 0 0 Chroma – 1 pixel (late)
1 0 1 Chroma – 2 pixels (late)
1 1 0 Chroma – 3 pixels (late)
1 1 1 Not a valid setting
AUTO_PDC_EN.
Automatically programs the 0 Use values in LTA[1:0] and
LTA/CTA values so that luma CTA[2:0] for delaying
and chroma are aligned at luma/chroma
output for all modes of
1 LTA and CTA values
operation.
determined automatically
SWPC. Allows the Cr and Cb
samples to be swapped. 0 No swapping
1 Swap the Cr and Cb

Rev. B | Page 76 of 104

 ADV7181
Table 184. Registers 0x2B and 0x2C
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x2B Misc Gain PW_UPD. Peak white update
Control determines the rate of gain. 0 Update once per Peak white must be
video line enabled. See LAGC[2:0].
1 Update once per
field
Reserved.
0
1 0 0 0 1 Set to default
CKE. Color kill enable allows For SECAM color kill,
the color kill function to be threshold is set at 8%.
switched on and off. 0 Color kill disabled
1 Color kill enabled See CKILLTHR[2:0]
(Table 192).
Reserved.
1 1 1 Set to default
0x2C AGC Mode CAGC[1:0]. Chroma automatic
Control gain control selects the basic 0 0 Manual fixed gain Use CMG[11:0].
mode of operation for the AGC
0 1 Use luma gain for
in the chroma path.
chroma
1 0 Automatic gain Based on color burst.
1 1 Freeze chroma gain

Reserved.
1 1 Set to 1
LAGC[2:0]. Luma automatic
gain control selects the mode 0 0 0 Manual fixed gain Use LMG[11:0].
of operation for the gain
0 0 1 AGC no override Blank level to sync tip.
control in the luma path.
through white
peak. Man IRE
control.
0 1 0 AGC auto-override Blank level to sync tip.
through white
peak. Man IRE
control.
0 1 1 AGC no override Blank level to sync tip.
through white
peak. Auto IRE
control.
1 0 0 AGC auto-override Blank level to sync tip.
through white
peak. Auto IRE
control.
1 0 1 AGC active video
with white peak
1 1 0 AGC active video
with average video
1 1 1 Freeze gain
Reserved.
1 Set to 1

Rev. B | Page 77 of 104

ADV7181
Table 185. Registers 0x2D to 0x30
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x2D Chroma CMG[11:8]. Chroma manual CAGC[1:0] settings
Gain gain can be used to program a decide in which
Control 1 desired manual chroma gain. mode CMG[11:0]
Reading back from this register operates .
in AGC mode gives the current 0 1 0 0
gain.
Reserved.
1 1 Set to 1
CAGT[1:0]. Chroma automatic Has an effect only if
gain timing allows adjustment of CAGC[1:0] is set to
the chroma AGC tracking speed. auto gain (10).
0 0 Slow (TC = 2 s)
0 1 Medium (TC = 1 s)
1 0 Fast (TC = 0.2 s)
1 1 Adaptive
0x2E Chroma CMG[7:0]. Chroma manual gain CMG[11:0] = 750d; Min value is 0d
Gain lower 8 bits. See CMG[11:8] for gain is 1 in NTSC (G = –60 dB)
Control 2 description. CMG[11:0] = 741d; Max value is 3750
gain is 1 in PAL. (gain = 5).
0 0 0 0 0 0 0 0
0x2F Luma Gain LMG[11:8]. Luma manual gain LAGC[1:0] settings
Control 1 can be used program a desired decide in which
manual chroma gain, or to read mode LMG[11:0]
back the actual gain value used. operates.
x x x x
Reserved.
1 1 Set to 1
LAGT[1:0]. Luma automatic gain Only has an effect if
timing allows adjustment of the AGC[1:0] is set to
luma AGC tracking speed. auto gain (001, 010,
011,or 100)
0 0 Slow (TC = 2 s)
0 1 Medium (TC = 1 s)
1 0 Fast (TC = 0.2 s)
1 1 Adaptive
0x30 Luma Gain LMG[7:0]. Luma manual gain LMG[11:0] = 1234d; Min value
Control 2 can be used to program a gain is 1 in NTSC NTSC 1024 (G = 0.85)
desired manual chroma gain or LMG[11:0] = 1266d; PAL (G = 0.81)
read back the actual used gain gain is 1 in PAL. Max value
value. x x x x x x x x NTSC 2468 (G = 2),
PAL = 2532 (G = 2)

Rev. B | Page 78 of 104

 ADV7181
Table 186. Register 0x31
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x31 VS and Reserved.
FIELD 0 1 0 Set to default.
Control 1
HVSTIM. Selects where
within a line of video the VS 0 Start of line relative to HSE. HSE = Hsync end
signal is asserted.
1 Start of line relative to HSB. HSB = Hsync begin
NEWAVMODE. Sets the
EAV/SAV mode. 0 EAV/SAV codes generated
to suit ADI encoders.
1 Manual VS/Field position
controlled by Registers
0x32, 0x33, and 0xE5–0xEA.
Reserved.
0 0 0 Set to default.

Table 187. Registers 0x32 and 0x33

Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x32 VSync Field Reserved.
Control 2 0 0 0 0 0 1 Set to default.
VSBHE NEWAVMODE bit
0 VS goes high in the middle of the line must be set high.
(even field).
1 VS changes state at the start of the
line (even field).
VSBHO
0 VS goes high in the middle of the line
(odd field).
1 VS changes state at the start of the
line (odd field).
0x33 VSync Field Reserved.
Control 3 0 0 0 1 0 0 Set to default.
VSEHE NEWAVMODE bit
0 VS goes low in the middle of the line must be set high.
(even field).
1 VS changes state at the start of the
line (even field).
VSEHO
0 VS goes low in the middle of the line
(odd field).
1 VS changes state at the start of the
line odd field.

Rev. B | Page 79 of 104

ADV7181
Table 188. Registers 0x34 to 0x36
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x34 HS Position
Control 1 HSE[10:8]. HS end allows the HS output ends Using HSB and HSE,
positioning of the HS output 0 0 0 HSE[10:0] pixels the user can program
within the video line. after the falling the position and
edge of HSync. length of the output
Reserved. HSync.
0 Set to 0.

HSB[10:8]. HS begin allows HS output starts

the positioning of the HS 0 0 0 HSB[10:0] pixels
output within the video line. after the falling
Reserved. edge of HSync.
0 Set to 0.
0x35 HS Position HSB[7:0] See above, using
Control 2 HSB[9:0] and HSE[9:0] the user 0 0 0 0 0 0 1 0
can program the position and
length of HS output signal.
0x36 HS Position HSE[7:0] See above.
Control 3 0 0 0 0 0 0 0 0

Table 189. Register 0x37

Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments
0x37 Polarity PCLK. Sets the polarity of LLC1.
0 Invert polarity
1 Normal polarity as per Timing Diagrams
Reserved.
0 0 Set to 0
PF. Sets the FIELD polarity.
0 Active high
1 Active low
Reserved.
0 Set to 0
PVS. Sets the VS polarity.
0 Active high
1 Active low
Reserved.
0 Set to 0
PHS. Sets HS polarity.
0 Active high
1 Active low

Rev. B | Page 80 of 104

 ADV7181
Table 190. Register 0x38
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x38 NTSC Comb YCMN[2:0]. Luma
Control Comb Mode, NTSC. 0 0 0 Adaptive 3-line, 3-tap
luma
1 0 0 Use low-pass notch
1 0 1 Fixed luma comb Top lines of memory
(2-line)
1 1 0 Fixed luma comb All lines of memory
(3-line)
1 1 1 Fixed luma comb Bottom lines of memory
(2-line)
CCMN[2:0]. Chroma
Comb Mode, NTSC. 0 0 0 3-line adaptive for
CTAPSN = 01
4-line adaptive for
CTAPSN = 10
5-line adaptive for
CTAPSN = 11
1 0 0 Disable chroma comb
1 0 1 Fixed 2-line for Top lines of memory
CTAPSN = 01
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
1 1 0 Fixed 3-line for All lines of memory
CTAPSN = 01
Fixed 4-line for
CTAPSN = 10
Fixed 5-line for
CTAPSN = 11
1 1 1 Fixed 2-line for Bottom lines of memory
CTAPSN = 01
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
CTAPSN[1:0].
Chroma 0 0 Not used
Comb Taps, NTSC.
0 1 Adapts 3 lines – 2 lines
1 0 Adapts 5 lines – 3 lines
1 1 Adapts 5 lines – 4 lines

Rev. B | Page 81 of 104

ADV7181
Table 191. Registers 0x39 and 0x3A
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x39 PAL Comb YCMP[2:0]. Luma Comb 0 0 0 Adaptive 5-line, 3-tap luma comb
Control mode, PAL. 1 0 0 Use low-pass notch
1 1 0 Fixed luma comb Top lines of
memory
1 1 0 Fixed luma comb (5-line) All lines of
memory
1 1 1 Fixed luma comb (3-line) Bottom lines
of memory
CCMP[2:0]. Chroma 0 0 0 3-line adaptive for CTAPSN = 01
Comb mode, PAL. 4-line adaptive for CTAPSN = 10
5-line adaptive for CTAPSN = 11
1 0 0 Disable chroma comb
1 0 1 Fixed 2-line for CTAPSN = 01 Top lines of
Fixed 3-line for CTAPSN = 10 memory
Fixed 4-line for CTAPSN = 11
1 1 0 Fixed 3-line for CTAPSN = 01 All lines of
Fixed 4-line for CTAPSN = 10 memory
Fixed 5-line for CTAPSN = 11
CTAPSP[1:0]. Chroma 0 0 Not used
comb taps, PAL. 0 1 Adapts 5-lines – 2 lines (2 taps)
1 0 Adapts 5 lines – 3 lines (3 taps)
1 1 Adapts 5 lines – 4 lines (4 taps)
0x3A ADC Reserved. 0 Set as default
Control PWRDN_ADC_2. Enables 0 ADC2 normal operation
power down of ADC2. 1 Power down ADC2
PWRDN_ADC_1. Enables 0 ADC1 normal operation
power down of ADC1. 1 Power down ADC1
PWRDN_ADC_0. Enables 0 ADC0 normal operation
power down of ADC0. 1 Power down ADC0
Reserved. 0 0 0 1 Set as default

Rev. B | Page 82 of 104

 ADV7181
Table 192. Register 0x3D
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x3D Manual Reserved.
Window 0 0 1 1 Set to default
CKILLTHR[2:0]. CKE = 1 enables the color kill function and
0 0 0 Kill at 0.5% must be enabled for CKILLTHR[2:0] to take
effect.
0 0 1 Kill at 1.5%
0 1 0 Kill at 2.5%
0 1 1 Kill at 4%
1 0 0 Kill at 8.5%
1 0 1 Kill at 16%
1 1 0 Kill at 32%
1 1 1 Reserved
Reserved.
0 Set to default

Table 193. Registers 0x41 to 0x4C

Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x41 Resample Reserved.
Control 0 1 0 0 0 0 Set to default
SFL_INV. Controls the
behavior of the PAL switch 0 SFL-compatible with
bit. ADV7190/ADV7191/ADV7194
encoders
1 SFL-compatible with
ADV717x/ADV7173x encoders
Reserved.
0 Set to default
0x48 Gemstar GDECEL[15:0]. 16 LSB = Line 10
Control 1 individual enable bits that MSB = Line 25
select the lines of video Default = Do not
(even field Lines 10–25) check for
that the decoder checks Gemstar-
for Gemstar-compatible compatible data
data. on any lines [10–
GDECEL[15:8]. See above. 0 0 0 0 0 0 0 0 25] in even fields
0x49 Gemstar GDECEL[7:0]. See above.
Control 2 0 0 0 0 0 0 0 0
0x4A Gemstar GDECOL[15:0]. 16 LSB = Line 10
Control 3 individual enable bits that MSB = Line 25
select the lines of video Default = Do not
(odd field lines 10–25) that check for
the decoder checks for Gemstar-
Gemstar-compatible data. compatible data
GDECOL[15:8]. See above. 0 0 0 0 0 0 0 0 on any lines [10–
25] in odd fields
0x4B Gemstar GDECOL[7:0]. See above.
Control 4 0 0 0 0 0 0 0 0
0x4C Gemstar GDECAD. Controls the
Control 5 manner in which decoded 0 Split data into half byte To avoid 00/FF
Gemstar data is inserted code
into the horizontal
1 Output in straight 8-bit format
blanking period.
Reserved.
x x x x x x x Undefined

Rev. B | Page 83 of 104

ADV7181
Table 194. Registers 0x4D to 0x50
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments
0x4D CTI DNR CTI_EN. CTI enable.
Control 1 0 Disable CTI
1 Enable CTI
CTI_AB_EN. Enables the mixing of the
transient improved chroma with the 0 Disable CTI alpha blender
original signal.
1 Enable CTI alpha blender
CTI_AB[1:0]. Controls the behavior of the
alpha-blend circuitry. 0 0 Sharpest mixing
0 1 Sharp mixing
1 0 Smooth
1 1 Smoothest
Reserved.
0 Set to default
DNR_EN. Enable or bypass the DNR block.
0 Bypass the DNR block
1 Enable the DNR block
Reserved.
1 Set to default
Reserved.
1 Set to default
0x4E CTI DNR CTI_CTH[7:0]. Specifies how big the
Control 2 amplitude step must be to be steepened 0 0 0 0 1 0 0 0
by the CTI block.
0x50 CTI DNR DNR_TH[7:0]. Specifies the maximum Set to 0x04 for A/V input; set to
Control 4 edge that is interpreted as noise and is 0x0A for tuner input.
therefore blanked. 0 0 0 0 1 0 0 0

Rev. B | Page 84 of 104

 ADV7181
Table 195. Register 0x51
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x51 Lock CIL[2:0]. Count-into-lock
Count determines the number of lines 0 0 0 1 line of video
the system must remain in lock
0 0 1 2 lines of video
before showing a locked status.
0 1 0 5 lines of video
0 1 1 10 lines of video
1 0 0 100 lines of video
1 0 1 500 lines of video
1 1 0 1000 lines of video
1 1 1 100000 lines of video
COL[2:0]. Count-out-of-lock
determines the number of lines 0 0 0 1 line of video
the system must remain out-of-
0 0 1 2 lines of video
lock before showing a lost-
locked status. 0 1 0 5 lines of video
0 1 1 10 lines of video
1 0 0 100 lines of video
1 0 1 500 lines of video
1 1 0 1000 lines of video
1 1 1 100000 lines of video
SRLS. Select raw lock signal.
Selects the determination of 0 Over field with vertical
the lock status. info
1 Line-to-line evaluation
FSCLE. Fsc lock enable. FSCLE must be set to
0 in YPrPb mode if a
reliable LOST_LOCK
bit is set to 0.
0 Lock status set only by
horizontal lock
1 Lock status set by
horizontal lock and
subcarrier lock

Rev. B | Page 85 of 104

ADV7181
Table 196. Registers 0x8F and 0x90
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x8F Free Run Reserved.
Line 0 0 0 0 Set to default
Length 1
LLC_PAD_SEL [2:0]. Enables
manual selection of clock for 0 0 0 LLC1 (nominally
LLC1 pin. 27 MHz) selected out
on LLC1 pin
1 0 1 LLC2 (nominally For 16-bit 4:2:2 out,
13.5 MHz) selected out OF_SEL[3:0] = 0010
on LLC1 pin
Reserved.
0 Set to default
0x90 VBI Info WSSD. Screen signaling Ready-only status
Read Mode detected. 0 No WSS detected bits
Details
1 WSS detected
CCAPD. Closed caption data.
0 No CCAP signals
detected
1 CCAP sequence
detected
EDTVD. EDTV sequence.
0 No EDTV sequence
detected
1 EDTV sequence
detected
CGMSD. CGMS sequence.
0 No CGMS transition
detected
1 CGMS sequence
decoded
Reserved.
x x x x

Rev. B | Page 86 of 104

 ADV7181
Table 197. Registers 0x91 to 0x9D
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0x91 WSS1[7:0]. Wide WSS1[7:0]
screen signaling x x x x x x x x
data. Read-only.
0x92 WSS1[7:0]. Wide WSS2[7:0] WSS2[7:6] are
screen signaling undetermined.
data. Read-only. x x x x x x x x
0x93 EDTV1[7:0]. EDTV1[7:0]
EDTV data. Read- x x x x x x x x
only.
0x94 EDTV2[7:0]. EDTV2[7:0]
EDTV data. Read- x x x x x x x x
only.
0x95 EDTV3[7:0]. EDTV3[7:0] EDTV3[7:6] are EDTV3[5] is reserved for
EDTV data. Read- undetermined. future use.
only. x x x x x x x x
0x96 CGMS1[7:0]. CGMS1[7:0]
CGMS data. x x x x x x x x
Read-only.
0x97 CGMS2[7:0]. CGMS2[7:0]
CGMS data. x x x x x x x x
Read-only.
0x98 CGMS3[7:0]. CGMS3[7:0] CGMS3[7:4] are
CGMS data. undetermined.
Read-only. x x x x x x x x
0x99 CCAP1[7:0]. CCAP1[7:0] CCAP1[7] contains parity
Closed caption bit for Byte 0.
data. Read-only. x x x x x x x x
0x9A CCAP2[7:0]. CCAP2[7:0] CCAP2[7] contains parity
Closed caption bit for Byte 0.
data. Read-only. x x x x x x x x
0x9B Letterbox 1. LB_LCT[7:0] Reports the number of This feature examines the
Read-only. x x x x x x x x black lines detected at active video at the start and
top of active video. at the end of each field. It
0x9C Letterbox 2. LB_LCM[7:0] Reports the number of enables format detection
Read-only. black lines detected in even if the video is not
x x x x x x x x
the bottom half of active accompanied by a CGMS or
video if subtitles are WSS sequence.
detected.
0x9D Letterbox 3. LB_LCB[7:0] Reports the number of
Read-only. x x x x x x x x black lines detected at
the bottom of active
video.

Table 198. Register 0xB2

Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments
0xB2 CRC Enable Reserved.
Write 0 0 Set as default.
CRC_ENABLE. Enables CRC checksum
decoded from CGMS packet to validate 0 Turn off CRC check.
CGMSD.
1 CGMSD goes high with
valid checksum.
Reserved.
0 0 0 1 1 Set as default.

Rev. B | Page 87 of 104

ADV7181
Table 199. Register 0xC3
Bit
Comment
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 (default) Note
0xC3 ADC ADC0_SW[3:0]. Manual muxing SETADC_sw_man_en = 1
SWITCH 1 control for ADC0. 0 0 0 0 NC
0 0 0 1 AIN2
0 0 1 0 NC
0 0 1 1 NC
0 1 0 0 AIN4
0 1 0 1 AIN6
0 1 1 0 NC
0 1 1 1 NC
1 0 0 0 NC
1 0 0 1 AIN1
1 0 1 0 NC
1 0 1 1 NC
1 1 0 0 AIN3
1 1 0 1 AIN5
1 1 1 0 NC
1 1 1 1 NC
ADC1_SW[3:0]. Manual muxing
control for ADC1. 0 0 0 0 NC
0 0 0 1 NC
0 0 1 0 NC
0 0 1 1 NC
0 1 0 0 AIN4
0 1 0 1 AIN6
0 1 1 0 NC
0 1 1 1 NC
1 0 0 0 NC
1 0 0 1 NC
1 0 1 0 NC
1 0 1 1 NC
1 1 0 0 AIN3
1 1 0 1 AIN5
1 1 1 0 NC
1 1 1 1 NC

NC = no connection.

Rev. B | Page 88 of 104

 ADV7181
Table 200. Register 0xC4
Bit
Comments
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 (default) Notes
0xC4 ADC ADC2_SW[3:0]. Manual muxing SETADC_sw_man_en = 1
SWITCH 2 control for ADC2. 0 0 0 0 NC
0 0 0 1 NC
0 0 1 0 NC
0 0 1 1 NC
0 1 0 0 NC
0 1 0 1 AIN6
0 1 1 0 NC
0 1 1 1 NC
1 0 0 0 NC
1 0 0 1 NC
1 0 1 0 NC
1 0 1 1 NC
1 1 0 0 NC
1 1 0 1 AIN5
1 1 1 0 NC
1 1 1 1 NC
Reserved.
x x x
ADC_SW_MAN_EN. Enable manual
setting of the input signal muxing. 0 Disable
1 Enable

NC = no connection.

Rev. B | Page 89 of 104

ADV7181
Table 201. Registers 0xDC to 0xE4
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments
0xDC Letterbox Control 1 LB_TH [4:0]. Sets the threshold
value that detects a black. 0 1 1 0 0 Default threshold for detection of
black lines.
Reserved.
1 0 1 Set as default.
0xDD Letterbox Control 2 LB_EL[3:0]. Programs the end line
of the activity window for LB 1 1 0 0 LB detection ends with the last line
detection (end of field). of active video on a field. 1100:
262/525.
LB_SL[3:0]. Programs the start line
of the activity window for LB 0 1 0 0 Letterbox detection aligned with
detection (start of field). the start of active video.
0100: 23/286 NTSC.
0xDE Reserved.
0 0 0 0 0 0 0 0
0xDF Reserved.
0 0 0 0 0 0 0 0
0xE0 Reserved.
0 0 0 1 0 1 0 0
0xE1 SD Offset Cb SD_OFF_CB [7:0]. Adjusts hue by
selecting offset for the Cb channel. 1 0 0 0 0 0 0 0
0xE2 SD Offset Cr SD_OFF_CR [7:0]. Adjusts hue by
selecting offset for the Cr channel. 1 0 0 0 0 0 0 0
0xE3 SD Saturation Cb SD_SAT_CB [7:0]. Adjusts
saturation of the picture by 1 0 0 0 0 0 0 0 Chroma gain = 0 dB
affecting gain on the Cb channel.
0xE4 SD Saturation Cr SD_SAT_CR [7:0]. Adjusts
saturation of the picture by 1 0 0 0 0 0 0 0 Chroma gain = 0 dB
affecting gain on the Cr channel.

Rev. B | Page 90 of 104

 ADV7181
Table 202. Registers 0xE5 to 0xE7
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments
0xE5 NTSC V Bit NVBEG[4:0]. How many lines after lCOUNT rollover
Begin to set V high. 0 0 1 0 1 NTSC default (BT.656)
NVBEGSIGN.
0 Set to low when manual
programming
1 Not suitable for user
programming
NVBEGDELE. Delay V bit going high by one line
relative to NVBEG (even field). 0 No delay
1 Additional delay by 1 line
NVBEGDELO. Delay V bit going high by one line
relative to NVBEG (odd field). 0 No delay
1 Additional delay by 1 line
0xE6 NTSC V Bit NVEND[4:0]. How many lines after lCOUNT rollover
End to set V low. 0 0 1 0 0 NTSC default (BT.656)
NVENDSIGN.
0 Set to low when manual
programming
1 Not suitable for user
programming
NVENDDELE. Delay V bit going low by one line
relative to NVEND (even field). 0 No delay
1 Additional delay by 1 line
NVENDDELO. Delay V bit going low by one line
relative to NVEND (odd field). 0 No delay
1 Additional delay by 1 line
0xE7 NTSC F Bit NFTOG[4:0]. How many lines after lCOUNT rollover
Toggle to toggle F signal. 0 0 0 1 1 NTSC default
NFTOGSIGN.
0 Set to low when manual
programming
1 Not suitable for user
programming
NFTOGDELE. Delay F transition by one line
relative to NFTOG (even field). 0 No delay
1 Additional delay by 1 line
NFTOGDELO. Delay F transition by one line
relative to NFTOG (odd field). 0 No delay
1 Additional delay by 1 line

Rev. B | Page 91 of 104

ADV7181
Table 203. Registers 0xE8 to 0xEA
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments
0xE8 PAL V Bit PVBEG[4:0]. How many lines after lCOUNT rollover
Begin to set V high. 0 0 1 0 1 PAL default (BT.656)
PVBEGSIGN.
0 Set to low when manual
programming
1 Not suitable for user
programming
PVBEGDELE. Delay V bit going high by one line
relative to PVBEG (even field). 0 No delay
1 Additional delay by 1 line
PVBEGDELO. Delay V bit going high by one line
relative to PVBEG (odd field). 0 No delay
1 Additional delay by 1 line
0xE9 PAL V Bit PVEND[4:0]. How many lines after lCOUNT rollover
End to set V low. 1 0 1 0 0 PAL default (BT.656)
PVENDSIGN.
0 Set to low when manual
programming
1 Not suitable for user
programming
PVENDDELE. Delay V bit going low by one line
relative to PVEND (even field). 0 No delay
1 Additional delay by 1 line
PVENDDELO. Delay V bit going low by one line
relative to PVEND (odd field). 0 No delay
1 Additional delay by 1 line
0xEA PAL F Bit PFTOG[4:0]. How many lines after lCOUNT rollover
Toggle to toggle F signal. 0 0 0 1 1 PAL default (BT.656)
PFTOGSIGN.
0 Set to low when manual
programming
1 Not suitable for user
programming
PFTOGDELE. Delay F transition by one line
relative to PFTOG (even field). 0 No delay
1 Additional delay by 1 line
PFTOGDELO. Delay F transition by one line
relative to PFTOG (odd field). 0 No delay
1 Additional delay by 1 line

Rev. B | Page 92 of 104

 ADV7181

I2C PROGRAMMING EXAMPLES

MODE 1—CVBS INPUT (COMPOSITE VIDEO ON AIN6)
All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15–P8.
Table 204. Mode 1—CVBS Input
Register Address Register Value Notes
0x00 0x04 CVBS input
0x01 0x88 Turn off Hsync processor (SECAM only4).
0x17 0x41 Set CSFM to SH1.
0x2B 0xE2 AGC flash tweak.
0x3A 0x16 Power down ADC 1 and ADC 2.
0x50 0x04 Set DNR threshold.
0x51 0x24 Turn off FSC detect for IN LOCK status.
0xC3 0x05 Man mux AIN6 to ADC0 (0101).
0xC4 0x80 Set setadc_sw_man_en = 1.
0xD2 0x01 AGC flash tweak.
0xD3 0x01 AGC flash tweak.
0xDB 0x9B AGC flash tweak.
0x0E 0x85 ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
0x89 0x0D Recommended setting.
0x8D 0x9B Recommended setting.
0x8F 0x48 Recommended setting.
0xB5 0x8B Recommended setting.
0xD4 0xFB Recommended setting.
0xD6 0x6D Recommended setting.
0xE2 0xAF Recommended setting.
0xE3 0x00 Recommended setting.
0xE4 0xB5 Recommended setting.
0xE8 0xF3 Recommended setting.
0x0E 0x05 Recommended setting.
4
For all SECAM modes of operation, Hsync processor must be turned off.

Rev. B | Page 93 of 104

ADV7181
MODE 2—S-VIDEO INPUT (Y ON AIN1 AND C ON AIN4)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15–P8.
Table 205. Mode 2—S-Video Input
Register Address Register Value Notes
0x00 0x06 S-Video input.
0x01 0x88 Turn off HSYNC processor (SECAM only).1
0x2B 0xE2 AGC flash tweak.
0x3A 0x12 Power down ADC 2.
0x50 0x04 Set DNR threshold.
0x51 0x24 Turn off FSC detect for IN LOCK status.
0xC3 0x41 Man mux AIN2 to ADC0 (0001), AIN4 to ADC1 (0100).
0xC4 0x80 Set setadc_sw_man_en = 1.
0xD2 0x01 AGC flash tweak.
0xD3 0x01 AGC flash tweak.
0xDB 0x9B AGC flash tweak.
0x0E 0x85 ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
0xB5 0x8B Recommended setting.
0xD4 0xFB Recommended setting.
0xD6 0x6D Recommended setting.
0xE2 0xAF Recommended setting.
0xE3 0x00 Recommended setting.
0xE4 0xB5 Recommended setting.
0xE8 0xF3 Recommended setting.
0x0E 0x05 Recommended setting.
1
For all SECAM modes of operation, the Hsync processor must be turned off.

MODE 3—525i/625i YPrPb INPUT (Y ON AIN1, Pr ON AIN3, AND Pb ON AIN5)

All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15–P8.
Table 206. Mode 3—YPrPb Input 525i/625i
Register Address Register Value Notes
0x00 0x0A Y2 = AIN2, Pr2 = AIN3, Pb2 = AIN6.
0x01 0x88 Disable HSync PLL.1
0x2B 0xE2 AGC flash tweak.
0x3A 0x10 Set latch clock.
0x51 0x24 Turn off FSC detect for IN LOCK status.
0xC3 0xC9 Man mux AIN1 to ADC0 (1001), AIN3 to ADC1 (1100).
0xC4 0x8D Set setadc_sw_man_en = 1.
0xD2 0x01 AGC flash tweak.
0xD3 0x01 AGC flash tweak.
0xDB 0x9B AGC flash tweak.
0x0E 0x85 ADI recommended programming sequence. This sequence must be followed exactly when setting
up the decoder.
0xD6 0x6D Recommended setting.
0xE8 0xF3 Recommended setting.
0x0E 0x05 Recommended setting.
1
For all YPrPb input modes of operation, the Hsync processor must be turned off.

Rev. B | Page 94 of 104

 ADV7181
MODE 4—CVBS TUNER INPUT CVBS PAL ON AIN6
8-bit, ITU-R BT.656 output on P15–P8.
Table 207. Mode 4—Tuner Input CVBS PAL Only
Register Address Register Value Notes
0x07 0x01 Enable PAL autodetection only.
0x17 0x41 Set CSFM to SH1.
0x2B 0xE2 AGC flash tweak.
0x19 0xFA Stronger dot crawl reduction.
0x3A 0x16 Power down ADC 1 and ADC 2.
0x50 0x0A Set higher DNR threshold.
0x51 0x24 Turn off FSC detect for IN LOCK status.
0xC3 0x05 Man mux AIN6 to ADC0 (0101).
0xC4 0x80 Set setadc_sw_man_en = 1.
0xD2 0x01 AGC flash tweak.
0xD3 0x01 AGC flash tweak.
0xDB 0x9B AGC flash tweak.
0x0E 0x85 ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
0x89 0x0D Recommended setting.
0x8D 0x9B Recommended setting.
0x8F 0x48 Recommended setting.
0xB5 0x8B Recommended setting.
0xD4 0xFB Recommended setting.
0xD6 0x6D Recommended setting.
0xE2 0xAF Recommended setting.
0xE3 0x00 Recommended setting.
0xE4 0xB5 Recommended setting.
0xE8 0xF3 Recommended setting.
0x0E 0x05 Recommended setting.

Rev. B | Page 95 of 104

ADV7181

PCB LAYOUT RECOMMENDATIONS

The ADV7181 is a high precision, high speed mixed-signal It is also recommend to use a single ground plane for the entire
device. To achieve the maximum performance from the part, it board. This ground plane should have a spacing gap between
is important to have a well laid out PCB board. The following is the analog and digital sections of the PCB (see Figure 38).
a guide for designing a board using the ADV7181.
ADV7181
ANALOG INTERFACE INPUTS ANALOG
SECTION
DIGITAL
SECTION

04820-037
The inputs should receive care when being routed on the PCB.
Track lengths should be kept to a minimum, and 75 Ω trace
Figure 38. PCB Ground Layout
impedances should be used when possible. Trace impedances
other than 75 Ω also increase the chance of reflections. Experience has repeatedly shown that the noise performance is
the same or better with a single ground plane. Using multiple
POWER SUPPLY DECOUPLING ground planes can be detrimental because each separate ground
It is recommended to decouple each power supply pin with plane is smaller, and long ground loops can result.
0.1 µF and 10 nF capacitors. The fundamental idea is to have a
decoupling capacitor within about 0.5 cm of each power pin. In some cases, using separate ground planes is unavoidable. For
Also, avoid placing the capacitor on the opposite side of the PC those cases, it is recommended to at least place a single ground
board from the ADV7181; doing so interposes resistive vias in plane under the ADV7181. The location of the split should be
the path. The decoupling capacitors should be located between under the ADV7181. For this case, it is even more important to
the power plane and the power pin. Current should flow from place components wisely because the current loops are much
the power plane to the capacitor to the power pin. Do not make longer (current takes the path of least resistance). An example
the power connection between the capacitor and the power pin. of a current loop: power plane to ADV7181 to digital output
Placing a via underneath the 100 nF capacitor pads, down to the trace to digital data receiver to digital ground plane to analog
power plane, is generally the best approach (see Figure 37). ground plane.

VDD VIA TO SUPPLY

PLL
10nF 100nF Place the PLL loop filter components as close to the ELPF pin as
GND VIA TO GND possible. Do not place any digital or other high frequency traces
near these components. Use the values suggested in the data
04820-038

sheet with tolerances of 10% or less.

Figure 37. Recommend Power Supply Decoupling
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
It is particularly important to maintain low noise and good Try to minimize the trace length that the digital outputs have to
stability of PVDD. Careful attention must be paid to regulation, drive. Longer traces have higher capacitance, which requires
filtering, and decoupling. It is highly desirable to provide more current, which causes more internal digital noise. Shorter
separate regulated supplies for each of the analog circuitry traces reduce the possibility of reflections.
groups (AVDD, DVDD, DVDDIO, and PVDD).
Adding a 30 Ω and 50 Ω series resistor can suppress reflections,
Some graphic controllers use substantially different levels of reduce EMI, and reduce the current spikes inside the ADV7181.
power when active (during active picture time) and when idle If series resistors are used, place them as close as possible to the
(during horizontal and vertical sync periods). This can result in ADV7181 pins. However, try not to add vias or extra length to
a measurable change in the voltage supplied to the analog the output trace to make the resistors closer.
supply regulator, which can, in turn, produce changes in the
regulated analog supply voltage. This can be mitigated by If possible, limit the capacitance that each of the digital outputs
regulating the analog supply, or at least PVDD, from a different, drives to less than 15 pF. This can easily be accomplished by
cleaner, power source, for example, from a 12 V supply. keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside the ADV7181, creating more
digital noise on its power supplies.

Rev. B | Page 96 of 104

 ADV7181
DIGITAL INPUTS XTAL AND LOAD CAPACITOR VALUE SELECTION
The digital inputs on the ADV7181 were designed to work with Figure 40 shows an example reference clock circuit for the
3.3 V signals, and are not tolerant of 5 V signals. Extra compo- ADV7181. Special care must be taken when using a crystal
nents are needed if 5 V logic signals are required to be applied circuit to generate the reference clock for the ADV7181. Small
to the decoder. variations in reference clock frequency can cause autodetection
Antialiasing Filters issues and impair the ADV7181 performance.

For inputs from some video sources that are not bandwidth XTAL
27 MHz
limited, signals outside the video band can alias back into the

04820-040
video band during A/D conversion and appear as noise on the 33pF 33pF

output video. The ADV7181 oversamples the analog inputs by

a factor of 4. This 54 MHz sampling frequency reduces the Figure 40. Crystal Circuit
requirement for an input filter; for optimal performance it is
Use the following guidelines to ensure correct operation:
recommended that an antialiasing filter be used. The
recommended low cost circuit for implementing this buffer and • Use the correct frequency crystal, which is 27 MHz.
filter circuit for all analog input signals is shown in Figure 41. Tolerance should be 50 ppm or better.
• Use a parallel-resonant crystal.
The buffer is a simple emitter-follower using a single npn
transistor. The antialiasing filter is implemented using passive • Know the Cload for the crystal part number selected. The
components. The passive filter is a third-order Butterworth value of Capacitors C1 and C2 must match Cload for the
filter with a –3 dB point of 9 MHz. The frequency response of specific crystal part number in the user’s system.
the passive filter is shown in Figure 39. The flat pass band up to
6 MHz is essential. The attenuation of the signal at the output of To find Cload, use the following formula:
the filter due to the voltage divider of R24 and R63 is compen-
sated for in the ADV7181 part using the automatic gain control. C1 = C2 = 2Cload – Cstray
The ac coupling capacitor at the input to the buffer creates a
high-pass filter with the biasing resistors for the transistor. This where Cstray is 3 pF to 8 pF, depending on board traces.
filter has a cutoff of
Example
{2 × π × (R39||R89) × C93}–1 = 0.62 Hz

It is essential that the cutoff of this filter be less than 1 Hz to Cload = 20 pF

ensure correct operation of the internal clamps within the part. C1 = 33 pF
These clamps ensure that the video stays within the 5 V range C2 = 33 pF
of the op amp used.
0

–20

–40

–60

–80

–100
04820-039

–120
100kHz 300kHz 1MHz 3MHz 10MHz 30MHz 100MHz 300MHz 1GHz
FREQUENCY

Figure 39. Third-Order Butterworth Filter Response

Rev. B | Page 97 of 104

ADV7181

TYPICAL CIRCUIT CONNECTION

Examples of how to connect the ADV7181 video decoder are shown in Figure 41 and Figure 42.
AVDD_5V

R43
BUFFER 0Ω

C93 R39 C
100µF 4.7kΩ
B FILTER
Q6
R53 L10
56Ω E 12µH
R38 R89
75Ω 5.6kΩ R24 C95 C102 R63
470Ω 22pF 10pF 820Ω

04820-042
AGND

Figure 41. ADI Recommended Antialiasing Circuit for All Input Channels

Rev. B | Page 98 of 104

 ADV7181
FERITE BEAD
DVDDIO
(3.3V)
33µF 10µF 0.1µF 0.01µF POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
DGND DGND DGND DGND
FERITE BEAD
PVDD
(1.8V)
33µF 10µF 0.1µF 0.01µF POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
AGND AGND AGND AGND
FERITE BEAD
AVDD
(3.3V)
33µF 10µF 0.1µF 0.01µF POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
AGND AGND AGND AGND
FERITE BEAD
AGND DGND DVDD
(1.8V)
33µF 10µF 0.1µF 0.01µF POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
DGND DGND DGND DGND
S-VIDEO ANTI-ALIAS
FILTER CIRCUIT
100nF

AVDD

DVDDIO
DVDD

PVDD
P0
ANTI-ALIAS AIN2 P1
FILTER CIRCUIT P2
100nF P3
ANTI-ALIAS AIN1 P4
Y P5
FILTER CIRCUIT
100nF P6
AIN3 MULTI
ANTI-ALIAS P7 FORMAT
Pr P8
FILTER CIRCUIT ADV7181 PIXEL
100nF P9 PORT
ANTI-ALIAS AIN4 P10
Pb P11 P15–P8 8-BIT ITU-R BT.656 PIXEL DATA @ 27MHz
FILTER CIRCUIT P12
100nF P7–P0 Cb AND Cr 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz
AIN5 P13 P15–P8 Y1 AND Y2 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz
CBVS ANTI-ALIAS P14
FILTER CIRCUIT P15
100nF
AIN6
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω

RECOMMENDED ANTI-ALIAS FILTER

CIRCUIT IS SHOWN IN FIGURE 40 ON THE
PREVIOUS PAGE. THIS CIRCUIT INCLUDES
A 75Ω TERMINATION RESISTOR, INPUT
BUFFER AND ANTI-ALIASING FILTER. AGND
CAP Y1
+
0.1µF 10µF 0.1µF 0.1nF
LLC 27MHz OUTPUT CLOCK
CAP Y2

0.1µF
AGND
+
10µF 0.1µF 0.1nF
AGND CAP C2

CML
+
10µF 0.1µF REFOUT
+
10µF 0.1µF

AGND SFL SFL O/P

XTAL HS HS O/P
33pF 27MHz
VS VS O/P
DVDDIO XTAL1 FIELD FIELD O/P
DGND
33pF
DVDDIO
SELECT I2C
ADDRESS DGND

PWRDN
DVSS ALSB
ELPF
DVDDIO DVDDIO
1.69kΩ 10nF
2kΩ 2kΩ 82nF
33Ω
SCLK
MPU INTERFACE
CONTROL LINES 33Ω
SDA PVDD
DVDDIO

4.7kΩ
RESET RESET AGND DGND
100nF
04820-041

DGND AGND DGND

Figure 42. Typical Connection Diagram

Rev. B | Page 99 of 104

ADV7181

OUTLINE DIMENSIONS
0.30
9.00 0.60 MAX 0.25
BSC SQ 0.18
0.60 MAX PIN 1
INDICATOR
49 64
48 1
PIN 1
INDICATOR

TOP 7.25
8.75 BOTTOM
VIEW BSC SQ 7.10 SQ*
VIEW
6.95

0.45
0.40 33 16
32 17
0.35
0.25 MIN
7.50 REF
0.80 MAX
1.00 12° MAX 0.65 TYP
0.85
0.80 0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
SEATING
PLANE
* COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION

Figure 43. 64-Lead Lead Frame Chip Scale Package [LFCSP]

9 mm × 9 mm Body
(CP-64-3)
Dimensions shown in millimeters

0.75 12.00
0.60 1.60 BSC SQ
0.45 MAX
64 49
1 48

SEATING PIN 1
PLANE

TOP VIEW 10.00

(PINS DOWN) BSC SQ
10°
1.45 6°
0.20
1.40 2°
0.09 VIEW A
1.35
7°
3.5° 16 33
0.15 0° 17 32
0.05 SEATING 0.08 MAX
PLANE COPLANARITY 0.27
0.50
BSC 0.22
VIEW A 0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BCD

Figure 44. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)
Dimensions shown in Millimeters

Rev. B | Page 100 of 104

 ADV7181
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADV7181BCP –40°C to +85°C Lead Frame Chip Scale Package (LFCSP) CP-64-3
ADV7181BST –40°C to +85°C Low Profile Quad Flat Package (LQFP) ST-64-2
EVAL-ADV7181BEB Evaluation Board

The ADV7181 is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The
coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface-
mount soldering at up to 255°C (±5°C).

In addition, it is backward-compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be
soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C.

The ADV7181 evaluation board is now obsolete. For new evaluation and design, the ADV7181B evaluation board is recommended.

Rev. B | Page 101 of 104

ADV7181

NOTES

Rev. B | Page 102 of 104

 ADV7181

NOTES

Rev. B | Page 103 of 104

ADV7181

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04820–0–3/05(B)

Rev. B | Page 104 of 104