// sdn_fpga_testbench.

v - Testbench for SDN on FPGA implementation

`timescale 1ns / 1ps

module sdn_fpga_tb ();

// Testbench parameters
localparam CLK_PERIOD = 10; // 100 MHz clock

// Test signals
reg clk;
reg rst_n;
reg [7:0] rx_data;
reg rx_valid;
wire rx_ready;
wire [7:0] tx_data;
wire tx_valid;
reg tx_ready;
reg [7:0] ctrl_data;
reg ctrl_valid;
wire ctrl_ready;
wire [7:0] status;
wire [7:0] led;

// Counters and testing variables

integer i;
integer error_count;
reg [31:0] packet_key;
reg [7:0] packet_action;

// Test packet data

reg [7:0] test_packet_1 [0:19]; // 20-byte test packet
reg [7:0] test_packet_2 [0:19]; // 20-byte test packet

// Instantiate the module under test

sdn_fpga_top dut (
.clk (clk),
.rst_n (rst_n),
.rx_data (rx_data),
.rx_valid (rx_valid),
.rx_ready (rx_ready),
.tx_data (tx_data),
.tx_valid (tx_valid),
.tx_ready (tx_ready),
.ctrl_data (ctrl_data),
.ctrl_valid (ctrl_valid),
.ctrl_ready (ctrl_ready),
.status (status),
.led (led)
);

// Clock generation
initial begin
clk = 0;
forever #(CLK_PERIOD/2) clk = ~clk;
end

// Initialize test data

initial begin
// Initialize test packet 1 (will be dropped without flow rule)
 for (i = 0; i < 20; i = i + 1) begin
if (i < 4) begin
test_packet_1[i] = 8'h10 + i; // Header: 0x10, 0x11, 0x12, 0x13
end else begin
test_packet_1[i] = 8'h20 + i; // Data
end
end

// Initialize test packet 2 (different flow)

for (i = 0; i < 20; i = i + 1) begin
if (i < 4) begin
test_packet_2[i] = 8'h20 + i; // Header: 0x20, 0x21, 0x22, 0x23
end else begin
test_packet_2[i] = 8'h30 + i; // Data
end
end

// Initialize test signals

rst_n = 1;
rx_valid = 0;
tx_ready = 1;
ctrl_valid = 0;
error_count = 0;
end

// Tasks for sending control and packet data

// Task for sending control commands

task send_control_data;
input [7:0] data;
begin
@(posedge clk);
ctrl_data = data;
ctrl_valid = 1'b1;

// Wait until ready

wait(ctrl_ready);
@(posedge clk);

// Hold for one cycle

@(posedge clk);
ctrl_valid = 1'b0;
end
endtask

// Task for adding a flow rule

task add_flow_rule;
input [31:0] key;
input [7:0] action;
begin
// Send command
send_control_data(8'h02); // CMD_ADD_FLOW

// Send key (4 bytes)

send_control_data(key[7:0]);
send_control_data(key[15:8]);
send_control_data(key[23:16]);
send_control_data(key[31:24]);
 // Send action
send_control_data(action);

// Wait for flow update to complete

wait(status == 8'h02);
@(posedge clk);
end
endtask

// Task for deleting a flow rule

task delete_flow_rule;
input [31:0] key;
begin
// Send command
send_control_data(8'h03); // CMD_DEL_FLOW

// Send key (4 bytes)

send_control_data(key[7:0]);
send_control_data(key[15:8]);
send_control_data(key[23:16]);
send_control_data(key[31:24]);

// Wait for flow update to complete

wait(status == 8'h02);
@(posedge clk);
end
endtask

// Task for sending a packet

task send_packet;
input [7:0] packet [];
input integer size;
begin
// Wait for ready
wait(rx_ready);

// Send packet byte by byte

for (i = 0; i < size; i = i + 1) begin
@(posedge clk);
rx_data = packet[i];
rx_valid = 1'b1;

// Wait for ready

wait(rx_ready);
@(posedge clk);
end

// End packet
@(posedge clk);
rx_valid = 1'b0;
@(posedge clk);
end
endtask

// Task for checking received packet

task check_packet;
input [7:0] expected [];
input integer size;
begin
 // Variables
integer j;
reg error;

j = 0;
error = 0;

// Wait for packet to start transmission

wait(tx_valid);

// Check packet byte by byte

for (j = 0; j < size; j = j + 1) begin
// Wait for valid data
wait(tx_valid);
@(posedge clk);

// Check value
if (tx_data !== expected[j]) begin
$display("ERROR: Packet byte %0d mismatch. Expected: %h, Got:
%h",
j, expected[j], tx_data);
error = 1;
error_count = error_count + 1;
end

// Next byte
tx_ready = 1'b1;
@(posedge clk);
end

// Display result
if (!error) begin
$display("INFO: Packet correctly forwarded");
end
end
endtask

// Check if packet is dropped (no tx_valid after timeout)

task check_packet_dropped;
input integer timeout_cycles;
begin
integer timeout;

timeout = 0;
tx_ready = 1'b1;

// Wait for timeout cycles or tx_valid

while (timeout < timeout_cycles && !tx_valid) begin
@(posedge clk);
timeout = timeout + 1;
end

// Check result
if (tx_valid) begin
$display("ERROR: Packet was forwarded when it should have been
dropped");
error_count = error_count + 1;
end else begin
$display("INFO: Packet correctly dropped");
 end
end
endtask

// Main test sequence

initial begin
// Reset sequence
#100;
rst_n = 0;
#50;
rst_n = 1;
#100;

$display("Starting SDN on FPGA test");

// Test 1: Send packet without flow rule (should be dropped)

$display("\nTest 1: Send packet without flow rule");
send_packet(test_packet_1, 20);
check_packet_dropped(50);

// Test 2: Add flow rule and send matching packet

$display("\nTest 2: Add flow rule and send matching packet");
packet_key = {test_packet_1[3], test_packet_1[2], test_packet_1[1],
test_packet_1[0]};
packet_action = 8'h01; // ACTION_FORWARD
add_flow_rule(packet_key, packet_action);
#50;
send_packet(test_packet_1, 20);
check_packet(test_packet_1, 20);

// Test 3: Send non-matching packet (should be dropped)

$display("\nTest 3: Send non-matching packet");
send_packet(test_packet_2, 20);
check_packet_dropped(50);

// Test 4: Add second flow rule and verify both work

$display("\nTest 4: Add second flow rule");
packet_key = {test_packet_2[3], test_packet_2[2], test_packet_2[1],
test_packet_2[0]};
packet_action = 8'h01; // ACTION_FORWARD
add_flow_rule(packet_key, packet_action);
#50;

// Test packet 1 (should be forwarded)

send_packet(test_packet_1, 20);
check_packet(test_packet_1, 20);

// Test packet 2 (should be forwarded)

send_packet(test_packet_2, 20);
check_packet(test_packet_2, 20);

// Test 5: Delete flow rule and verify packet is dropped

$display("\nTest 5: Delete flow rule");
packet_key = {test_packet_1[3], test_packet_1[2], test_packet_1[1],
test_packet_1[0]};
delete_flow_rule(packet_key);
#50;

// Test packet 1 again (should be dropped)

 send_packet(test_packet_1, 20);
check_packet_dropped(50);

// Test packet 2 (should still be forwarded)

send_packet(test_packet_2, 20);
check_packet(test_packet_2, 20);

// Test 6: Check control plane status

$display("\nTest 6: Check control plane status");
send_control_data(8'h01); // CMD_STATUS
#50;

// Display final results

if (error_count == 0) begin
$display("\nTEST PASSED: All tests completed successfully");
end else begin
$display("\nTEST FAILED: %0d errors detected", error_count);
end

// Finish simulation
#100;
$finish;
end

// Monitor for debug output

initial begin
$monitor("Time: %0t, Status: %h, LEDs: %b", $time, status, led);
end

endmodule