I2C Controller IP User Guide
I2C Controller IP User Guide
IP Version: v2.2.0
User Guide
FPGA-IPUG-02071-1.9
December 2024
I2C Controller IP
User Guide
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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I2C Controller IP
User Guide
Contents
Contents ............................................................................................................................................................................... 3
Acronyms in This Document ................................................................................................................................................. 6
1. Introduction .................................................................................................................................................................. 7
1.1. Overview of the IP ............................................................................................................................................... 7
1.2. Quick Facts .......................................................................................................................................................... 7
1.3. IP Support Summary ........................................................................................................................................... 7
1.4. Features .............................................................................................................................................................. 8
1.5. Licensing Information .......................................................................................................................................... 8
1.6. Hardware Support ............................................................................................................................................... 8
1.7. Minimum Device Requirements ......................................................................................................................... 8
1.8. Naming Conventions ........................................................................................................................................... 9
1.8.1. Nomenclature................................................................................................................................................. 9
1.8.2. Signal Names .................................................................................................................................................. 9
2. Functional Description ................................................................................................................................................ 10
2.1. IP Architecture Overview .................................................................................................................................. 10
2.2. Clocking and Reset ............................................................................................................................................ 10
2.3. Operations Details ............................................................................................................................................. 11
2.3.1. General I2C Operation .................................................................................................................................. 11
2.3.2. Clock Generation and Synchronization ........................................................................................................ 11
2.3.3. Glitch Filter ................................................................................................................................................... 12
2.3.4. Clock Stretching and SCL Timeout ................................................................................................................ 12
2.3.5. Multi-controller Arbitration ......................................................................................................................... 12
2.4. User Interfaces .................................................................................................................................................. 12
2.4.1. Selectable Memory-Mapped Interface ........................................................................................................ 12
2.5. Programming Flow ............................................................................................................................................ 13
2.5.1. Initialization .................................................................................................................................................. 13
2.5.2. Write to a Target Device .............................................................................................................................. 13
2.5.3. Read from a Target Device ........................................................................................................................... 13
2.5.4. Read from a Target Device with a Specific Register or Command (Repeated Start) .................................... 14
3. IP Parameter Description ............................................................................................................................................ 16
4. Signal Description ....................................................................................................................................................... 17
5. Register Description ................................................................................................................................................... 19
5.1. Overview ........................................................................................................................................................... 19
5.2. Write Data Register (WR_DATA_REG) .............................................................................................................. 20
5.3. Read Data Register (RD_DATA_REG) ................................................................................................................ 20
5.4. Target Address Registers (TARGET_ADDRL_REG, TARGET_ADDRH_REG) ........................................................ 20
5.5. Control Register (CONTROL_REG) ..................................................................................................................... 20
5.6. Target Byte Count Register (TGT_BYTE_CNT_REG) .......................................................................................... 21
5.7. Mode Register (MODE_REG) ............................................................................................................................. 21
5.8. Clock Prescaler Low Register (CLK_PRESCL_REG) ............................................................................................. 22
5.9. Interrupt Status Registers (INT_STATUS1_REG, INT_STATUS2_REG) ............................................................... 22
5.10. Interrupt Enable Registers (INT_ENABLE1_REG, INT_ENABLE2_REG) .............................................................. 24
5.11. Interrupt Set Registers (INT_SET1_REG, INT_SET2_REG).................................................................................. 26
5.12. FIFO Status Register (FIFO_STATUS_REG) ......................................................................................................... 27
5.13. SCL Timeout Register (SCL_TIMEOUT_REG) ...................................................................................................... 28
6. Example Design........................................................................................................................................................... 29
6.1. Example Design Supported Configuration ........................................................................................................ 29
6.2. Overview of the Example Design and Features ................................................................................................ 29
6.3. Design Components Example ............................................................................................................................ 31
6.4. Generating the Example Design ........................................................................................................................ 31
6.5. Hardware Testing .............................................................................................................................................. 34
6.5.1. Hardware Testing Setup ............................................................................................................................... 34
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 3
I2C Controller IP
User Guide
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 4
I2C Controller IP
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Figures
Figure 2.1. I2C Controller IP Functional Diagram................................................................................................................ 10
Figure 2.2. START and STOP Conditions ............................................................................................................................. 11
Figure 6.1. I2C Controller IP in Propel SoC Project ............................................................................................................. 30
Figure 6.2. Sample C-Code Test Routine............................................................................................................................. 30
Figure 6.3. I2C Controller Example Design Block Diagram ................................................................................................. 31
Figure 6.4. Create SoC Project ............................................................................................................................................ 32
Figure 6.5. Define Instance ................................................................................................................................................. 32
Figure 6.6. Build SoC Project Result .................................................................................................................................... 33
Figure 6.7. Lattice C/C++ Design Project ............................................................................................................................. 33
Figure 6.8. Build C/C++ Project Result ................................................................................................................................ 34
Figure 6.9 Sample I2C Read Command Sent by I2C Controller ........................................................................................... 34
Figure 7.1. Module/IP Block Wizard ................................................................................................................................... 35
Figure 7.2. Configure User Interface of I2C Controller IP ................................................................................................... 36
Figure 7.3. Check Generating Result ................................................................................................................................... 36
Figure 7.4. Simulation Wizard ............................................................................................................................................. 38
Figure 7.5. Add and Reorder Source ................................................................................................................................... 38
Figure 7.6. Simulation Waveform ....................................................................................................................................... 39
Tables
Table 1.1. Summary of the I2C Controller IP ........................................................................................................................ 7
Table 1.2. I2C Controller IP Support Readiness .................................................................................................................... 7
Table 3.1. Attributes Table ................................................................................................................................................. 16
Table 3.2. Attributes Descriptions ...................................................................................................................................... 16
Table 4.1. I2C Controller IP Signal Description ................................................................................................................... 17
Table 5.1. Registers Address Map....................................................................................................................................... 19
Table 5.2. Access Type Definition ....................................................................................................................................... 19
Table 5.3. Write Data Register ............................................................................................................................................ 20
Table 5.4. Read Data Register ............................................................................................................................................. 20
Table 5.5. Target Address Lower Register .......................................................................................................................... 20
Table 5.6. Target Address Higher Register ......................................................................................................................... 20
Table 5.7. Control Register ................................................................................................................................................. 20
Table 5.8. Target Byte Count Register ................................................................................................................................ 21
Table 5.9. Mode Register .................................................................................................................................................... 21
Table 5.10. Clock Prescaler Low Register ........................................................................................................................... 22
Table 5.11. Interrupt Status First Register .......................................................................................................................... 22
Table 5.12. Interrupt Status Second Register ..................................................................................................................... 23
Table 5.13. Interrupt Enable First Register ......................................................................................................................... 24
Table 5.14. Interrupt Enable Second Register .................................................................................................................... 25
Table 5.15. Interrupt Set First Register ............................................................................................................................... 26
Table 5.16. Interrupt Set Second Register .......................................................................................................................... 26
Table 5.17. FIFO Status Register ......................................................................................................................................... 27
Table 5.18. SCL Timeout Register ....................................................................................................................................... 28
Table 6.1. I2C Controller IP Configuration Supported by the Example Design ................................................................... 29
Table 7.1. Generated File List ............................................................................................................................................. 37
Table A.1. LIFCL-40-9BG400I Device Resource Utilization .................................................................................................. 40
Table A.2. LAV-AT-E70-1LFG1156I Device Resource Utilization ......................................................................................... 40
Table A.3. LN2-CT-20-1CBG484C Device Resource Utilization ........................................................................................... 40
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 5
I2C Controller IP
User Guide
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 6
I2C Controller IP
User Guide
1. Introduction
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 7
I2C Controller IP
User Guide
1.4. Features
The I2C Controller IP supports the following key features:
• Supports 7-bit and 10-bit Addressing Mode
• Programmable SCL frequency, supporting the following bus speeds:
• Standard-mode (Sm) – up to 100 kbit/s
• Fast-mode (Fm) – up to 400 kbit/s
• Fast-mode Plus (Fm+) – up to 1 Mbit/s
• Integrated Pull-up
• Integrated Glitch filter
• Arbitration lost detection in multi-controller system
• Polling and Out-of-band Interrupt Modes
• Selectable LMMI or APB interface
• Supports Clock stretching
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 8
I2C Controller IP
User Guide
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 9
I2C Controller IP
User Guide
2. Functional Description
This section provides a detailed functional description of the I2C Controller IP which includes information regarding
clock and reset handling, and user interfaces.
clk_i
apb_psel_i
lmmi_request_i
I2C INTERFACE
apb_penable_i
APB INTERFACE
LMMI INTERFACE
lmmi_wr_rdn_i
apb_pwrite_i lmmi_offset_i[3:0] I2C
(Optional)
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FPGA-IPUG-02071-1.9 10
I2C Controller IP
User Guide
scl_io
sda_io
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 11
I2C Controller IP
User Guide
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 12
I2C Controller IP
User Guide
© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02071-1.9 13
I2C Controller IP
User Guide
2.5.4. Read from a Target Device with a Specific Register or Command (Repeated Start)
Below are the recommended steps for performing a combined I2C read transaction. This assumes that the module is
not currently performing any operation and initialization is completed.
To perform write transaction of a combined I2C transaction:
1. Set the following MODE_REG fields according to the desired transfer mode: bus_speed_mode, addr_mode,
clk_presc_high. Set the trx_mode field to 1’b0 for write transaction.
2. Set TGT_BYTE_CNT_REG according to the number of bytes to transfer.
3. Write data to WR_DATA_REG, amounting to <= FIFO Depth. Write the target register and commands needed.
4. Set CONTROL_REG.repeated_start to 1’b1 and CONTROL_REG.start to 1’b1 to start the I2C transaction.
5. Optional: If interrupt mode is desired, enable target interrupts in INT_ENABLE1_REG.
If number of words to transfer is <= FIFO Depth, set tr_cmp_en = 1’b1.
If number of words to transfer is > FIFO Depth, set the following: tx_fifo_aempty_en = 1’b1 and tr_cmp_en = 1’b1.
Other interrupts in this register are disabled.
6. If total number of bytes to transfer > FIFO Depth, wait for Transmit FIFO Almost Empty Interrupt.
If polling mode is desired (interrupts are disabled), read INT_STATUS1_REG until tx_fifo_aempty_int asserts.
If interrupt mode is desired, simply wait for interrupt signal to assert, then read INT_STATUS1_REG and check that
tx_fifo_aempt_int is asserted.
In both cases, read also INT_STATUS2_REG to ensure that the transfer is good.
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I2C Controller IP
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7. Clear Transmit Buffer Almost Empty Interrupt by writing 1’b1 to INT_STATUS1_REG.tx_fifo_aempty_int. Clearing all
interrupts in this register by writing 8’hFF to INT_STATUS1_REG is also okay since we are not interested in other
interrupts for this recommended sequence.
8. Write data to WR_DATA_REG, amounting to less than or equal to (FIFO Depth – TX FIFO Almost Empty Flag).
9. If there is remaining data to transfer, go back to Step 6.
10. Wait for Transfer Complete Interrupt.
If polling mode is desired (interrupts are disabled), read INT_STATUS1_REG until tr_cmp_int asserts.
If interrupt mode is desired, set INT_ENABLE1_REG = 8’h80 then wait for interrupt signal to assert. Then, read
INT_STATUS1_REG and check that tr_cmp_int is asserted.
11. Clear all interrupts by writing 8’hFF to INT_STATUS1_REG.
To perform read transaction of a combined I2C transaction:
12. Set the following MODE_REG fields according to the desired transfer mode: bus_speed_mode, addr_mode,
ack_mode, clk_presc_high. Set the trx_mode field to 1’b1 for read transaction.
13. Set TGT_BYTE_CNT_REG according to the number of bytes to transfer.
14. Set CONTROL_REG.repeated_start to 1’b0 and CONTROL_REG.start to 1’b1 to start the I2C transaction.
15. Optional: If interrupt mode is desired, enable target interrupts in INT_ENABLE1_REG.
If number of words to transfer is <= FIFO Depth, set tr_cmp_en = 1’b1.
If number of words to transfer is > FIFO Depth, set the following: rx_fifo_afull_en = 1’b1 and tr_cmp_en = 1’b1.
Other interrupts in this register are disabled.
16. If total number of bytes to receive > FIFO Depth, wait for Receive FIFO Almost Full Interrupt.
If polling mode is desired (interrupts are disabled), read INT_STATUS1_REG until rx_fifo_afull_int asserts.
If interrupt mode is desired, simply wait for interrupt signal to assert. Then, read INT_STATUS1_REG and check that
rx_fifo_afull_int is asserted.
In both cases, read also INT_STATUS2_REG to ensure that the transfer is good.
17. Clear Receive FIFO Almost Full Interrupt by writing 1’b1 to INT_STATUS1_REG.rx_fifo_afull_int. Clearing all
interrupts in this register by writing 8’hFF to INT_STATUS1_REG is also okay since we are not interested in other
interrupts for this recommended sequence.
18. Read all data from RD_DATA_REG. It is expected the amount of received data is less than or equal to (FIFO Depth –
TX FIFO Almost Empty Flag). Read FIFO_STATUS_REG to confirm if Receive FIFO is emptied.
19. If there is remaining data to receive, go back to Step 16.
20. Wait for Transfer Complete Interrupt.
If polling mode is desired (interrupts are disabled), read INT_STATUS1_REG until tr_cmp_int asserts.
If interrupt mode is desired, set INT_ENABLE1_REG = 8’h80 then wait for interrupt signal to assert. Then read
INT_STATUS1_REG and check that tr_cmp_int is asserted.
21. Clear all interrupts by writing 8’hFF to INT_STATUS1_REG.
22. Read all the remaining data from RD_DATA_REG.
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I2C Controller IP
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3. IP Parameter Description
The configurable attributes of the I2C Controller IP are shown in Table 3.1 and are described in Table 3.2. The attributes
can be configured through the IP Catalog Module/IP wizard of the Lattice Radiant software.
Table 3.1. Attributes Table
Attribute Selectable Values Default Dependency on Other Attributes
General
APB Mode Enable Checked, Unchecked Checked —
Remove Tristate Buffers Checked, Unchecked Unchecked —
FIFO
FIFO Width 8 8 —
FIFO Depth 16, 32, 64, 128, 256 16 —
Implementation of FIFO EBR, LUT LUT —
TX FIFO Almost Empty Flag 1 – 256 2 Less than or equal to FIFO Depth.
RX FIFO Almost Full Flag 1 – 256 14 Less than or equal to FIFO Depth.
Clock
System Clock Frequency (MHz) 10 - 200 50 —
Desired SCL Frequency (kHz) 100 - 1000 100 —
Clock Prescaler 1 - 2047 247 Calculated based on System Clock
Frequency and Desired SCL Frequency.
Actual SCL Frequency (kHz) Output Value 100 Calculated based on System Clock
Frequency and Clock Prescaler.
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I2C Controller IP
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4. Signal Description
Table 4.1 lists the input and output signals for the I2C Controller IP.
Table 4.1. I2C Controller IP Signal Description
Port Name I/O Width Description
Clock and Reset
clk_i In 1 System clock
rst_n_i In 1 Asynchronous active low reset
The reset assertion can be asynchronous but reset negation should be
synchronous. When asserted, output ports and registers are forced to their
reset values.
Interrupt Port
int_o Out 1 Interrupt signal
Reset value is 1’b0.
I2C Interface (Remove Tristate Buffers = 0)
I2C Serial Clock
Generated by the I2C Controller to synchronize data transfers. Selected from
scl_io In/Out 1
the user interface.
Reset value is weak high (pull-up).
I2C data signal
sda_io In/Out 1
Reset value is weak high (pull-up).
I2C Interface (Remove Tristate Buffers = 1)
I2C serial clock input
In 1
scl_i Input from tristate buffer.
I2C serial clock output
scl_o Out 1
Output to tristate buffer. This signal is fixed to 1’b0.
I2C serial clock output enable
scl_oe_o Out 1
Signal to enable output of a tristate buffer. Reset value is 1’b0.
I2C data signal input
sda_i In 1
Input from tristate buffer.
I2C data signal output
sda_o Out 1
Output to tristate buffer. This signal is fixed to 1’b0.
I2C data signal output enable
sda_oe_o Out 1
Signal to enable output of a tristate buffer. Reset value is 1’b0.
LMMI Interface*
lmmi_request_i In 1 Start transaction
lmmi_wr_rdn_i In 1 Write = 1’b1, Read = 1’b0
lmmi_offset_i In 4 Register offset, starting at offset 0
lmmi_wdata_i In 8 Input data bus
lmmi_rdata_o Out 8 Output data bus
Reset value is 0.
lmmi_rdata_valid_o Out 1 Read transaction is complete and lmmi_rdata_o contains valid data.
Reset value is 1’b0.
lmmi_ready_o Out 1 IP is ready to receive a new transaction. This is always asserted (tied to 1’b1).
APB Interface*
apb_psel_i In 1 APB Select signal
Indicates that the device is selected and a data transfer is required.
apb_paddr_i In 6 APB Address signal
apb_pwdata_i In 32 APB Write data signal
Bits [31:8] are not used.
apb_pwrite_i In 1 APB Direction signal
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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I2C Controller IP
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© 2024 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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I2C Controller IP
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5. Register Description
5.1. Overview
You can control the I2C Controller IP by writing to and reading from the configuration registers. The I2C Controller IP
configuration registers can be performed at the run-time.
Table 5.1 lists the address map and specifies the registers available to you. The offset of each register is dependent on
attribute APB Mode Enable setting as follows:
• APB Mode Enable is Unchecked – the offset increments by 1.
• APB Mode Enable is Checked – the offset increments by 4 to allow easy interfacing with the Processor and System
Buses. It this mode, each register is 32-bit wide wherein the upper bits [31:8] are reserved and the lower 8 bits
[7:0] are described in the next section.
Table 5.1. Registers Address Map
Offset Offset APB Register Name Access Description
LMMI Type
0x0 0x00 WR_DATA_REG WO Write Data Register
0x0 0x00 RD_DATA_REG RO Read Data Register
0x1 0x04 TARGET_ADDRL_REG RW Target Address Lower Register
0x2 0x08 TARGET_ADDRH_REG RW Target Address Higher Register
0x3 0x0C CONTROL_REG WO Control Register
0x4 0x10 TGT_BYTE_CNT_REG RW Byte Count Register
0x5 0x14 MODE_REG RW Mode Register
0x6 0x18 CLK_PRESCL_REG RW Clock Prescaler Low Register
0x7 0x1C INT_STATUS1_REG RW1C First Interrupt Status Register
0x8 0x20 INT_ENABLE1_REG RW First Interrupt Enable Register
0x9 0x24 INT_SET1_REG WO First Interrupt Set Register
0xA 0x28 INT_STATUS2_REG RW1C Second Interrupt Status Register
0xB 0x2C INT_ENABLE2_REG RW Second Interrupt Enable Register
0xC 0x30 INT_SET2_REG WO Second Interrupt Set Register
0xD 0x34 FIFO_STATUS_REG RO FIFO Status Register
0xE 0x38 SCL_TIMEOUT_REG RW SCL Timeout Register
0xF 0x3C Reserved RSVD Reserved
Write access is ignored and 0 is returned on read access.
The RD_DATA_REG and WR_DATA_REG share the same offset. Write access to this offset goes to WR_DATA_REG while
read access goes to RD_DATA_REG.
The behavior of registers to write and read access is defined by its access type, which is defined in Table 5.2.
Table 5.2. Access Type Definition
Access Type Behavior on Read Access Behavior on Write Access
RO Returns register value Ignores write access
WO Returns 0 Updates register value
RW Returns register value Updates register value
RW1C Returns register value Writing 1’b1 on register bit clears the bit to 1’b0.
Writing 1’b0 on register bit is ignored.
RSVD Returns 0 Ignores write access
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The Target Address Higher Register (TARGET_ADDRH_REG) shown in Table 5.6 is the upper 3 bits of 10-bit Target
address. This is not used in 7-bit addressing mode.
Table 5.6. Target Address Higher Register
Field Name Access Width Reset
[7:3] reserved RSVD 5 —
[2:0] target_addr_h_reg RW 3 3’h0
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• rx_fifo_reset
Resets the Receive FIFO logic, effectively flushing the contents. This is write-only bit because it has an auto clear
feature; it is cleared to 1’b0 after 1 clock cycle.
1’b0 – No action.
1’b1 – Resets the Receive FIFO.
• tx_fifo_reset
Resets the Transmit FIFO logic, effectively flushing the contents. This is write-only bit because it has an auto clear
feature; it is cleared to 1’b0 after 1 clock cycle.
1’b0 – No action.
1’b1 – Resets the Transmit FIFO.
• repeated_start
Repeated Start. Causes I2C Controller to omit the generation of a stop condition following the completion of a
transaction. Subsequent transaction is a repeated start.
1’b0 – No action.
1’b1 – Next transaction uses a repeated start.
• reset
Reset. Resets I2C Controller IP. The registers and LMMI interface are not affected by this reset.
1’b0 – No action.
1’b1 – Resets I2C Controller IP.
• abort
Abort. Stops an I2C transaction in progress. After aborted process, INT_STATUS2_REG.abort_ack asserts.
1’b0 – No action.
1’b1 – Stops an I2C transaction in progress.
• start
Start. Starts an I2C transaction. This bit is written when all registers are programmed for the transaction.
1’b0 – No action.
1’b1 – Starts an I2C transaction.
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FPGA-IPUG-02071-1.9 21
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• bus_speed_mode
Bus Speed Mode. Specifies the bus speed mode. This information is used for generating the setup time for
repeated START condition (tSU;STA) and setup time for STOP condition (tSU;STO). The values below are estimated
based on System Clock Frequency attribute.
2’b00 – Standard mode: tSU;STA = tSU;STO ~= 4.7 µs
2’b01 – Fast mode: tSU;STA = tSU;STO ~ 1.3 µs
2’b10 – Fast mode Plus: tSU;STA = tSU;STO ~ 0.5 µs
• addr_mode
Address Mode. Selects the Addressing Mode.
1’b0 – 7-bit address mode
1’b1 – 10-bit address mode
• trx_mode
Transmit/Receive Mode. Sets the read or write operation on the I2C bus.
1’b0 – Write I2C transaction
1’b1 – Read I2C transaction
• clk_presc_high
Clock Prescaler High Register. The upper three bits of the Clock Prescaler High Register.
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• tr_cmp_int
Transfer Complete Interrupt Status. This interrupt status bit asserts when the number of bytes transferred in I2C
interface is equal to TGT_BYTE_CNT.byte_cnt.
1’b0 – No interrupt
1’b1 – Interrupt pending
• tx_fifo_full_int
Transmit FIFO Full Interrupt Status. This interrupt status bit asserts when Transmit FIFO changes from not full state
to full state.
1’b0 – No interrupt
1’b1 – Interrupt pending
• tx_fifo_aempty_int
Transmit FIFO Almost Empty Interrupt Status. This interrupt status bit asserts when the amount of data words in
Transmit FIFO changes from ‘TX FIFO Almost Empty Flag’ + 1 to ‘TX FIFO Almost Empty Flag’.
1’b0 – No interrupt
1’b1 – Interrupt pending
• tx_fifo_empty_int
Transmit FIFO Empty Interrupt Status. This interrupt status bit asserts when the last data in Transmit FIFO is
popped-out, causing the FIFO to become empty.
1’b0 – No interrupt
1’b1 – Interrupt pending
• rx_fifo_full_int
Receive FIFO Full Interrupt Status. This interrupt status bit asserts when RX FIFO full status changes from not full to
full state.
1’b0 – No interrupt
1’b1 – Interrupt pending
• rx_fifo_afull_int
Receive FIFO Almost Full Interrupt Status. This interrupt status bit asserts when the amount of data words in
Receive FIFO changes from ‘RX FIFO Almost Full Flag’ – 1 to ‘RX FIFO Almost Full Flag’.
1’b0 – No interrupt
1’b1 – Interrupt pending
• rx_fifo_ready_int
Receive FIFO Ready Interrupt Status. This interrupt status bit asserts when Receive FIFO is empty and receives a
data word from I2C interface.
1’b0 – No interrupt
1’b1 – Interrupt pending
Table 5.12. Interrupt Status Second Register
Field Name Access Width Reset
[7:4] reserved RSVD 4 —
[3] nack_error_int RW1C 1 1’b0
[2] abort_ack_int RW1C 1 1’b0
[1] arb_lost_int RW1C 1 1’b0
[0] timeout_int RW1C 1 1’b0
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FPGA-IPUG-02071-1.9 23
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• nack_error_int
NACK Error Interrupt Status. This interrupt status bit asserts when NACK is received, expecting an ACK during data
phase and address phase.
1’b0 – No interrupt
1’b1 – Interrupt pending
• abort_ack_int
Transaction Abort Acknowledgement Interrupt Status. This interrupt status bit asserts when an I2C Controller IP
aborts an ongoing transaction because you write 1’b1 to CONTROL_REG.abort. The interrupt asserts when NACK
has been issued.
1’b0 – No interrupt
1’b1 – Interrupt pending
• arb_lost_int
Arbitration Lost Interrupt Status. This interrupt status bit asserts when I2C Controller IP loses arbitration.
1’b0 – No interrupt
1’b1 – Interrupt pending
• timeout_int
SCL Timeout Interrupt Status. This interrupt status of bit asserts when scl_io is hold for
SCL_TIMEOUT_REG.timeout_val times the programmed SCL low period.
1’b0 – No interrupt
1’b1 – Interrupt pending
• tr_cmp_en
Transfer Complete Interrupt Enable. Interrupt enabled bit corresponded to Transfer Complete Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• tx_fifo_full_en
Transmit FIFO Full Interrupt Enable. Interrupt enabled bit corresponded to Transmit FIFO Full Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• tx_fifo_aempty_en
Transmit FIFO Almost Empty Interrupt Enable. Interrupt enabled bit corresponded to Transmit FIFO Almost Empty
Interrupt Status.
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0 – Interrupt disabled
1 – Interrupt enabled
• tx_fifo_empty_en
Transmit FIFO Empty Interrupt Enable. Interrupt enabled bit corresponded to Transmit FIFO Empty Interrupt
Status.
0 – Interrupt disabled
1 – Interrupt enabled
• rx_fifo_full_en
Receive FIFO Full Interrupt Enable. Interrupt enabled bit corresponded to Receive FIFO Full Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• rx_fifo_afull_en
Receive FIFO Almost Full Interrupt Enable. Interrupt enabled bit corresponded to Receive FIFO Almost Full
Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• rx_fifo_ready_en
Receive FIFO Ready Interrupt Enable. Interrupt enabled bit corresponded to Receive FIFO Ready Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
Table 5.14. Interrupt Enable Second Register
Field Name Access Width Reset
[7:4] reserved RSVD 4 —
[3] nack_error_en RW 1 1’b0
[2] abort_ack_en RW 1 1’b0
[1] arb_lost_en RW 1 1’b0
[0] timeout_en RW 1 1’b0
• nack_error_en
NACK Error Interrupt Enable. Interrupt enabled bit corresponded to NACK Error Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• abort_ack_en
Transaction Abort Acknowledgement Interrupt Enable. Interrupt enabled bit corresponded to Transaction Abort
Acknowledgement Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• arb_lost_en
Arbitration Lost Interrupt Enable. Interrupt enabled bit corresponded to Arbitration Lost Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• timeout_en
SCL Timeout Interrupt Enable. Interrupt enabled bit corresponded to SCL Timeout Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
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• tr_cmp_set
Transfer Complete Interrupt Set. Interrupt set bit corresponded to Transfer Complete Interrupt Status.
1’b0 – No action
1’b1 – Asserts INT_STATUS1_REG.tr_cmp_int
• tx_fifo_full_set
Transmit FIFO Full Interrupt Set. Interrupt set bit corresponded to Transmit FIFO Full Interrupt Status.
1’b0 – No action
1’b1 – Asserts INT_STATUS1_REG.tx_fifo_full_int
• tx_fifo_aempty_set
Transmit FIFO Almost Empty Interrupt Set. Interrupt set bit corresponded to Transmit FIFO Almost Empty Interrupt
Status.
1’b0 – No action
1’b1 – Asserts INT_STATUS1_REG.tx_fifo_aempty_int
• tx_fifo_empty_set
Transmit FIFO Empty Interrupt Set. Interrupt set bit corresponded to Transmit FIFO Empty Interrupt Status.
1’b0 – No action
1’b1 – Asserts INT_STATUS1_REG.tx_fifo_empty_int
• rx_fifo_full_set
Receive FIFO Full Interrupt Set. Interrupt set bit corresponded to Receive FIFO Full Interrupt Status.
1’b0 – No action
1’b1 – Asserts INT_STATUS1_REG.rx_fifo_full_int
• rx_fifo_afull_set
Receive FIFO Almost Full Interrupt Set. Interrupt set bit corresponded to Receive FIFO Almost Full Interrupt Status.
1’b0 – No action
1’b1 – Asserts INT_STATUS1_REG.rx_fifo_afull_int
• rx_fifo_ready_set
Receive FIFO Ready Interrupt Set. Interrupt set bit corresponded to Receive FIFO Ready Interrupt Status.
1’b0 – No action
1’b1 – Asserts INT_STATUS1_REG.rx_fifo_ready_int
Table 5.16. Interrupt Set Second Register
Field Name Access Width Reset
[7:4] reserved RSVD 4 —
[3] nack_error_set WO 1 1’b0
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• nack_error_set
NACK Error Interrupt Set. Interrupt set bit corresponded to NACK Error Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• abort_ack_set
Transaction Abort Acknowledgement Interrupt Set. Interrupt set bit corresponded to Transaction Abort
Acknowledgement Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• arb_lost_set
Arbitration Lost Interrupt Set. Interrupt set bit corresponded to Arbitration Lost Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• timeout_set
SCL Timeout Interrupt Set. Interrupt set bit corresponded to SCL Timeout Interrupt Status.
0 – Interrupt disabled
1 – Interrupt enabled
• tx_fifo_full
Transmit FIFO Full. This bit reflects the full condition of Transmit FIFO.
1’b0 – Transmit FIFO is not full
1’b1 – Transmit FIFO is full
• tx_fifo_aempty
Transmit FIFO Almost Empty. This bit reflects the almost empty condition of Transmit FIFO.
1’b0 – Data words in Transmit FIFO is greater than ‘TX FIFO Almost Empty Flag’ attribute
1’b1 – Data words in Transmit FIFO is less than or equal to ‘TX FIFO Almost Empty Flag’ attribute
• tx_fifo_empty
Transmit FIFO Empty. This bit reflects the empty condition of Transmit FIFO.
1’b0 – Transmit FIFO is not empty – has at least 1 data word
1’b1 – Transmit FIFO is empty
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• rx_fifo_full
Receive FIFO Full. This bit reflects the full condition of Receive FIFO.
1’b0 – Receive FIFO is not full
1’b1 – Receive FIFO is full
• rx_fifo_afull
Receive FIFO Full. This bit reflects the almost full condition of Receive FIFO.
1’b0 – Data words in Receive FIFO is less than ‘RX FIFO Almost Full Flag’ attribute
1’b1 – Data words in Receive FIFO is greater than or equal to ‘RX FIFO Almost Full Flag’ attribute
• rx_fifo_empty
Receive FIFO Full. This bit reflects the empty condition of Receive FIFO.
1’b0 – Receive FIFO is not empty – has at least 1 data word
1’b1 – Receive FIFO is empty
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FPGA-IPUG-02071-1.9 28
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6. Example Design
The I2C Controller example design allows you to compile, simulate, and test the I2C Controller IP on the following
Lattice evaluation boards:
• CertusPro-NX Evaluation Board
• MachXO5-NX Development Board
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An Embedded C/C++ Project is also created in the Propel software to enable developing and debugging application
code for different IP features. I2C Controller features can be tested by sending I2C Commands from the I2C Controller
to the I2C Target. Runtime configuration of IP and feature testing can be done through C-Code Test Routine. Figure 6.2
shows an example routine to send write data from I2C Controller. This sample test routine can be found in the driver
file included in the generated IP.
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FPGA-IPUG-02071-1.9 30
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User Guide
FPGA
SDA SCL
AHB-Lite-to-APB Bridge
RISC-V CPU
I2C Analyzer/
Exerciser
System
I2C Target
Memory
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User Guide
4. Run Propel Builder by clicking the icon or navigate to LatticeTools > Open Design in Propel Builder. The Propel
Builder will open and load the design template.
5. In the IP Catalog tab, instantiate the I2C Controller IP. Refer to the Generating and Instantiating the IP section for
more details. In this example, there is one instance of the I2C Controller IP:
See the Example Design Supported Configuration section for the corresponding parameter settings.
6. After generating the IP, the Define Instance window will open. Modify the instance name if needed, then click OK.
7. Connect the instantiated IPs to the system. Refer to Figure 6.1 for the connections used in this IP. You will need to
update other components of the system for clock and reset sources, interrupt, and bus interface.
8. Click the icon or navigate to Design > Run Radiant to launch the Lattice Radiant Software.
9. Update your constraints file accordingly and generate the programming file.
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10. In the Lattice Propel software, build your SoC project to generate the system environment needed for the
embedded C/C++ project. Select your SoC project then navigate to Project > Build Project.
11. Check the build result from the Console view.
12. Generate a new Lattice C/C++ project by navigating to File > New > Lattice C/C++ Project. Update your Project
name, click Next, and then click Finish.
13. Select your C/C++ project then select Project > Build.
14. Check the build result from the Console view.
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15. This environment is now ready for running your tests on the device. Refer to the Running Demo on MachXO3D
Breakout Board – Hello World section of the Lattice Propel SDK User Guide for step-by-step guide.
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User Guide
3. In the module dialog box of the Module/IP Block Wizard window, customize the selected I2C Controller IP using
drop-down menus and check boxes. As a sample configuration, see Figure 7.2. For configuration options, see the
IP Parameter Description section.
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4. Click Generate. The Check Generating Result dialog box opens, showing design block messages and results as
shown in Figure 7.3.
5. Click the Finish button. All the generated files are placed under the directory paths in the Create in and the
Component name fields shown in Figure 7.1.
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<IP_Instance_Path>/<IP_Instance_Name>/constraints/<IP_Instance_Name>.ldc
The constraint file has been verified during IP evaluation with the IP instantiated directly in the top-level module. You
can modify the constraints in this file with thorough understanding of the effect of each constraint.
To use this constraint file:
1. Copy the contents of <IP_Instance_Name>.ldc to the top-level design constraint for post-synthesis.
2. Remove create_clock constraints if the I2C Controller is instantiated in another module.
3. Remove ldc_set_port for scl_io and sda_io if REMOVE_TRISTATE buffer is enabled.
Refer to Lattice Radiant Timing Constraints Methodology (FPGA-AN-02059) for details on how to constraint your
design.
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1. Click the button located on the Toolbar to initiate the Simulation Wizard shown in Figure 7.4.
2. Click Next to open the Add and Reorder Source window as shown in Figure 7.5.
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3. Click Next. The Summary window is shown. Click Finish to run the simulation.
Note: It is necessary to follow the procedure above until it is fully automated in the Lattice Radiant software suite.
The results of the simulation in our example are provided in Figure 7.6.
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Table A.2 shows configuration and resource utilization for the LAV-AT-E70-1LFG1156I device using Synplify Pro of the
Lattice Radiant Software 2022.1.
Table A.2. LAV-AT-E70-1LFG1156I Device Resource Utilization
Configuration Clk Fmax (MHz)* Slice Registers LUTs EBRs
Default 115.168 508 587 0
APB Mode Enable is Unchecked, Others = Default 249.813 491 576 0
Implementation of FIFO = EBR, Others = Default 116.239 492 559 2
FIFO Depth = 256, RX FIFO Almost Full Flag = 254, Others =
99.780 620 1164 0
Default
FIFO Depth = 256, RX FIFO Almost Full Flag = 254,
97.809 604 651 2
Implementation of FIFO = EBR, Others = Default
*Note: Fmax is generated when the FPGA design only contains I2C Controller IP and the target Frequency is 50 MHz. These values
Table A.3 shows configuration and resource utilization for the LN2-CT-20-1CBG484C device using Synplify Pro of the
Lattice Radiant Software 2024.2.
Table A.3. LN2-CT-20-1CBG484C Device Resource Utilization
Configuration Clk Fmax (MHz)* Slice Registers LUTs EBRs
Default 115.741 487 588 0
APB Mode Enable is Unchecked, Others = Default 250.000 483 587 0
Implementation of FIFO = EBR, Others = Default 124.626 471 494 2
FIFO Depth = 256, RX FIFO Almost Full Flag = 254, Others =
117.082 599 1165 0
Default
FIFO Depth = 256, RX FIFO Almost Full Flag = 254,
130.056 583 654 2
Implementation of FIFO = EBR, Others = Default
*Note: Fmax is generated when the FPGA design only contains I2C Controller IP and the target Frequency is 50 MHz. These values
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User Guide
References
For more information, refer to:
• Lattice Memory Mapped Interface and Lattice Interrupt Interface (FPGA-UG-02039)
• AMBA 3 APB Protocol v1.0 Specification
• I2C Bus Specification and User Manual
• Lattice Radiant Software 2023.1 User Guide
• Lattice Radiant Timing Constraints Methodology (FPGA-AN-02059)
• Reveal User Guide for Radiant Software
• I2C Controller IP Release Notes (FPGA-RN-02027)
• Lattice Radiant Software web page
• Lattice Solutions IP Cores web page
• Avant-E web page
• Avant-G web page
• Avant-X web page
• Certus-N2 web page
• Certus-NX web page
• CertusPro-NX web page
• CrossLink-NX web page
• CertusPro-NX Evaluation Board
• MachXO5-NX Development Board web page
• Lattice Insights web page for Lattice Semiconductor training courses and learning plans
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Revision History
Revision 1.9, IP v2.2.0, December 2024
Section Change Summary
All • Added the IP version information on the cover page.
• Updated I2C to I2C.
• Removed the Debugging section.
• Made editorial fixes.
Acronyms in This Document • Added Design Under Test (DUT), Embedded Block RAM (EBR), First In, First Out (FIFO),
General Purpose Input/Output (GPIO), Input/Output (I/O), Intellectual Property (IP),
Lattice Synthesis Engine (LSE), Look-Up Table (LUT), Programmable Interrupt Controller
(PIC), Phase-Locked Loop (PLL), Random Access Memory (RAM), Receiver (RX), Reduced
Instruction Set Computer Five (RISC-V), Serial Clock (SCL), Static Random Access Memory
(SRAM), System on Chip (SoC), Serial Data (SDA), Transmitter (TX), and Universal
Asynchronous Receiver/Transmitter (UART).
Introduction • Updated Table 1.1. Summary of the I2C Controller IP:
• Added the Certus-N2 device family to Supported FPGA Family.
• Removed IP Version and added IP Changes.
• Added the LFD2NX-9, LFD2NX-28, LFCPNX-50, LFMXO5-55T, LFMXO5-100T,
LAV-AT-G70, LAV-AT-X70, and LN2-CT-20 devices to Targeted Devices.
• Updated Resources and Lattice Implementation.
• Updated the Licensing Information and Minimum Device Requirements sections.
• Replaced the IP Validation Summary section with the IP Support Summary section.
• Removed the 1.7.3. Host and 1.7.4. Attribute sections.
Functional Description • Removed ack_mode from step 1 in the Write to a Target Device, Read from a Target
Device, and Read from a Target Device with a Specific Register or Command (Repeated
Start) sections.
• Updated the scl_io description in the Clock Generation and Synchronization section.
• Added (interrupts are disabled) to the following:
• Steps 6 and 10 in the Write to a Target Device section
• Steps 5 and 9 in the Read from a Target Device section
• Steps 6, 10, 16, and 20 in the Read from a Target Device with a Specific Register or
Command (Repeated Start) section.
• Replaced Target Register with Specific Register in the Read from a Target Device with a
Specific Register or Command (Repeated Start) section header.
IP Parameter Description In Table 3.1. Attributes Table, updated the Selectable Values field for the TX FIFO Almost
Empty Flag and RX FIFO Almost Full Flag attributes.
Example Design Added this section.
Designing with the IP • Updated the paragraph in the Designing with the IP section.
• Updated Figure 7.1. Module/IP Block Wizard, Figure 7.2. Configure User Interface of I2C
Controller IP, and Figure 7.3. Check Generating Result.
Resource Utilization Added resource utilizations for the Lattice Radiant software version 2024.2.
References Added the Lattice Solutions IP Cores web page, Avant-G web page, Avant-X web page,
Certus-N2 web page, CertusPro-NX Evaluation Board web page, MachXO5-NX Development
Board web page, and I2C Controller IP Release Notes (FPGA-RN-02027).
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