SPI

Serial Peripheral Interface

The AVR microcontroller

and embedded
systems
using assembly and c

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 SPI …
◼ Started by Motorola Corp. (now Freescale)
◼ Uses 2 pins for data (SDI and SDO ) one for clock (SCLK) and chip
enable (CE)
◼ The pins are alternatively named MISO (Master In Slave out) , MOSI
(Master Out Slave In) , SS (Slave Select) and SCK
◼ Read and Write happens at the same time

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 SPI …
Master Slave
MISO MISO
MOSI MOSI
SCK SCK
OUT1 SS
OUT2

Slave
MISO
MOSI
SCK
SS

AVR Microcont roller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 SPI pins in Atmega32

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 SPI BUS PROTOCOL
➢ SPI was developed to provide a low-cost and simple interface between
microcontrollers and peripheral chips.
➢ SPI devices use only 2 pins for data transfer, SDI (Din) & SDO (Dout), instead of 8
or more pins used in traditional buses.
➢ This reduces package size and power consumption.
➢ SPI bus has the SCLK (clock) pin to synchronize the data transfer between two
chips, CE (chip enable) used to initiate and terminate the data transfer.
➢ Four pins, SDI, SDO, SCLK, and CE, make the SPI a 4-wire interface.
➢ SDI, SDO, SCLK, and CE signals are alternatively named as MOSI, MISO, SCK, and
SS.
➢ There is also a standard called 3-wire interface bus where SCLK, CE, and only a
single pin for data transfer.
➢ SPI 4-wire bus can become 3-wire interface when the SDI and SDO data pins are
tied together.
➢ There are some major differences between the SPI and 3-wire devices in the data
transfer protocol. For that reason, a device must support the 3-wire protocol
internally in order to be used as a 3-wire device.
SPI Bus vs. Traditional Parallel Bus Connection
 SPI Interface
• Also known as a four-wire interface.
• Used to interface to memory (for data storage), ADC, DAC, real-time
clock calendars, LCD drivers, sensors, audio chips, and even other
processors.
• Unlike a standard serial port, SPI is a synchronous protocol in which all
transmissions are referenced to a common clock, generated by the
master (processor).
• The receiving peripheral (slave) uses the clock to synchronize its
acquisition of the serial bit stream.
Basic SPI Interface
• SPI uses four main signals:
• Master Out Slave In (MOSI)
• Master In Slave Out (MISO)
• Serial CLocK (SCLK or SCK)
• Chip Select (CS)
SPI Transmission
• Both masters and slaves contain a serial shift register.
• The master starts a transfer of a byte by writing it to its SPI shift
register.
• As the register transmits the byte to the slave on the MOSI signal
line, the slave transfers the contents of its shift register back to the
master on the MISO signal line.
• In this way, the contents of the two shift registers are exchanged.
• Both a write and a read operation are performed with the slave
simultaneously.
 SPSR (SPI Status Register)

◼ SPIF (SPI interrupt Flag)

◼ Transmitted/Received
◼ Switched to Slave mode
◼ WCOL (Write COLision Flag)
◼ SPI2X (Double SPI Speed bit)
◼ 1: Double

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 SPCR (SPI Control Register)

◼ SPIE (SPI Interrupt Enable)

◼ SPE (SPI Enable)
◼ DORD (Data Order): 1:Send LSB 1st, 0:Send MSB 1st
◼ MSTR (Master/Slave Select): 1:Master, 0: Slave
◼ CPOL (Clock Polarity): 1: idle SCK = 1, 0: SCK = 0
◼ CPHA (Clock Phase):
◼ SPR1 (SPI Clock Rate Select 1)
◼ SPR0 (SPI Clock Rate Select 0)

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
SPI Timing
➢ SPI has four modes of operation, depending on clock
polarity and clock phase.
➢ For low (0) clock polarity, the clock (SCK) is low when
idle and toggles high during a transfer and vice versa.
➢ The two clock phases are known as clock phase zero
and clock phase one.
➢ For clock phase zero, MOSI and MISO outputs are valid
on the rising edge of the clock (SCK) if the clock polarity
is low and vice versa.
 SPCR (SPI Control Register)

◼ SPIE (SPI Interrupt Enable)

◼ SPE (SPI Enable)
◼ DORD (Data Order): 1:Send LSB 1st, 0:Send MSB 1st
◼ MSTR (Master/Slave Select): 1:Master, 0: Slave
◼ CPOL (Clock Polarity): 1: idle SCK = 1, 0: SCK = 0
◼ CPHA (Clock Phase):
◼ SPR1 (SPI Clock Rate Select 1)
◼ SPR0 (SPI Clock Rate Select 0)
AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
Steps for writing data to an SPI device
Single-byte write
The following steps are used to write data in single-byte mode for SPI devices:
1. Make CE = 0 to begin writing.
2. The 8-bit address is shifted in, one bit at a time, with each edge of SCLK.
Notice that A7 = 1 for the write operation, and the A7 bit goes in first.
3. After all 8 bits of the address are sent in, the SPI device expects to receive
the data belonging to that address location immediately.
4. The 8-bit data is shifted in one bit at a time, with each edge of the SCLK.
5. Make CE = 1 to indicate the end of the write cycle.

What about Single-byte read!!

Multibyte burst write
1. Make CE = 0 to begin writing.
2. The 8-bit address of the first location is provided and shifted in, one bit at
a time, with each edge of SCLK. Notice that A7 = 1 for the write operation
and the A7 bit goes in first.
3. The 8-bit data for the first location is provided and shifted in, one bit at a
time, with each edge of the SCLK. From then on, we simply provide consecutive
bytes of data to be placed in consecutive memory locations. In the
process, CE must stay low to indicate that this is a burst mode multibyte
write operation.
4. Make CE = 1 to end writing.

What about Multibyte burst read!!

 SPCR (SPI Control Register)

◼ SPIE (SPI Interrupt Enable)

◼ SPE (SPI Enable)
◼ DORD (Data Order): 1:Send LSB 1st, 0:Send MSB 1st
◼ MSTR (Master/Slave Select): 1:Master, 0: Slave
◼ CPOL (Clock Polarity): 1: idle SCK = 1, 0: SCK = 0
◼ CPHA (Clock Phase):
◼ SPR1 (SPI Clock Rate Select 1)
◼ SPR0 (SPI Clock Rate Select 0)
AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 SS Pin
◼ Master Mode
◼ You can set the direction to output and SPI will not
control the pin
◼ If you set the direction to input, It should be
externally pulled up
◼ if you make it externally low, the SPI module stops working
in master mode and switches to slave mode by clearing the
MSTR bit in SPCR, and then sets the SPIF bit in SPSR.
◼ Slave Mode
◼ SS pin is always input and you can not control it by
software.
◼ You should hold it externally low to activate the SPI.
◼ When SS is driven high, SPI is disabled and all pins of
SPI are input. Also the SPI module will immediately
clear any partially received data in the shift register
BUT IT WILL NOT BE DISABLED
AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 Master Operating Mode
◼ Set the MSTR bit to one
◼ Set SCK frequency by setting the values of SPI2X,
SPR1, and SPR2
◼ Set the SPI mode. If not set, it is 0.
◼ Enable SPI by setting the SPIE bit to one
◼ Write a byte to the SPI Data Register (SPDR)
◼ Poll the SPIF flag. Data transfer is finished when it
changes to one.
◼ read the received byte from SPDR before the next byte
arrives.
◼ Note: After the transmission, the byte in the Master shift
register is moved to the Slave Shift register and the Byte in the
Slave shift register is moved to the Master shift register. It
means that send and received happens at the same time. If
you only want to read a byte, you should transmit a dummy
byte like 0xff and then read the received data!

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 Slave Operating Mode

◼ Set the SPI mode. If not set, it is 0.

◼ Enable SPI by setting the SPIE bit to one
◼ Write a byte to the SPI Data Register (SPDR)
◼ Poll the SPIF flag. Data transfer is finished when
it changes to one.
◼ read the received byte from SPDR.

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 SPI Application: SPI-Based Clock/Calendar
What is Calendar Integration?
Allows two different applications to sync together and share data from your
calendar, avoiding duplicate calendar entries or overlapping appointments.
Calendar integration is a two-way process; when you book appointments in
either application, that data is automatically synced so that both applications
stay current in real time.
Every electronic device is now integrated with the electronic calendar to
enable the user to keep time and date anywhere at any time.

• A clock/calendar chips contain an oscillator

module driven by a crystal, just like a processor.
• The oscillator module ticks over internal
counters that track milliseconds, seconds,
minutes, hours, days, months, and years.
• They are specifically designed to provide
accurate timekeeping, and many have additional
functions such as an "alarm" and a watchdog.
 What is 7-Segment
◼ 7-Segments are made of 7 LEDs to show
different numbers plus another LED to display
the decimal point.
◼ There are two types of 7-segments, common
anode and common cathode. (below figure)

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 MAX 7921 (SPI 7-Seg Driver)

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
 MAX 7921 Connections to AVR
◼ Up to 8 7-Segs can be connected to MAX7921
◼ The ISET resistor control the intensity of light
◼ The VCC and GND must be able to handle up to
300 mA

AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.