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HDL Report 2++

The document contains HDL code for various digital circuits including a module for addition and subtraction with overflow detection, a 2x1 multiplexer with an enable switch, and modules for converting binary to BCD and Gray code. It also includes an ALU with a 4-bit select input that performs various operations such as AND, OR, XOR, addition, and subtraction. Each module is defined with input and output specifications, and the behavior is described using always blocks and case statements.

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Mohamed Ahmed
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9 views4 pages

HDL Report 2++

The document contains HDL code for various digital circuits including a module for addition and subtraction with overflow detection, a 2x1 multiplexer with an enable switch, and modules for converting binary to BCD and Gray code. It also includes an ALU with a 4-bit select input that performs various operations such as AND, OR, XOR, addition, and subtraction. Each module is defined with input and output specifications, and the behavior is described using always blocks and case statements.

Uploaded by

Mohamed Ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Mohamed Ahmed Hammouda

HDL report 2
1-Ex 4.40
module ex4_40 (

output [3 : 0] Sum_diff ,

output V , // overflow

input [3:0] A , B ,

input M

);

always@ (M , A , B)

assign { V , Sum_diff } = M ? A-B : A+B ;

endmodule

2- Ex 4.43

We can consider the code above as a description for a 2x1 multiplexer circuit
with enable switch.

When the enable switch is off the output is in high impedance state
(open circuit).

While when the enable switch is on the input S selects which of the inputs A
or B to be the output of the multiplexer as explained in the diagram shown.
3-Ex 4.50
module ex4_50_a (

input [3:0] B_84_2_1 , // 8,4,-2,-1 number

output reg [3:0] BCD // BCD number

);

always @ ( B_84_2_1 , BCD )

case (B_84_2_1)

4’b0000 : BCD = 4’b0000 ; // decimal 0

4’b0111 : BCD = 4’b0001 ; // d1

4’b0110 : BCD = 4’b0010 ; // d2

4’b0101 : BCD = 4’b0011 ; //d 3

4’b0100 : BCD = 4’b0100 ; //d 4

4’b1011 : BCD = 4’b0101 ; // d5

4’b1010 : BCD = 4’b0110 ; //d 6

4’b1001 : BCD = 4’b0111 ; // d7

4’b1000 : BCD = 4’b1000 ; // d8

4’b1111 : BCD = 4’b1001 ; // d9

// cases from 10 to 15 shouldn’t be used

4’b0001 : BCD = 4’b1010 ; // d10

4’b0010 : BCD = 4’b1011 ; // d11

4’b0011 : BCD = 4’b1100 ; // d12

4’b1100 : BCD = 4’b1101 ; // d13

4’b1101 : BCD = 4’b1110 ; // d14

4’b1110 : BCD = 4’b1111 ; // d15

endcase

endmodule
module ex4_50_b (

input [3:0] B_84_2_1 , // 8,4,-2,-1 number

output reg [3:0] Gray // Gray code number

);

always @ ( B_84_2_1 , Gray )

case (B_84_2_1)

4’b0000 : Gray = 4’b0000 ; // decimal 0

4’b0111 : Gray = 4’b0001 ; //d1

4’b0110 : Gray = 4’b 0011 ; //d2

4’b0101 : Gray = 4’b0010 ; //d3

4’b0100 : Gray = 4’b0110 ; //d4

4’b1011 : Gray = 4’b0111 ; //d5

4’b1010 : Gray = 4’b0101 ; //d6

4’b1001 : Gray = 4’b0100 ; //d7

4’b1000 : Gray = 4’b1100 ; //d8

4’b1111 : Gray = 4’b1101 ; //d9

// cases from 10 to 15 shouldn’t be used

4’b0001 : Gray = 4’b1111 ; // d10

4’b0010 : Gray = 4’b1110 ; // d11

4’b0011 : Gray = 4’b1010 ; // d12

4’b1100 : Gray = 4’b1011 ; // d13

4’b1101 : Gray = 4’b1001 ; // d14

4’b1110 : Gray = 4b1000 ’; // d15

endcase

endmodule
4-ALU with 4 bit select

module ALU_with_4_bit_select(

output reg [7:0] y ,

input [7:0] A , B ,

input [3:0] Select

);

always @ (A , B , Select) begin

y=0 ;

case (Select)

4’b0000 : y = 8’b0 ; // all zeros

4’b00001 : y= A&B ; // AND

4’b0010 : y= A|B ; // OR

4’b0011 : y= A^B ; // XOR

4’b0100 : y= A+B ; // binary addition

4’b0101 : y=A-B ; // binary subtraction

4’b0110 : y= ~A ; // complement

4’b0111 : y= A ;

4’b1000 : y=B ;

4’b1001 : y=~B ; // complement

4’b1010 : y=B-A ; // binary subtraction

4’b1011 : y= ~(A+B) ; // binary addition complement

4’b1100 : y=~(A^B) ; // XNOR

4’b1101 : y=~(A|B) ; // NOR

4’b1110 : y=~(A&B) ; // NAND

4’b1111 : y = 8’hFF ; // all ones

endcase

end // begin

endmodule

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