GUJARAT TECHNOLOGICAL UNIVERSITY

Affiliated
S. N. PATEL INSTITUTE OF TECHNOLOGY &
RESEARCH CENTRE, UMRAKH
QUESTION BANK SOLUTION

Subject Name : Computer Organization & Architecture

Subject Code : 3140707
Branch : Computer Science & Engineering/Information Technology
Semester : 4th
Subject Teacher : Ms. Arpita Patel, MS. Priyanka Chaudhari
Q.1. Draw and explain working of 4 bit binary adder & 4 - bit Arithmetic Logic Shift Unit.
Ans: 4 Bit Binary adder:
● The digital circuit that generates the arithmetic sum of two binary numbers of any lengths is called
a binary adder.
● The binary adder is constructed with full-adder circuits connected in cascade, with the output carry
from one full-adder connected to the input carry of the next full-adder.

● Above figure 1.7 shows the interconnections of four full-adders (FA) to provide a 4-bit binary
adder.
● The augends bits of A and the addend bits of B are designated by subscript numbers from right
to left, with subscript 0 denoting the low-order bit.
● The carries are connected in a chain through the full-adders.
● The input carry to the binary adder is C0 and the output carry is C4.
● The S outputs of the full-adders generate the required sum bits.
● An n-bit binary adder requires n full-adders.
● The output carry from each full-adder is connected to the input carry of the next-high- order full-
adder.
● The n data bits for the A inputs come from one register (such as R1), and the n data bits for the
B inputs come from another register (such as R2). The sum can be transferred to a third register
or to one of the source registers (R1 or R2), replacing its previous content.

● 4- bit Arithmetic Logic Shift :

● To perform a micro operation, the contents of specified registers are placed in the inputs of the
common ALU.The ALU performs an operation and the result of the operation is then transferred
to a destination register.
● The ALU is a combinational circuit so that the entire register transfer operation from the source
registers through the ALU and into the destination register can be performed during one dock
 pulse period.
● The arithmetic, logic, and shift circuits introduced in previous sections can be combined into one
ALU with common selection variables.
● One stage of an arithmetic logic shift unit is shown in figure below:

● The subscript i designates a typical stage. Inputs Ai and Bi are applied to both the arithmetic and
logic units.A particular micro operation is selected with inputs S1 and S0.
● A 4 x 1 multiplexer at the output chooses between an arithmetic output in Di and a logic output
in Ei .The data in the multiplexer are selected with inputs S3 and S2.
● The other two data inputs to the multiplexer receive inputs Ai-1 for the shift-right operation and
Ai+1 for the shift-left operation.
● Note that the diagram shows just one typical stage. The circuit shown in figure must be repeated
n times for an n-bit ALU.
● The outputs carry Ci+1 of a given arithmetic stage must be connected to the input carry Cin of the
next stage in sequence.
● The input carry to the first stage is the input carry On, which provides a selection variable for the
arithmetic operations.
● The circuit whose one stage is specified in figure provides
▪ 8 arithmetic operation
▪ 4 logic operations
▪ 2 shift operations

● Table below lists the 14 operations of the ALU.

Q.2 Construct diagram of common bus system of four 4-bits registers with diagram. (Using Multiplexer
and Using tri-state Buffer).
Ans. • The basic computer has eight registers, a memory unit and a control unit.Paths must be provided to
transfer information from one register to another and between memory and register.
• The number of wires will be excessive if connections are between the outputs of each register and
the inputs of the other registers. An efficient scheme for transferring information in a system with
many register is to use a common bus.
• The connection of the registers and memory of the basic computer to a common bus system is shown
in figure 2.5.
• The outputs of seven registers and memory are connected to the common bus. The specific output
that is selected for the bus lines at any given time is determined from the binary value of the selection
variables S2, S1, and S0.
• The number along each output shows the decimal equivalent of the required binary selection.
• The particular register whose LD (load) input is enabled receives the data from the bus during the
next clock pulse transition. The memory receives the contents of the bus when its write input is
activated. The memory places its 16-bit output onto the bus when the read input is activated and S2
S1 S0 = 1 1 1.
• Four registers, DR, AC, IR, and TR have 16 bits each. Two registers, AR and PC, have 12 bits each
since they hold a memory address.
• When the contents of AR or PC are applied to the 16-bit common bus, the four most significant bits
are set to 0’s. When AR and PC receive information from the bus, only the 12 least significant bits
are transferred into the register.
• The input register INPR and the output register OUTR have 8 bits each and communicate with the
eight least significant bits in the bus. INPR is connected to provide information to the bus but OUTR
can only receive information from the bus.
 • Five registers have three control inputs: LD (load), INR (increment), and CLR (clear). Two
registers have only a LD input.
• AR must always be used to specify a memory address; therefore memory address is connected to
AR.
• The 16 inputs of AC come from an adder and logic circuit. This circuit has three sets of inputs.
o Set of 16-bit inputs come from the outputs of AC.
o Set of 16-bits come from the data register DR.
o Set of 8-bit inputs come from the input register INPR.
• The result of an addition is transferred to AC and the end carry-out of the addition is transferred
to flip-flop E (extended AC bit).
• The clock transition at the end of the cycle transfers the content of the bus into the designated
destination register and the output of the adder and logic circuit into AC.

Q.3 Explain 4 bit arithmetic circuit with suitable diagram.

Ans. • The arithmetic micro operations can be implemented in one composite arithmetic circuit.
• The basic component of an arithmetic circuit is the parallel adder.
• By controlling the data inputs to the adder, it is possible to obtain different types of arithmetic
operations.
• Hardware implementation consists of:
• 4 full-adder circuits that constitute the 4-bit adder and four multiplexers for choosing different
operations.
• There are two 4-bit inputs A and B
The four inputs from A go directly to the X inputs of the binary adder. Each
of the four inputs from B is connected to the data inputs of the multiplexers.
The multiplexer’s data inputs also receive the complement of B.
• The other two data inputs are connected to logic-0 and logic-1. Logic-0 is a fixed voltage value
(0 volts for TTL integrated circuits) and the logic-1 signal can be generated through an inverter
whose input is 0.
• The four multiplexers are controlled by two selection inputs, S1 and S0.
• The input carry Cin goes to the carry input of the FA in the least significant position. The other
carries are connected from one stage to the next.
• 4-bit output D0…D3

• The output of binary adder is calculated from arithmetic sum.

D=A+Y+Cin

• When S1 S0= 0 0
If Cin=0, D=A+B; Add
If Cin=1, D=A+B+1;Add with carry
• When S1 S0= 0 1
̅
If Cin=0, D=A+B; Subtract with borrow
̅
If Cin=1, D=A+B+1;A+2’s compliment of B i.e. A-B
• When S1 S0= 1 0
Input B is neglected and Y=> logic ‘0’
D=A+0+ Cin
If Cin=0, D=A; Transfer A If
Cin=1, D=A+1;Increment A
 • When S1 S0= 1 1
Input B is neglected and Y=> logic ‘1’
D=A-1+ Cin
If Cin=0, D=A-1; 2’s compliment If
Cin=1, D=A; Transfer A
• Note that the micro-operation D = A is generated twice, so there are only seven distinct micro-
operations in the arithmetic circuit.
Q.4
Ans. Enlist register reference instructions and explain any one of them in detail. And Explain any four
Input output reference instruction.

Register reference instructions:

• When the register-reference instruction is decoded, D7 bit is set to 1.
• Each control function needs the Boolean relation D7 I' T3

15 12 11 0
0 1 1 1 Register Operation

• These 12 bits are available in IR (0-11). They were also transferred to AR during time T2.These
instructions are executed at timing cycle T3.
• The first seven register-reference instructions perform clear, complement, circular shift, and
increment micro operations on the AC or E registers.
• The next four instructions cause a skip of the next instruction in sequence when condition is satisfied.
The skipping of the instruction is achieved by incrementing PC.
• The condition control statements must be recognized as part of the control conditions. The AC is
positive when the sign bit in AC(15) = 0; it is negative when AC(15) = 1. The content of AC is zero
(AC = 0) if all the flip-flops of the register are zero.
• The HLT instruction clears a start-stop flip-flop S and stops the sequence counter from counting. To
restore the operation of the computer, the start-stop flip-flop must be set manually.
 Input-Output reference instructions:
• Input and output instructions are needed for transferring information to and from AC register, for
checking the flag bits, and for controlling the interrupt facility.
• Input-output instructions have an operation code 1111 and are recognized by the control when D7
= 1 and I = 1.
• The remaining bits of the instruction specify the particular operation.
• The control functions and micro operations for the input-output instructions are listed below.

• The INP instruction transfers the input information from INPR into the eight low-order bits of
AC and also clears the input flag to 0.
• The OUT instruction transfers the eight least significant bits of AC into the output register OUTR
and clears the output flag to 0.
o The next two instructions in Table 2.2 check the status of the flags and cause a skip of the
next instruction if the flag is 1.
o The instruction that is skipped will normally be a branch instruction to return and check
the flag again.
o The branch instruction is not skipped if the flag is 0. If the flag is 1, the branch instruction
is skipped and an input or output instruction is executed.
• The last two instructions set and clear an interrupt enable flip-flop IEN. The purpose of IEN is
explained in conjunction with the interrupt operation

Explain Memory reference instructions in detail and Explain register transfer using block
Q.5 diagram and timing diagram.
• When the memory-reference instruction is decoded, D7 bit is set to 0.
Ans.

• The effective address of the instruction is in the address register AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1.
• The execution of the memory-reference instructions starts with timing signal T4.
 AND to AC
• This is an instruction that performs the AND logic operation on pairs of bits in AC and the memory
word specified by the effective address. The result of the operation is transferred to AC.
D0T4: DR←M[AR]
D0T5: AC ← AC 𝖠 DR, SC ← 0

ADD to AC
• This instruction adds the content of the memory word specified by the effective address to the value
of AC. The sum is transferred into AC and the output carry Cout is transferred to the E (extended
accumulator) flip-flop.

ISZ: Increment and Skip if Zero

 • These instruction increments the word specified by the effective address, and if the incremented
value is equal to 0, PC is incremented by 1. Since it is not possible to increment a word inside the
memory, it is necessary to read the word into DR, increment DR, and store the word back into
memory.

Register transfer:
• Registers define the storage area that influences the data and instructions. It can send data and
instructions from one register to another register, memory to register, and memory to memory,
the register transfer approach is used.
• The data transfer from one register to another is named in representative design using a
replacement operator. The statement is
R2←R1
• It indicates a transfer of the content of register R1 into register R2. It labelled a replacement of
the content of R2 by the content of R1. The content of the source register R1 does not shift after
the transfer.
 • The diagram demonstrates the block diagram that shows the transfer from R1 to R2. The n outputs
of register R1 are linked to the n inputs of register R2. The letter n can denote any number of bits for
the register. It will be restored by an actual number when the duration of the register is established.
• Register R2 has a load input that is activated by the control variable P. It is considered that the control
variable is synchronized with the equivalent clock like the one used to the register

Q.6
Ans. What is interrupt? Describe interrupt cycle with neat diagram.
• An interrupt is a condition that halts the microprocessor temporarily to work on a different task
and then returns to its previous task. An interrupt is an event or signal that requests the CPU's
attention.
• The way that the interrupt is handled by the computer can be explained by means of the flowchart
shown in figure 2.13.An interrupt flip-flop R is included in the computer.
• When R = 0, the computer goes through an instruction cycle.
• During the execute phase of the instruction cycle IEN is checked by the control.
• If it is 0, it indicates that the programmer does not want to use the interrupt, so control continues
with the next instruction cycle.
• If IEN is 1, control checks the flag bits.If both flags are 0, it indicates that neither the input nor
 the output registers are ready for transfer of information.
• In this case, control continues with the next instruction cycle. If either flag is set to 1 while IEN
= 1, flip-flop R is set to 1.
• At the end of the execute phase, control checks the value of R, and if it is equal to 1, it goes to
an interrupt cycle instead of an instruction cycle.

• The interrupt cycle is a hardware implementation of a branch and save return address operation.
• The return address available in PC is stored in a specific location where it can be found later
when the program returns to the instruction at which it was interrupted. This location may be a
processor register, a memory stack, or a specific memory location.
• Here we choose the memory location at address 0 as the place for storing the return address.
• Control then inserts address 1 into PC and clears IEN and R so that no more interruptions can
occur until the interrupt request from the flag has been serviced.
• An example that shows what happens during the interrupt cycle is shown in Figure 2.14:

Q.7 Draw and explain the flowchart for instruction cycle and explain any seven logic micro operation.
Ans. • A program residing in the memory unit of the computer consists of a sequence of instructions. In
the basic computer each instruction cycle consists of the following phases:
 o Fetch an instruction from memory.
o Decode the instruction.
o Read the effective address from memory if the instruction has an indirect address.
o Execute the instruction.
• After step 4, the control goes back to step 1 to fetch, decode and execute the nex instruction.

• The flowchart presents an initial configuration for the instruction cycle and shows how the control
determines the instruction type after the decoding.
• If D7 = 1, the instruction must be register-reference or input-output type. If D7 = 0, the operation
code must be one of the other seven values 110, specifying a memory- reference instruction.
Control then inspects the value of the first bit of the instruction, which now available in flip-flop
I.
• If D7 = 0 and I = 1, we have a memory-reference instruction with an indirect address. It is then
necessary to read the effective address from memory.The three instruction types are subdivided
into four separate paths. The selected operation is activated with the clock transition associated
with timing signal T3.This can be symbolized as follows:
D’7 I T3: AR ßM [AR]
D’7 I’ T3: Nothing
D7 I’ T3: Execute a register-reference instruction
D7 I T3: Execute an input-output instruction

• When a memory-reference instruction with I = 0 is encountered, it is not necessary to do anything

since the effective address is already in AR.
 Logic Micro-Operation:

Q.8 Draw the flowchart of first pass of the assembler and explain working of the same.
Ans. First Pass of an assembler:
• During the first pass, it generates a table that correlates all user-defined address symbols with
their binary equivalent value.The binary translation is done during the second pass.
• To keep track of the location of instructions, the assembler uses a memory word called a location
counter (abbreviated LC).The content of LC stores the value of the memory location assigned to
the instruction or operand presently being processed.
• The ORG pseudo instruction initializes the location counter to the value of the first location.
• Since instructions are stored in sequential locations, the content of LC is incremented by 1 after
processing each line of code.
• To avoid ambiguity in case ORG is missing, the assembler sets the location counter to 0 initially.
• The tasks performed by the assembler during the first pass are described in the flowchart of figure
3.1.
• LC is initially set to 0. A line of symbolic code is analyzed to determine if it has a label (by the
presence of a comma).
• If the line of code has no label, the assembler checks the symbol in the instruction field.
• If it contains an ORG pseudo instruction, the assembler sets LC to the number that follows ORG
and goes back to process the next line.If the line has an END pseudo instruction the assembler
 terminates the first pass and goes to the second pass.
• If the line of code contains a label, it is stored in the address symbol table together with its binary
equivalent number specified by the content of LC Nothing is stored in the table if no label is
encountered.

First

LC ← 0

Scan next line of code

Set LC
Ye
No
Labe OR No
Yes
Ye
EN
Store symbol in
address symbol Go to
no
table together Secon
ith l f dPass

Increment

What is assembler? Draw the flowchart of second pass of the assembler.

Q.9
Assembler:An assembler is a program that accepts a symbolic language program and produces its
Ans
binary machine language equivalent. The input symbolic program is called the source program and
the resulting binary program is called the object program.
• Machine instructions are translated during the second pass by means of table-lookup procedures.
• A table-lookup procedure is a search of table entries to determine whether a specific item
matches one of the items stored in the table.
• The assembler uses four tables. Any symbol that is encountered in the program must be available
as an entry in one of these tables; otherwise, the symbol cannot be interpreted.
o Pseudo instruction table
o MRI table
o Non-MRI table
o Address symbol table
• The entries of the pseudo instruction table are the four symbols ORG, END, DEC, andHEX.
• Each entry refers the assembler to a subroutine that processes the pseudo instructionwhen
encountered in the program.
• The MRI table contains the seven symbols of the memory-reference instructions andtheir 3-bit
operation code equivalent.
• The non-MRI table contains the symbols for the 18 register-reference and input-output
instructions and their 16-bit binary code equivalent.
• The address symbol table is generated during the first pass of the assembly process.
• The assembler searches these tables to find the symbol that it is currently processing inorder to
determine its binary value.
• The tasks performed by the assembler during the second pass are described in theflowchart of
Figure 3.2.
• LC is initially set to 0.
• Lines of code are then analyzed one at a time.
• Labels are neglected during the second pass, so the assembler goes immediately to the
instruction field and proceeds to check the first symbol encountered.
• It first checks the pseudo instruction table.A match with ORG sends the assembler to a subroutine
that sets LC to an initial value.
• If the symbol encountered is not a pseudo instruction, the assembler refers to the MRItable.
• If the symbol is not found in this table, the assembler refers to the non-MRI table.
• A symbol found in the non-MRI table corresponds to a register reference or input-output
instruction.
• The assembler stores the 16-bit instruction code into the memory word specified by LC.
• The location counter is incremented and a new line analyzed.
• When a symbol is found in the MRI table, the assembler extracts its equivalent 3-bitcode
and inserts it m bits 2 through 4 of a word.The second symbol is a symbolic address and the
third, which may or may not bepresent, is the letter I.
• The symbolic address is converted to binary by searching the address symbol table.
• The first bit of the instruction is set to 0 or 1, depending on whether the letter I is absentor
present.
• The three parts of the binary instruction code are assembled and then stored in thememory
location specified by the content of LC.

LC ← 0
D
Scan next line of code
Set LC
Pseudo-
instruction ORG END

MR Convert
operand to
Get Operation Code binary and
Valid non- store in
and set bits 2-4
MRI location
Search address-
symbol table for
binary equivalent of
symbolic address and
Store binary Error in
I Equivalent of line of
instruction in
Set first Set first location given by
bit to 1 bit to 0 LC

Assemble all parts of binary

instruction and store in Increment LC
location given by LC
Q.10 Elaborate flynn’s classification scheme with proper diagram
Ans. Flynn's classification
• It is based on the multiplicity of Instruction Streams and Data Streams
Instruction Stream: Sequence of Instructions read from memory
Data Stream: Operations performed on the data in the processor
Q.11 List various types of addressing modes and explain any five of them.
Ans. The general addressing modes supported by the computer processor are as follows:
• Implied addressing mode
• Immediate addressing mode
• Direct addressing mode
• Indirect addressing mode
• Register addressing mode
• Register indirect addressing mode
• Auto-increment/decrement addressing mode
• Relative addressing mode
• Indexed addressing mode
• Base Register Addressing mode
Implied mode:
• In this mode the operands are specified implicitly in the definition of the definition of the
instruction. For example, the instruction “complement accumulator” is an implied-mode
instruction because the operand in the accumulator is an implied mode instructionbecause the
operand in the accumulator register is implied in the definition of theinstruction.
• In fact all register later register is implied in the definition of the instruction. In fact, all register
reference instructions that use an accumulator are implied mode instructions.
Immediate Mode:
• In this mode the operand is specified in the instruction itself. In other words, animmediate-mode
instruction has an operand field rather than an address field.
• The operand field contains the actual operand to be used in conjunction with the operation
specified in the instruction.
• Immediate mode of instructions is useful for initializing register to constant value.
 Register Mode:
• In this mode the operands are in registers that within the CPU. The particular register isselected
from a register field in the instruction.
• A k-bit field can specify any one of 2k registers

Register Indirect Mode:

• In this mode the instruction specifies a register in the CPU whose contents give the address of the
operand in memory.
• Before using a register indirect mode instruction, the programmer must ensure that the memory
address of the operand is placed in the processor register with a previous instruction.
• The advantage of this mode is that address field of the instruction uses fewer bits to select a register
than would have been required to specify a memory address directly.

Auto increment or Auto decrement Mode:

• This is similar to the register indirect mode expect that the register is incremented or decremented
after (or before) its value is used to access memory.
• When the address stored in the register refers to a table of data in memory, it isnecessary to
increment or decrement the register after every access to the table. Thiscan be achieved by using
the increment or decrement instruction.

Direct Address Mode:

• In this mode the effective address is equal to the address part of the instruction. The operand resides
in memory and its address is given directly by the address field of the instruction.

Q.12 Compare and contrast RISC and CISC.

Ans.
Q.13 Explain arithmetic pipeline. Summarize major hazards in pipelined execution.
Ans. • The inputs to the floating-point adder pipeline are two normalized floating-point binarynumbers.

• A and B are two fractions that represent the mantissas and a and b are the exponents.
• The floating-point addition and subtraction can be performed in four segments, asshown in Figure
6.6.
• The registers labeled R are placed between the segments to store intermediate results.
• The sub-operations that are performed in the four segments are:
• Compare the exponents
• Align the mantissas
• Add or subtract the mantissas
• Normalize the result
• The following numerical example may clarify the sub-operations performed in eachsegment.
• For simplicity, we use decimal numbers, although Figure 6.6 refers to binary numbers.
• Consider the two normalized floating-point numbers:X = 0.9504 x 103
Y = 0.8200 x 102
• The two exponents are subtracted in the first segment to obtain 3 - 2 = 1.
• The larger exponent 3 is chosen as the exponent of the result.
• The next segment shifts the mantissa of Y to the right to obtainX = 0.9504 x 103
Y = 0.0820 x 103
• This aligns the two mantissas under the same exponent. The addition of the twomantissas in
 segment 3 produces the sum Z = 1.0324 x 103

• There are three major difficulties that cause the instruction pipeline conflicts.
o Resource conflicts caused by access to memory by two segments at the same time.
o Data dependency conflicts arise when an instruction depends on the result of a previous
instruction, but this result is not yet available.
o Branch difficulties arise from branch and other instructions that change the value of PC.
Data Dependency:
o A collision occurs when an instruction cannot proceed because previous instructions
didnot complete certain operations.
o A data dependency occurs when an instruction needs data that are not yet available.
o Similarly, an address dependency may occur when an operand address cannot be
calculated because the information needed by the addressing mode is not available.
o Pipelined computers deal with such conflicts between data dependencies in a variety of
ways as follows.
Handling of Branch Instructions:
o One of the major problems in operating an instruction pipeline is the occurrence of
branch instructions.
o A branch instruction can be conditional or unconditional.
o The branch instruction breaks the normal sequence of the instruction stream, causing
difficulties in the operation of the instruction pipeline.
o Various hardware techniques are available to minimize the performance degradation
caused by instruction branching.
Q.14 Demonstrate four-segment instruction pipeline in detail
Ans. • Assume that the decoding of the instruction can be combined with the calculation of the effective
address into one segment.
• Assume further that most of the instructions place the result into a processor registersso that the
instruction execution and storing of the result can be combined into one segment.
• This reduces the instruction pipeline into four segments.
• FI: Fetch an instruction from memory
• DA: Decode the instruction and calculate the effective address of the operand
• FO: Fetch the operand
• EX: Execute the operation
• Figure 6.7 shows, how the instruction cycle in the CPU can be processed with a four- segment
pipeline.
• While an instruction is being executed in segment 4, the next instruction in sequence is busy
fetching an operand from memory in segment 3.
• The effective address may be calculated in a separate arithmetic circuit for the third instruction,
and whenever the memory is available, the fourth and all subsequent instructions can be fetched
and placed in an instruction FIFO.
• Thus up to four sub operations in the instruction cycle can overlap and up to four different
instructions can be in progress of being processed at the same time.
 What is the significance of pipelining in computer architecture? & Describe pipeline conflicts
Q.15
• Pipeline is a technique of decomposing a sequential process into sub operations, with each sub
Ans:
process being executed in a special dedicated segment that operates concurrently with all other
segments.
• A pipeline can be visualized as a collection of processing segments through which binary
information flows.
• Each segment performs partial processing dictated by the way the task is partitioned.
• The result obtained from the computation in each segment is transferred to the nextsegment in
the pipeline.
• It is characteristic of pipelines that several computations can be in progress in distinctsegments
at the same time.
• The overlapping of computation is made possible by associating a register with eachsegment
in the pipeline.
• The registers provide isolation between each segment so that each can operate ondistinct
data simultaneously.
• Any operation that can be decomposed into a sequence of sub operations of about thesame
complexity can be implemented by a pipeline processor.
• The technique is efficient for those applications that need to repeat the same task manytimes with
 different sets of data.
• The general structure of a four-segment pipeline is illustrated in Figure 6.5.

Pipeline conflict:
• There are three major difficulties that cause the instruction pipeline conflicts.
o Resource conflicts caused by access to memory by two segments at the same time.
o Data dependency conflicts arise when an instruction depends on the result of a previous
instruction, but this result is not yet available.
o Branch difficulties arise from branch and other instructions that change the value of PC.
Q.16 Write an assembly language program to add and subtract two given numbers and store it.
Ans.
ADD:
LXI H,2000H
MOV A,M
INX H
MOV B,M
ADD B
INX H
MOV M,A
HLT

SUBTRACT:
LXI H,2000H
MOV A,M
INX H
MOV B,M
SUB B
INX H
MOV M,A
HLT
Q.17 Explain register stack and memory stack in detail.
Ans:

• A stack can be placed in a portion of a large memory or it can be organized as acollection of a

finite number of memory words or registers. Figure shows the organization of a 64-word register
stack.
• The stack pointer register SP contains a binary number whose value is equal to the address of the
word that is currently on top of the stack. Three items are placed in the stack: A, B, and C, in that
order. Item C is on top of the stack so that the content of SP is now 3.
• To remove the top item, the stack is popped by reading the memory word at address 3 and
decrementing the content of SP. Item B is now on top of the stack since SP holds address 2.
• To insert a new item, the stack is pushed by incrementing SP and writing a word in the next-higher
location in the stack.
• In a 64-word stack, the stack pointer contains 6 bits because 26 = 64
Memory Stack:
Q.18 Write a program to evaluate the arithmetic statement: A*B+C*D+E
Ans. i. Using an accumulator type computer.
ii. Using a stack organized computer.

Using an Accumulator:
LOAD A
MUL B
ADD C
MUL D
ADD E

Using a stack organized computer:

PUSH A TOSA
PUSH B TOSB
MUL TOSA*B
PUSH C TOSC
ADD TOSA*B+C
PUSH D TOSD
MUL TOSA*B+C*D
PUSH E TOSE
ADD TOSA*B+C*D+E
POP X M[X] TOS

Q.19 Explain booth’s multiplication algorithm. Assume a computer system uses 5 bit (1 sign +4
Ans. Magnitude) registers and 2’s complement representation. Perform multiplication of number 10 with
the smallest number in this system using booth algorithm. Show step- by-step multiplication
process.
• Booth algorithm gives a procedure for multiplying binary integers in signed- 2’s complement
representation.
• It operates on the fact that strings of 0’s in the multiplier require no addition but just shifting, and
a string of 1’s in the multiplier from bit weight 2 k to weight 2 m can be treated as 2 k+1 – 2 m .
• For example, the binary number 001110 (+14) has a string 1’s from 2 3 to 2 1 (k=3, m=1). The
number can be represented as 2 k+1 – 2 m . = 2 4 – 2 1 = 16 – 2 = 14. Therefore, the multiplication
M X 14, where M is the multiplicand and 14 the multiplier, can be done as M X 2 4 – M X 2 1 .
• Thus the product can be obtained by shifting the binary multiplicand M four times to the left and
subtracting M shifted left once.
 • As in all multiplication schemes, booth algorithm requires examination of the multiplier bits and
shifting of partial product.
• Prior to the shifting, the multiplicand may be added to the partial product, subtracted from the
partial, or left unchanged according to the following rules:
1. The multiplicand is subtracted from the partial product upon encountering the first least
significant 1 in a string of 1’s in the multiplier.
2. The multiplicand is added to the partial product upon encountering the first 0 in a string of 0’s
in the multiplier.
3. The partial product does not change when multiplier bit is identical to the previous multiplier
bit.
• The algorithm works for positive or negative multipliers in 2’s complement representation.
• This is because a negative multiplier ends with a string of 1’s and the last operation will be a
subtraction of the appropriate weight.
• The two bits of the multiplier in Qn and Qn+1 are inspected.
• If the two bits are equal to 10, it means that the first 1 in a string of 1 's has been encountered.
This requires a subtraction of the multiplicand from the partial product in AC.
• If the two bits are equal to 01, it means that the first 0 in a string of 0's has been encountered.
This requires the addition of the multiplicand to the partial product in AC.
• When the two bits are equal, the partial product does not change.

Example:

+10 = 1010
+1 = 0001
BR= 1010, QR=0001
Q.20 Draw and explain flow chart of address sequencing. & Explain BCD adder in brief
Ans. Microinstructions are stored in control memory in groups, with each group specifying a routine.
• To appreciate the address sequencing in a micro-program control unit, let us specify the steps that
the control must undergo during the execution of a single computer instruction.
BCD Adder:
 • BCD representation is a class of binary encodings of decimal numbers where each decimal digit
is represented by a fixed number of bits.
• BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit in BCD form.
• Since each input digit does not exceed 9, the output sum cannot be greater than 19(9+9+1). For
example: suppose we apply two BCD digits to 4-bit binary adder.
• The adder will form the sum in binary and produce a result that may range from 0 to 19.
• In following figure 7.5, these binary numbers are represented by K, Z8, Z4, Z2, and Z1.
• K is the carry and subscripts under the Z represent the weights 8, 4, 2, and 1 that can be assigned
to the four bits in the BCD code.
• When binary sum is equal to or less than or equal to 9, corresponding BCD number is identical
and therefore no conversion is needed.
• The condition for correction and output carry can be expressed by the Boolean function:
C= K + Z8Z4 + Z8 Z2

• When it is greater than 9, we obtain non valid BCD representation, then additional binary 6 to
binary sum converts it to correct BCD representation.
• The two decimal digits, together with the input-carry, are first added in the top 4-bit binary adder
to produce the binary sum. When the output-carry is equal to 0, nothing is added to the binary sum.
• When C is equal to 1, binary 0110 is added to the binary sum using bottom 4-bit binary adder. The
output carry generated from the bottom binary-adder may be ignored.

Q.21 Explain Control Memory & What is micro-Programmed Control architecture?

Ans.
Microprogrammed Control:
• The basic components of a microprogrammed control unit are the control memory and the circuits
that select the next address.
• The address selection part is called a microprogram sequencer.
• A microprogram sequencer can be constructed with digital functions to suit a particular
application.
• To guarantee a wide range of acceptability, an integrated circuit sequencer must provide an internal
organization that can be adapted to a wide range of applications.
• The purpose of a microprogram sequencer is to present an address to the control memory so that
a microinstruction may be read and executed.
• Commercial sequencers include within the unit an internal register stack used for temporary
storage of addresses during microprogram looping and subroutine calls.
• Some sequencers provide an output register which can function as the address register for the
control memory
Q.22 Briefly explain DMA & DMA Controls.
Ans.
Q.23
Explain any two types of mapping procedures when considering the organization of Cache memory.
Ans.
Direct Mapping:
Q.24 What is virtual memory? Explain relation between address space and memory space in virtual
memory system.
Ans.
Virtual Memory:
• Virtual memory is used to give programmers the illusion that they have a very large memory at
their disposal, even though the computer actually has a relatively small main memory.
• A virtual memory system provides a mechanism for translating program-generated addresses into
correct main memory locations
 Discuss source-initiated transfer using handshaking in asynchronous data transfer.
Q.25 • The handshake method solves the problem of Strobe method by introducing a second control
Ans. signal that provides a reply to the unit that initiates the transfer.

Source-initiated transfer using handshaking

• One control line is in the same direction as the data flow in the bus from the source tothe
destination.
• It is used by the source unit to inform the destination unit whether there are valid data inthe bus.
 Write a brief note on memory hierarchy & Elaborate CPU-IOP communication.
Q.26
Memory Hierarchy:
Ans.
A memory unit is an essential component in any digital computer since it is needed for storing programs
and data.

Typically, a memory unit can be classified into two categories:

1. The memory unit that establishes direct communication with the CPU is called Main Memory. The
main memory is often referred to as RAM (Random Access Memory).
2. The memory units that provide backup storage are called Auxiliary Memory. For instance,
magnetic disks and magnetic tapes are the most commonly used auxiliary memories.

Apart from the basic classifications of a memory unit, the memory hierarchy consists all of the storage
devices available in a computer system ranging from the slow but high-capacity auxiliary memory to
relatively faster main memory.

• Auxiliary memory is known as the lowest-cost, highest-capacity and slowest-access storage in a

computer system.
• The main memory in a computer system is often referred to as Random Access Memory (RAM).
This memory unit communicates directly with the CPU and with auxiliary memory devices
through an I/O processor.
CPU-IOP Communication:
Q.27 Differentiate Programmed I/O and Interrupt initiated I/O
Ans.
Q.28
Elaborate cache coherence problem with its solutions.
Ans.
Q.29 Discuss in brief the interconnection structures of a multiprocessor system. & Discuss various
Ans. Dynamic Arbitration Algorithms for Interprocessor Arbitration.
Dynamic Arbitration Algorithms
• A dynamic priority algorithm gives the system the capability for changing the priority of the
devices while the system is in operation.
Time slice
• The time slice algorithm allocates a fixed-length time slice of bus time that is offered
sequentially to each processor, in round-robin fashion.
• The service is location independent.
• No preference is given to any particular device since each is allotted the same amount
oftime to communicate with the bus.

Polling

• In a bus system that uses polling, the bus grant signal is replaced by a set of lines called
polllines which are connected to all units.
• These lines are used by the bus controller to define an address for each device connected
tothe bus.
• The bus controller sequences through the addresses in a prescribed manner.
• When a processor that requires access recognizes its address, it activates the bus busy
lineand then accesses the bus.
• After a number of bus cycle, the polling process continues by choosing a different processor
• The polling sequence is normally programmable, and as a result, the selection priority
canbe altered under program control.
LRU
• The least recently used (LRU) algorithm gives the highest priority to the requesting
devicethat has not used the bus for the longest interval.
• The priorities are adjusted after a number of bus cycles according to the LRU algorithm.
 • With this procedure, no processor is favored over any other since the priorities are
dynamically changed to give every device an opportunity to access the bus.

FIFO
• In the first-come first-serve scheme, requests are served in the order received.
• To implement this algorithm the bus controller establishes a queue arranged according
tothe time that the bus requests arrive.
• Each processor must wait for its turn to use the bus on a first-in first-out (FIFO) basis.

Rotating daisy-chain
• The rotating daisy-chain procedure is a dynamic extension of the daisy chain algorithm.
Highest priority to the unit that is nearest to the unit that has most recently accessed the
bus(it becomes the bus controller).

Q.30 State the differences between hardwired control and micro programmed control.
Ans.
Q.31 Write the symbolic microprogram routine for the BSA instruction. Use the microinstruction format
Ans. of basic micro programmed control unit.

Q.32 A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored
Ans. in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register
code part to specify one of 64 registers, and an address part.
1. How many bits are there in operation code, the register code part and the address part?
2. Draw the instruction word format and indicate the number of bits in each part.
3. How many bits are there in the data and address inputs of the memory?
Number of bits in each part of the instruction:
Total memory words: 256K
Memory word size: 32 bits
Instruction stored in one word of memory
Instruction parts: Indirect bit, Operation code, Register code, Address part
Given:
Word size: 32 bits
Indirect bit: 1 bit
Register code part (to specify one of 64 registers): Assuming log2(64) = 6 bits
Address part: Remaining bits after accounting for other parts
Calculation:

Bits for operation code: Total bits - (Indirect bit + Register code bits)
Bits for operation code = 32 - (1 + 6) = 25 bits
So,
Bits in operation code: 25 bits
Bits in register code part: 6 bits
Bits in address part: Remaining bits, which is 32 - (1 + 25 + 6) = 32 - 32 = 0 bits
Instruction word format:

Indirect Operation Regis Address

bit code ter
 1 bit 25 bits 6 bits 0 bits

Number of bits in data and address inputs of the memory:

For the given memory unit:
Memory words: 256K
Word size: 32 bits
So
Number of bits in data input: Word size = 32 bits
Number of bits in address input: Log2(256K) = 18 bits
Thus,
Bits in data input of memory: 32 bits
Bits in address input of memory: 18 bits

Q. 33 Calculate the size of a ROM chip which operates using 8-bit data bus, two chip select lines and 9-bit
Ans. address bus.
Data bus width: 8 bits
Address bus width: 9 bits
Two chip select lines
Number of addressable locations = 29=512
Size of ROM chip = Number of addressable locations × Data width
Size=512×8
Size=4096
convert the size to a more common unit like kilobits (Kb) or megabits (Mb) if needed.
For e.g, to convert bits to kilobits, we divide by 1024:
4096 bits=4096 / 1024 kilobits
=4 Kb
So, the size of the ROM chip is 4 kilobits.

Q.34 Explain status bit conditions with neat diagram. & Explain Types of array processor.
Ans.
• It is sometimes convenient to supplement the ALU circuit in the CPU with a status register where
status bit conditions be stored for further analysis. Status bits are also called condition-code bits
or flag bits.
• Figure 5.3 shows the block diagram of an 8-bit ALU with a 4-bit status register. The four status
bits are symbolized by C, S, Z, and V. The bits are set or cleared as a result of an operation
performed in the ALU.

1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.

 2. Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to 0 if set to 0 if the bit is 0.

3. Bit Z (zero) is set to 1 if the output of the ALU contains all 0’s. it is cleared to 0 otherwise. In other
words, Z = 1 if the output is zero and Z = 0 if the output is not zero.

4. Bit V (overflow) is set to 1 if the exclusives-OR of the last two carries is equal to 1, and cleared to 0
otherwise. This is the condition for an overflow when negative numbers are in 2’s complement. For
the 8-bit ALU, V = 1 if the output is greater than + 127 or less than -128.

• The status bits can be checked after an ALU operation to determine certain relationships that
exist between the vales of A and B.
• If bit V is set after the addition of two signed numbers, it indicates an overflow condition.
• If Z is set after an exclusive-OR operation, it indicates that A = B.
• A single bit in A can be checked to determine if it is 0 or 1 by masking all bits except the bit in
question and then checking the Z status bit.

Types of array processor:

Q.35 Write a detailed note on associative memory (or Explain Content Addressable Memory (CAM).) &
Ans. Explain Write-through and Write-back cache write method.
• The time required to find an item stored in memory can be reduced considerably if stored data can
be identified for access by the content of the data itself rather than by an address.
• A memory unit accessed by content is called an associative memory or content addressable
memory (CAM).
• This type of memory is accessed simultaneously and in parallel on the basis of data content rather
than by specific address or location.

·
 • The block diagram of an associative memory is shown in figure 9.3.

Block diagram of associative memory

• It consists of a memory array and logic form words with n bits per word.

• The argument register A and key register K each have n bits, one for each bit of a word.

• The match register M has m bits, one for each memory word.

• Each word in memory is compared in parallel with the content of the argument register.

• The words that match the bits of the argument register set a corresponding bit in the match register.

• After the matching process, those bits in the match register that have been set indicate the fact that
their corresponding words have been matched.

• Reading is accomplished by a sequential access to memory for those words whose corresponding
bits in the match register have been set.

Write Through
• The simplest and most commonly used procedure is to update main memory with every memory
write operation.
• The cache memory being updated in parallel if it contains the word at the specified address. This
is called the write-through method.
• This method has the advantage that main memory always contains the same data as the cache.
• This characteristic is important in systems with direct memory access transfer·
• It ensures that the data residing in main memory are valid at all times so that an I/O device
communicating through DMA would receive the most recent updated data
Write-Back (Copy-Back)
• The second procedure is called the write-back method.

• In this method only the cache location is updated during a write operation.

• The location is then marked by a flag so that later when the word is removed from the cache it is
copied into main memory.

• The reason for the write-back method is that during the time a word resides in the cache, it may be
updated several times.

• However, as long as the word remains in the cache, it does not matter whether the copy in main
memory is out of date, since requests from the word are filled from the cache.

• It is only when the word is displaced from the cache that an accurate copy need be rewritten into
main memory.