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interrupt programming

The document discusses interrupt programming in the 8051 microcontroller, detailing how interrupts signal the microcontroller to pause its current task and execute an interrupt service routine (ISR). It outlines types of interrupts, including timer, external hardware, and serial communication interrupts, along with the enabling and disabling of interrupts via the IE register. Additionally, it explains the differences between level-triggered and edge-triggered interrupts and their configurations using the TCON register.

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Abhishek Pankaj
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1 views

interrupt programming

The document discusses interrupt programming in the 8051 microcontroller, detailing how interrupts signal the microcontroller to pause its current task and execute an interrupt service routine (ISR). It outlines types of interrupts, including timer, external hardware, and serial communication interrupts, along with the enabling and disabling of interrupts via the IE register. Additionally, it explains the differences between level-triggered and edge-triggered interrupts and their configurations using the TCON register.

Uploaded by

Abhishek Pankaj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

5.3 INTERRUPT PROGRAMMING IN 8051

The Microcontroller can serve several devices. The Interrupt is the method to
indicate the microcontroller by sending an interrupt signal. After receiving an interrupt,
the microcontroller interrupts whatever it is doing and serves the device. The program
associated with the interrupt is called the interrupt service routine (ISR). When an
interrupt is invoked, the microcontroller runs the interrupt service routine. For every
interrupt, there is a fixed location set aside to hold the addresses of ISRs.

The following events will cause an interrupt:


1. Timer 0 Overflow.
2. Timer 1 Overflow.
3. Reception/Transmission of Serial Character.
4. External Event 0.
5. External Event 1.

To distinguish between various interrupts and executing different code depending on


what interrupt was triggered, 8051may be jumping to a fixed address when a given
interrupt occurs as shown in Table 5.3.1.

Table 5.3.1 Interrupt Vector Table for 8051

[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.320]

EC8691 MICROPROCESSORS AND MICROCONTROLLERS


ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

ENABLING AND DISABLING AN INTERRUPT

Upon reset all interrupts are disable, meaning that known will be responded to by
the microcontroller if they are activated. The Interrupt must be enabled by software in
order for microcontroller to respond to them there is a register called IE that is responsible
for enabling and disabling the interrupts as shown in Figure 5.3.1

Figure 5.3.1 Interrupt Enable(IE) Register


[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.321]
PROGRAMMING EXTERNAL HARDWARE INTERRUPTS
The 8051 has two external hardware interrupts PIN 12 (P3.2) and Pin 13 (P3.3),
designated as INT0 and INT1. Upon activation of these pins, the 8051 finishes the

EC8691 MICROPROCESSORS AND MICROCONTROLLERS


ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

execution of current instruction whatever it is executing and jumps to the vector table to
perform the interrupt service routine.

TYPES OF INTERRUPT
1)Level-TriggeredInterrupt
2)Edge -Triggered Interrupt
LEVEL-TRIGGERED INTERRUPT
In this mode, INT0 and INT1 are normally high and if the low level signal is
applied to them, it triggers the Interrupt. Then the microcontroller stops and jumps to the
interrupt vector table to service that interrupt. The low-level signal at the INT pin must
be removed before the execution of the last instruction of the ISR, RETI. Otherwise,
another interrupt will be generated. This is called a level-triggered or level-activated
interruptandis the default mode upon reset

Figure 5.3.2 Activation of INT0 and INT1


[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.326]
EDGE -TRIGGERED INTERRUPT
Upon reset 8051 makes INT0 and INT1 low l Level-Triggered Interrupt. To make
them Edge -Triggered Interrupt, we must program the bits of the TCON Register. The
TCON register holds among other bits and IT0 and IT1 flags bit the determine level- or
edge triggered mode. IT0 and IT1 are bits D0 (TCON.0) and D2(TCON.2) of the TCON
Register respectively.

EC8691 MICROPROCESSORS AND MICROCONTROLLERS


ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

Figure 5.3.3 Example for Level triggered Interrupt

[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.327]

SERIAL COMMUNICATION INTERRUPT

TI (transfer interrupt) is raised when the stop bit is transferred indicating that the SBUF
register is ready to transfer the next byte

RI (received interrupt) is raised when the stop bit is received indicating that the received
byte needs to be picked up before it is lost (overrun) by new incoming serial data

In the 8051 there is only one interrupt set aside for serial communication ,used for both
sending and receiving data.

EC8691 MICROPROCESSORS AND MICROCONTROLLERS


ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

If the interrupt bit in the IE register (IE.4) is enabled, when RI or TI is raised the 8051
gets interrupted and jumps to memory location 0023H to execute the ISR

In that ISR we must examine the TI and RI flags to see which one caused the interrupt
and respond accordingly.

Figure 5.3.4 Example for Serial Communication Interrupt


[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.334]

TIMER INTERRUPTS

The timer flag (TF) is raised when the timer rolls over. In polling TF, we have to
wait until the TF is raised. The microcontroller is tied down while waiting for TF to be
raised, and cannot do anything else. If the timer interrupt in the IE register is enabled,
whenever the timer rolls over, TF is raised. This avoids tying down the controller.

The microcontroller is interrupted in whatever it is doing, and jumps to the


interrupt vector table to service the ISR.In this way, the microcontroller can do other task
until it is notified that the timer has rolled over

EC8691 MICROPROCESSORS AND MICROCONTROLLERS


ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

Figure 5.3.5 Example for Timer Interrupt


[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.323]

EC8691 MICROPROCESSORS AND MICROCONTROLLERS

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