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Processors Interrupt Service Mechanism - W2 ASS3-1

The document discusses the interrupt service mechanisms of various processors, including 8051, 68HC11, and ARM7, focusing on context saving during interrupts. It highlights the advantages and disadvantages of each mechanism, particularly the trade-offs between speed and programmer responsibility for context saving. The summary emphasizes the importance of saving the CPU state to ensure proper multitasking and execution of multiple tasks.

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14 views11 pages

Processors Interrupt Service Mechanism - W2 ASS3-1

The document discusses the interrupt service mechanisms of various processors, including 8051, 68HC11, and ARM7, focusing on context saving during interrupts. It highlights the advantages and disadvantages of each mechanism, particularly the trade-offs between speed and programmer responsibility for context saving. The summary emphasizes the importance of saving the CPU state to ensure proper multitasking and execution of multiple tasks.

Uploaded by

Mahu D
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ASY3

P18EST1002

DESIGN OF EMBEDDED SYSTEMS

UNIT2 - Processors Interrupt Service Mechanism


from Context Saving Angle
Dr.B.KARUNAMOORTHY , ASP
Department of Electrical and Electronics Engineering
Overview of this Lecturer

➢ Classification of Processors Interrupt


Service Mechanism from Context Saving
angleDRIVERS AND INTERRUPTS SERVICE
MECHANISM
Context

➢ The multitasking and multiple ISRs execute


even though there is only one processor by first
saving the one program context and retrieving
another program context
Context
➢ Executes multiple tasks (processes)
➢ Operating system facilitates this
➢ perform multiple actions or functions due to
multiple sources of the interrupts
➢ An interrupt service mechanism in the system
facilitates this
8051
8051 interrupt-service mechanism is such that on
occurrence of an interrupt service, the processor pushes
the processor registers PCH (program counter higher
byte) and PCL (program counter higher byte) on to the
memory stack.
The 8051 family processors do not save the context of
the program (other than the absolutely essential program
counter) and a context can save only by using the specific
set of instructions for that. For example, using Push
instructions at the ISR.
Advantage of Saving PC only in
8051
➢ It speeds up the start of ISR and returns from
ISR but at a cost.
➢ The onus of context saving is on the
programmer in case the context (SP and CPU
registers other than PCL and PCH) to be
modified on service of or on function calls
during execution of the remaining ISR
instructions
68HC11 interrupt mechanism

➢ Processor registers save on to the stack whenever an


interrupt service occurs.
➢ These are in the order of PCL, PCH, IYL, IYH, IXL, IXH,
ACCA, ACCB, and CCR.
➢ 68HC11 thus does automatically save the processor
context of the program without being so any instructed
in the user program.
68HC11 interrupt mechanism
➢As context saving takes processor time, it slows
a little at the start of ISR and returns from ISR
but at the a great advantage that the onus of
context saving is not there on the programmer
and there is no risk in case the context modifies
on service or function calls
ARM7 interrupt mechanism
• ARM7 provides a mechanism for fast context
switching between the two tasks, one current and
one at the stack
Summary
• Each running-program has a context at an instant.
• Context means a CPU state (program counter, stack
pointer(s), registers and program state (variables that
should not be modified by another routine).
• The context must be saved on a call to another ISR
or task or routine

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