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Instruction Set of 8085

 An instruction is a binary pattern designed inside a microprocessor

to perform a specific function.

 The entire group of instructions that a microprocessor supports is

INSTRUCTION SET OF 8085 called Instruction Set.

 8085 has 246 instructions.

 Each instruction is represented by an 8-bit binary value.

 These 8-bits of binary value is called Op-Code or Instruction Byte.

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How to Write Instruction

An Instruction is a command to the microprocessor to perform a given task Classification of Instruction Set
on specified data.
Each instruction has two parts: one is the task to be performed, called the
operation code (op-code), and the second is the data to be operated on,
called the operand. • Data Transfer Instruction

The operand (or data) can be specified in various ways. It may include 8-bit • Arithmetic Instructions
(or 16-bit) data, an internal register, a memory location, or an 8-bit (or 16-
bit) address. Example: MOV r1, r2, LDA 2050H, JMP 2080H, XRA M etc. • Logical Instructions

Purpose of Instruction • Branching Instructions

1.Determine the desired operation
2. Prepare all the necessary data • Control Instructions
3. Allot required memory space
4. Execute the operation
5. Preserve the result of the operation

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Data Transfer Instructions Data Transfer Instructions

Opcode Operand Description
• These instructions move data between registers, or between MOV Rd, Rs Copy from source to destination.
memory and registers. Rd, M
M, Rs
• These instructions copy data from source to destination.  This instruction copies the contents of the source register into the
destination register.
• While copying, the contents of source are not modified.
 The contents of the source register are not altered.

 If one of the operands is a memory location, its location is specified by

the contents of the HL registers.

 Example: MOV B, C

 MOV B, M

 MOV M, C

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Data Transfer Instructions Data Transfer Instructions

Opcode Operand Description Opcode Operand Description

MVI Rd, Data Move immediate 8-bit LXI Reg. pair, 16-bit Load register pair immediate
M, Data data

 The 8-bit data is stored in the destination register or  This instruction loads 16-bit data in the register pair.
memory.
 Example: LXI H, 2034 H
 If the operand is a memory location, its location is
specified by the contents of the H-L registers.

 Example: MVI A, 57H

 MVI M, 57H

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Data Transfer Instructions Data Transfer Instructions

Opcode Operand Description Opcode Operand Description

LDA 16-bit address Load Accumulator LDAX B/D Register Pair Load accumulator indirect

 The contents of the designated register pair point to a memory

 The contents of a memory location, specified by a 16-
location.
bit address in the operand, are copied to the
accumulator.  This instruction copies the contents of that memory location into
the accumulator.
 The contents of the source are not altered.  The contents of either the register pair or the memory location are
not altered.
 Example: LDA 2034H
 Example: LDAX B

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Data Transfer Instructions Data Transfer Instructions

Opcode Operand Description Opcode Operand Description

LHLD 16-bit address Load H-L registers direct STA 16-bit address Store accumulator direct

 This instruction copies the contents of memory  The contents of accumulator are copied into the
location pointed out by 16-bit address into register L. memory location specified by the operand.

 It copies the contents of next memory location into  Example: STA 2500 H
register H.

 Example: LHLD 2040 H

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Data Transfer Instructions Data Transfer Instructions

Opcode Operand Description Opcode Operand Description

STAX Reg. pair Store accumulator indirect SHLD 16-bit address Store H-L registers direct

 The contents of accumulator are copied into the  The contents of register L are stored into memory
memory location specified by the contents of the location specified by the 16-bit address.
register pair.
 The contents of register H are stored into the next
 Example: STAX B memory location.

 Example: SHLD 2550 H

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Data Transfer Instructions Arithmetic Instructions

Opcode Operand Description • These instructions perform the operations like:

XCHG None Exchange H-L with D-E
• Addition

• Subtract
 The contents of register H are exchanged with the
• Increment
contents of register D.
• Decrement
 The contents of register L are exchanged with the
contents of register E.

 Example: XCHG

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Addition Subtraction

• Any 8-bit number, or the contents of register, or the contents of • Any 8-bit number, or the contents of register, or the contents of
memory location can be added to the contents of accumulator. memory location can be subtracted from the contents of
accumulator.
• The result (sum) is stored in the accumulator.
• The result is stored in the accumulator.
• No two other 8-bit registers can be added directly.
• Subtraction is performed in 2’s complement form.
• Example: The contents of register B cannot be added directly to the
contents of register C. • If the result is negative, it is stored in 2’s complement form.

• No two other 8-bit registers can be subtracted directly.

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Increment / Decrement Arithmetic Instructions

• The 8-bit contents of a register or a memory location can be Opcode Operand Description
incremented or decremented by 1. ADD R Add register or memory to accumulator
M
• The 16-bit contents of a register pair can be incremented or
decremented by 1.
 The contents of register or memory are added to the contents of
accumulator.
• Increment or decrement can be performed on any register or a
memory location.  The result is stored in accumulator.

 If the operand is memory location, its address is specified by H-L pair.

 All flags are modified to reflect the result of the addition.

 Example: ADD B or ADD M

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Arithmetic Instructions Arithmetic Instructions

Opcode Operand Description Opcode Operand Description

ADC R Add register or memory to accumulator with ADI 8-bit data Add immediate to accumulator
M carry

 The contents of register or memory and Carry Flag (CY) are added to the
contents of accumulator.
 The 8-bit data is added to the contents of accumulator.

 The result is stored in accumulator.  The result is stored in accumulator.

 If the operand is memory location, its address is specified by H-L pair.
 All flags are modified to reflect the result of the
 All flags are modified to reflect the result of the addition. addition.
 Example: ADC B or ADC M
 Example: ADI 45 H

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Arithmetic Instructions Arithmetic Instructions

Opcode Operand Description Opcode Operand Description

ACI 8-bit data Add immediate to accumulator with carry DAD Reg. pair Add register pair to H-L pair

 The 8-bit data and the Carry Flag (CY) are added to the  The 16-bit contents of the register pair are added to the
contents of H-L pair.
contents of accumulator.
 The result is stored in H-L pair.
 The result is stored in accumulator.
 If the result is larger than 16 bits, then CY is set.
 All flags are modified to reflect the result of the addition.
 No other flags are changed.
 Example: ACI 45 H  Example: DAD B

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Arithmetic Instructions Arithmetic Instructions

Opcode Operand Description Opcode Operand Description

SUB R Subtract register or memory from accumulator SBB R Subtract register or memory from accumulator
M M with borrow

 The contents of the register or memory location are subtracted from the  The contents of the register or memory location and Borrow Flag (i.e. CY)
contents of the accumulator. are subtracted from the contents of the accumulator.

 The result is stored in accumulator.  The result is stored in accumulator.

 If the operand is memory location, its address is specified by H-L pair.  If the operand is memory location, its address is specified by H-L pair.

 All flags are modified to reflect the result of subtraction.  All flags are modified to reflect the result of subtraction.

 Example: SUB B or SUB M  Example: SBB B or SBB M

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Arithmetic Instructions Arithmetic Instructions

Opcode Operand Description Opcode Operand Description

SUI 8-bit data Subtract immediate from accumulator SBI 8-bit data Subtract immediate from accumulator with
borrow

 The 8-bit data is subtracted from the contents of the  The 8-bit data and the Borrow Flag (i.e. CY) is subtracted
accumulator. from the contents of the accumulator.

 The result is stored in accumulator.  The result is stored in accumulator.

 All flags are modified to reflect the result of subtraction.  All flags are modified to reflect the result of subtraction.

 Example: SUI 45 H  Example: SBI 45 H

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Arithmetic Instructions Arithmetic Instructions

Opcode Operand Description Opcode Operand Description

INR R Increment register or memory by 1 INX R Increment register pair by 1
M

 The contents of register or memory location are incremented  The contents of register pair are incremented by 1.
by 1.
 The result is stored in the same place.
 The result is stored in the same place.

 If the operand is a memory location, its address is specified by  Example: INX H

the contents of H-L pair.

 Example: INR B or INR M

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Arithmetic Instructions Arithmetic Instructions

Opcode Operand Description Opcode Operand Description

DCR R Decrement register or memory by 1 DCX R Decrement register pair by 1
M

 The contents of register or memory location are decremented  The contents of register pair are decremented by 1.
by 1.
 The result is stored in the same place.
 The result is stored in the same place.

 If the operand is a memory location, its address is specified by  Example: DCX H

the contents of H-L pair.

 Example: DCR B or DCR M

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Logical Instructions AND, OR, XOR

• These instructions perform logical operations on data stored in • Any 8-bit data, or the contents of register, or memory location can
registers, memory and status flags. logically have

• AND operation
• The logical operations are:
• OR operation
• AND
• OR • XOR operation
• XOR
with the contents of accumulator.
• Rotate
• Compare • The result is stored in accumulator.
• Complement

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Rotate Compare

• Each bit in the accumulator can be shifted either left or right to the • Any 8-bit data, or the contents of register, or memory location can be
next position. compares for:

• Equality

• Greater Than

• Less Than

with the contents of accumulator.

• The result is reflected in status flags.

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Complement Logical Instructions

• The contents of accumulator can be complemented. Opcode Operand Description

CMP R Compare register or memory with accumulator
• Each 0 is replaced by 1 and each 1 is replaced by 0. M

 The contents of the operand (register or memory) are

compared with the contents of the accumulator.

 Both contents are preserved .

 The result of the comparison is shown by setting the

flags of the PSW as follows:

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Logical Instructions Logical Instructions

Opcode Operand Description Opcode Operand Description

CMP R Compare register or memory with accumulator CPI 8-bit data Compare immediate with accumulator
M

 if (A) < (reg/mem): carry flag is set  The 8-bit data is compared with the contents of
accumulator.
 if (A) = (reg/mem): zero flag is set
 The values being compared remain unchanged.
 if (A) > (reg/mem): carry and zero flags are reset.
 The result of the comparison is shown by setting the
 Example: CMP B or CMP M flags of the PSW as follows:

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Logical Instructions Logical Instructions

Opcode Operand Description Opcode Operand Description

CPI 8-bit data Compare immediate with accumulator ANA R Logical AND register or memory with
M accumulator

 if (A) < data: carry flag is set  The contents of the accumulator are logically ANDed with the contents of
register or memory.

 if (A) = data: zero flag is set  The result is placed in the accumulator.
 If the operand is a memory location, its address is specified by the contents
 if (A) > data: carry and zero flags are reset of H-L pair.
 S, Z, P are modified to reflect the result of the operation.
 Example: CPI 89H  CY is reset and AC is set.
 Example: ANA B or ANA M.

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Logical Instructions Logical Instructions

Opcode Operand Description Opcode Operand Description

ANI 8-bit data Logical AND immediate with accumulator XRA R Exclusive OR register or memory with
M accumulator

 The contents of the accumulator are logically ANDed with the  The contents of the accumulator are XORed with the contents of the register or memory.

8-bit data.  The result is placed in the accumulator.

 The result is placed in the accumulator.  If the operand is a memory location, its address is specified by the contents of H-L pair.

 S, Z, P are modified to reflect the result.  S, Z, P are modified to reflect the result of the operation.

 CY and AC are reset.

 CY is reset, AC is set.
 Example: XRA B or XRA M.
 Example: ANI 86H.

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Logical Instructions Logical Instructions

Opcode Operand Description Opcode Operand Description

ORA R Logical OR register or memory with ORI 8-bit data Logical OR immediate with accumulator
M accumulator

 The contents of the accumulator are logically ORed with the contents of the register or  The contents of the accumulator are logically ORed with the 8-
memory.
bit data.
 The result is placed in the accumulator.
 The result is placed in the accumulator.
 If the operand is a memory location, its address is specified by the contents of H-L pair.
 S, Z, P are modified to reflect the result.
 S, Z, P are modified to reflect the result.

 CY and AC are reset.  CY and AC are reset.

 Example: ORA B or ORA M.  Example: ORI 86H.

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Logical Instructions Logical Instructions

Opcode Operand Description Opcode Operand Description

XRA R Logical XOR register or memory with XRI 8-bit data XOR immediate with accumulator
M accumulator

 The contents of the accumulator are XORed with the contents of the  The contents of the accumulator are XORed with the
register or memory.
8-bit data.
 The result is placed in the accumulator.
 If the operand is a memory location, its address is specified by the  The result is placed in the accumulator.
contents of H-L pair.
 S, Z, P are modified to reflect the result.
 S, Z, P are modified to reflect the result of the operation.
 CY and AC are reset.  CY and AC are reset.
 Example: XRA B or XRA M.  Example: XRI 86H.

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Logical Instructions Logical Instructions

Opcode Operand Description Opcode Operand Description

RLC None Rotate accumulator left RRC None Rotate accumulator right

 Each binary bit of the accumulator is rotated left by one  Each binary bit of the accumulator is rotated right by one
position. position.
 Bit D7 is placed in the position of D0 as well as in the Carry  Bit D0 is placed in the position of D7 as well as in the Carry
flag. flag.
 CY is modified according to bit D7.  CY is modified according to bit D0.
 S, Z, P, AC are not affected.  S, Z, P, AC are not affected.
 Example: RLC.  Example: RRC.

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Logical Instructions Logical Instructions

Opcode Operand Description Opcode Operand Description

RAL None Rotate accumulator left through carry RAR None Rotate accumulator right through carry

 Each binary bit of the accumulator is rotated left by one  Each binary bit of the accumulator is rotated right by one
position through the Carry flag. position through the Carry flag.
 Bit D7 is placed in the Carry flag, and the Carry flag is placed in  Bit D0 is placed in the Carry flag, and the Carry flag is placed in
the least significant position D0. the most significant position D7.
 CY is modified according to bit D7.  CY is modified according to bit D0.
 S, Z, P, AC are not affected.  S, Z, P, AC are not affected.
 Example: RAL.  Example: RAR.

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Logical Instructions Logical Instructions

Opcode Operand Description Opcode Operand Description

CMA None Complement accumulator CMC None Complement carry

 The contents of the accumulator are complemented.  The Carry flag is complemented.

 No flags are affected.  No other flags are affected.

 Example: CMA.  Example: CMC.

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Logical Instructions Branching Instructions

Opcode Operand Description • The branching instruction alter the normal sequential flow.
STC None Set carry
• These instructions alter either unconditionally or conditionally.

 The Carry flag is set to 1.

 No other flags are affected.

 Example: STC.

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Branching Instructions Branching Instructions

Opcode Operand Description Opcode Operand Description

JMP 16-bit address Jump unconditionally Jx 16-bit address Jump conditionally

 The program sequence is transferred to the memory  The program sequence is transferred to the memory
location specified by the 16-bit address given in the location specified by the 16-bit address given in the
operand. operand based on the specified flag of the PSW.
 Example: JMP 2034 H.  Example: JZ 2034 H.

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Jump Conditionally Branching Instructions

Opcode Description Status Flags Opcode Operand Description

JC Jump if Carry CY = 1 CALL 16-bit address Call unconditionally

JNC Jump if No Carry CY = 0

JP Jump if Positive S=0

 The program sequence is transferred to the memory
JM Jump if Minus S=1 location specified by the 16-bit address given in the
operand.
JZ Jump if Zero Z=1

JNZ Jump if No Zero Z=0  Before the transfer, the address of the next instruction after
CALL (the contents of the program counter) is pushed onto
JPE Jump if Parity Even P=1
the stack.
JPO Jump if Parity Odd P=0
 Example: CALL 2034 H.

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Branching Instructions Call Conditionally

Opcode Operand Description Opcode Description Status Flags

Cx 16-bit address Call conditionally CC Call if Carry CY = 1

CNC Call if No Carry CY = 0

CP Call if Positive S=0

 The program sequence is transferred to the memory
location specified by the 16-bit address given in the CM Call if Minus S=1
operand based on the specified flag of the PSW. CZ Call if Zero Z=1

 Before the transfer, the address of the next instruction CNZ Call if No Zero Z=0
after the call (the contents of the program counter) is CPE Call if Parity Even P=1
pushed onto the stack.
CPO Call if Parity Odd P=0
 Example: CZ 2034 H.

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Branching Instructions Branching Instructions

Opcode Operand Description Opcode Operand Description

RET None Return unconditionally Rx None Call conditionally

 The program sequence is transferred from the  The program sequence is transferred from the
subroutine to the calling program. subroutine to the calling program based on the
specified flag of the PSW.
 The two bytes from the top of the stack are copied into
 The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the program counter, and program execution begins at
the new address. the new address.
 Example: RET.  Example: RZ.

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Return Conditionally Branching Instructions

Opcode Description Status Flags Opcode Operand Description

RC Return if Carry CY = 1 RST 0–7 Restart (Software Interrupts)

RNC Return if No Carry CY = 0

RP Return if Positive S=0

 The RST instruction jumps the control to one of eight
RM Return if Minus S=1 memory locations depending upon the number.
RZ Return if Zero Z=1
 These are used as software instructions in a program to
RNZ Return if No Zero Z=0
transfer program execution to one of the eight
RPE Return if Parity Even P=1
locations.
RPO Return if Parity Odd P=0
 Example: RST 3.

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Restart Address Table Control Instructions

Instructions Restart Address • The control instructions control the operation of microprocessor.
RST 0 0000 H

RST 1 0008 H

RST 2 0010 H

RST 3 0018 H

RST 4 0020 H

RST 5 0028 H

RST 6 0030 H

RST 7 0038 H

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Control Instructions Control Instructions

Opcode Operand Description Opcode Operand Description

NOP None No operation HLT None Halt

 No operation is performed.  The CPU finishes executing the current instruction

and halts any further execution.
 The instruction is fetched and decoded but no
operation is executed.  An interrupt or reset is necessary to exit from the halt
state.
 Example: NOP
 Example: HLT

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Control Instructions Control Instructions

Opcode Operand Description Opcode Operand Description

DI None Disable interrupt EI None Enable interrupt

 The interrupt enable flip-flop is reset and all the  The interrupt enable flip-flop is set and all interrupts
interrupts except the TRAP are disabled. are enabled.

 No flags are affected.  No flags are affected.

 Example: DI  This instruction is necessary to re-enable the

interrupts (except TRAP).
 Example: EI

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Control Instructions RIM Instruction

Opcode Operand Description

RIM None Read Interrupt Mask

 This is a multipurpose instruction used to read the

status of interrupts 7.5, 6.5, 5.5 and read serial data
input bit.
 The instruction loads eight bits in the accumulator
with the following interpretations.
 Example: RIM

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Control Instructions SIM Instruction

Opcode Operand Description

SIM None Set Interrupt Mask

 This is a multipurpose instruction and used to

implement the 8085 interrupts 7.5, 6.5, 5.5, and serial
data output.
 The instruction interprets the accumulator contents as
follows.
 Example: SIM

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