AN INTERNSHIP

REPORT ON

VERY LARGE-SCALE INTERATION

submitted to

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY OF KAKINADA

In Partial Fulfilment for the Award of the Degree of

BA CHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

BY

K. MANOHAR - 22MC5A0422

Under the esteemed guidance of

Sk. John Sydha MTech (PhD)
Assistant Professor

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
RK COLLEGE OF ENGINEERING
(Approved by AICTE, New Delhi and Affiliated to JNTUK, Kakinada)
(Accredited by NAAC “A” Grade with Autonomous)
Kethanakonda (V), Ibrahimpatnam (M), Vijayawada, Amaravati – 521456

2021-2025
 DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE
This is to certify that the Internship report entitled “VLSI” a Bonafide
record work carried out by K. MANOHAR (22MC5A0422) IV B-Tech II
Semester Electronics and Communication Engineering under the
guidance of SK John Sydha M. Tech (PhD) during academic year of 2024-
2025. The results of investigation enclosed in this report have been verified
and found to be satisfactory.

INTERNSHIP GUIDE HOD

EXTERNAL EXAMINER
 ACKNOWLEDGEMENT

I sincerely salute our esteemed institution, RK COLLEGE OF ENGINEERING, Kethanakonda,

Approved and affiliated to Jawaharlal Nehru Technological University, Kakinada for giving this golden
opportunity for fulfilling our warm dreams in Bachelor of Technology form Electronics and
Communication Engineering.

We express our heartfelt gratitude and deep indebtedness to our Founder & chairman Sri M.
M. KONDAIAH Garu, for his great help and encouragement in doing our Internship successfully.

We express our heartfelt gratitude to our Honourable secretary Dr. M.

MAHENDRANADH
Garu, for his encouragement in doing our Internship successfully.

We also express our heartfelt gratitude and wholehearted thanks to our principal
sir Dr. K. RAMA KRISHNAIAH, M.Sc., Ph.D. & M.Tech., Ph.D. MIE, LMISTE & FIETE for his
encouragement and facilities provided during our Internship

We express our heartfelt gratitude to Prof. V.V.G.S. RAJENDRA PRASAD M.

Tech(PhD.), MISTE, and Head of the department of Electronics and Communication
Engineering for his valuable suggestions.

We express our h e a r t f e l t g r a t i t u d e a n d deep indebtedness t o our Internship guide

SK. JOHN SYDHA M. Tech (PhD) and Assistant professor for his valuable guidance and
suggestions.

We express our sincere thanks to the members of our Internship review committee and the entire
faculty of the department for their guidance and cooperation in completing our Internship. We would like
to thank our parents and well-wishers for helping us to complete our Internship smoothly. Thanks to all
those who directly or indirectly helped us to complete this Internship work.

K. MANOHAR 22MC5A0422
 DECLARATION
I are the members of the Internship entitled with “VLSI” here by “declared that

matter embodies in this Internship is a genuine work done by us and has not

been submitted to any other university for the fulfilment of the requirement

of any course of study.

K. MANOHAR
 CONTENT
TITLE PAGE.NO

CHAPTER 1: EXECUTIVE SUMMARY………………………………..1

CHAPTER 2: OVERVIEW OF THE ORGANIZATION 2-9

2.1 Introduction of the organization 2

2.2 Vision, Mission of the Organization 8

2.3 Values of the Organization 9

CHAPTER 3: INTERNSHIP PART……………………………………………. 10-63

3.1 Internship and its importance 10

3.2 Internship Responsibilities 11

3.3 Skills acquired during internship 12

3.4 VERILOG 13
CHAPTER 4…………………………………………………………………………….64-88
Activity log for the first week 64
Weekly report 1 65
Activity log for the second week 66
Weekly report 2 67
Activity log for the third week 68
Weekly report 3 69
Activity log for the fourth week 70
weekly report 4 71
Activity log for the fifth week 72
weekly report 5 73
Activity log for the sixth week 74
weekly report 6 75
Activity log for the seventh week 76
weekly report 7 77
Activity log for the 8th week 79
weekly report 8 80
Activity log for the 9th week 81
 weekly report 9 82
Activity log for the 10th week 83
weekly report10 84
Activity log for the 11th week 85
weekly report11 86
Activity log for the 12th week 87
weekly report 12 88

CHAPTER 5: OUTCOMES DESCRIPTION………………………….89-94

5.1 Course Outcomes 89
5.2 Real time technical skills acquired 90
5.3 Managerial skills acquired 91
5.4 Improvement of Communication skills 92
5.5 Technology Development 94
Student Self Evaluation 95
Evaluation by Supervisor 96
Evaluation 97

INTERNAL ASSESSMENT STATEMENT…………………………………….100

 VLSI

CHAPTER 1

EXECUTIVE SUMMARY

Naresh Technologies & Consultancy Services is a Training and

Consultancy Services that provides internship resources and career services to
students and employers. The platform offers internship searching and posting
services as well as many other career services such as counselling, cover-letter
writing, resume building, and training programs to students.

Naresh Technologies & Consultancy Services is a startup company. we

are a technology company on a mission to equip students with relevant skills
and practical exposure to help them get the best possible start to their careers.
Imagine a world full of freedom and possibilities.

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CHAPTER 2:
OVERVIEW OF THE ORGANIZATION
2.1 INTRODUCTION OF THE ORGANIZATION

Naresh Technologies & Consultancy Services is a training and consultancy

firm, it can be assumed that they provide services related to education,
training, and consulting. Typically, such organizations offer a range of services
to individuals and businesses, including:
Training Services:

2 Technical Training: This could include courses related to information

technology, programming languages, software development, data science, etc.

3 Soft Skills Training: Training in communication, leadership, teamwork, and

other interpersonal skills is often provided for professional development.

4 Certification Programs: Preparation courses for various industry

certifications, which are essential for career growth in many fields.

5 Customized Training: Tailored training programs designed specifically for

businesses or organizations to enhance the skills of their employees.

Consultancy Services:

• IT Consultancy: Advising businesses on how to use information technology to

meet their objectives or overcome problems.

• Business Process Optimization: Analysing and optimizing existing business

processes to improve efficiency and reduce costs.

• Data Analysis and Interpretation: Helping businesses make sense of data,

providing insights that can be used for strategic decision-making.

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• Project Management: Providing expertise in managing projects, ensuring they

are completed on time and within budget.

1. Cybersecurity Consultancy: Advising businesses on how to protect their

digital assets from cyber threats and attacks.

Introduction:

Naresh Technologies & Consultancy Services is a leading organization

specializing in comprehensive
training and consultancy services. With a team of experienced professionals
and experts in various fields, we are committed to empowering individuals and
businesses with the knowledge and skills needed to thrive in today's
competitive world.

Our Training Services:

At Naresh Technologies & Consultancy Services, we offer a diverse range of

training programs, from technical courses covering the latest programming
languages and technologies to soft skills development, ensuring that our clients
are well-equipped to meet the challenges of the modern workforce.

Our Consultancy Services:

In addition to our training programs, we provide strategic consultancy services
to businesses of all sizes. Our experts work closely with clients to understand
their unique needs and challenges, offering tailored solutions in areas such as
IT consultancy, business process optimization, data analysis, project
management, and cybersecurity.

Why Choose Us:

5 Expert Trainers: Our trainers are industry experts with years of practical

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experience, ensuring the highest quality of education.

6 Customized Solutions: We understand that every business is unique. That's

why we provide customized training and consultancy services to meet specific
requirements.

Cutting-Edge Curriculum: Our training programs are constantly updated to

reflect the latest industry trends and technologies, keeping our clients ahead of
the curve.

7 Client-Centric Approach: We prioritize client satisfaction, focusing on delivering

exceptional services that add tangible value to individuals and organizations.

Whether you're an individual looking to enhance your skills or a business

seeking strategic guidance, Naresh Technologies & Consultancy Services is
your trusted partner for success. Contact us today to explore how we can help
you achieve your goals.

Organizational Structure

Naresh Technologies & Consultancy Services might have a structure that

includes various departments such as:

3 Executive Leadership: This includes top executives such as the CEO (Chief
Executive Officer), CFO (Chief Financial Officer), and other C-level executives
who are responsible for the overall direction of the company.

4 Departments: Different departments within the organization might include IT

Services, Consultancy, Training, Sales and Marketing, Human Resources,
Finance, and Administration.

5 Managers and Team Leaders: Each department may have managers or team
leaders who oversee specific teams or projects.

6 Employees: These are the professionals working within the various

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departments, including consultants, trainers, IT specialists, and administrative

staff.

7 Support Staff: This includes roles such as receptionists, administrative

assistants, and other support personnel who help in the day-to-day functioning
of the organization.

1. Clients and Partners: While not part of the internal organizational structure,
clients and partners are integral to the company’s operations. Maintaining
strong relationships with clients and partners is essential for the company's
success.

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Internship Policy at Naresh Technologies & Consultancy Services

At Naresh Technologies & Consultancy Services, we recognize the value of

internships as a bridge between academic learning and professional
experience. Our internship program is designed to provide aspiring
professionals with meaningful opportunities to learn, grow, and contribute
within our organization. To ensure a mutually beneficial experience for both
our interns and the organization, we have established the following policies:

**1. ** Equal Opportunity: We are committed to providing equal opportunities

to all interns, regardless of their background, ethnicity, gender, or any other
characteristic. Selections are made based on merit and the potential to
contribute effectively to our organization.

**2. ** Learning and Development: Interns at Naresh Technologies &

Consultancy Services are considered valuable members of our team. We
provide a supportive environment where interns can
enhance their skills, gain practical experience, and participate in real projects under
the guidance of experienced professionals.

**3. ** Mentorship: Each intern is assigned a mentor who will guide and
support them throughout their internship. Our mentors are experienced
professionals who provide valuable insights, feedback, and encouragement to
help interns succeed in their roles.

**4. ** Professional Conduct: We expect interns to adhere to the same

professional standards as our full-time employees. This includes punctuality,
respect for colleagues, clients, and company property, and maintaining
confidentiality on sensitive matters.

**5. ** Project Involvement: Interns will be involved in meaningful projects

that align with their skills and interests. These projects are carefully chosen to
p

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rovide a learning experience while also contributing to the organization's goals.

**6. ** Feedback and Evaluation: Regular feedback sessions will be conducted
to assess the intern's performance and provide constructive guidance for
improvement. Successful completion of the internship may lead to a certificate
of achievement and a potential opportunity for future collaboration.

**7. ** Confidentiality: Interns will have access to sensitive information and

are expected to maintain strict confidentiality about the company's operations,
clients, and projects, both during and after their internship.

**8. ** Duration and Schedule: The duration and schedule of the internship
will be clearly defined at the beginning of the program. Any changes to the
schedule should be communicated and agreed upon in advance.

**9. ** Conclusion of Internship: At the end of the internship, interns are

expected to return any company property and materials and complete an exit
interview to provide feedback about their experience.

Future Plans:

1. Diversification of Services: The company could expand its range of services to

cater to a broader clientele. This might include offering new training programs,
specialized consultancy services, or venturing into emerging technology
sectors.

2. Global Expansion: Naresh Technologies & Consultancy Services might

consider expanding its operations internationally, tapping into new markets
and establishing a global presence. This expansion could involve opening
offices in different countries or forming strategic partnerships with
international organizations.

3. Digital Transformation: Embracing digital technologies internally can

enhance efficiency. This might involve implementing advanced project
management software, data analytics tools, or customer relationship
m

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anagement (CRM) systems.

4. Focus on Emerging Technologies: Staying ahead of the curve in terms of

technological advancements is crucial. The company could focus on emerging

technologies such as artificial intelligence, blockchain, cybersecurity, or
Internet o of Things (IoT), offering specialized services and training programs
in these areas.

5. Partnerships and Collaborations: Collaborating with universities, research

institutions, or other businesses can foster innovation. Partnerships can lead
to joint research projects, access to new talent pools, and the development of
cutting-edge solutions.

6. Quality Assurance and Certifications: Obtaining industry certifications and

quality assurance standards can enhance the company’s reputation.
Certifications in specific technologies or consultancy methodologies can instill
trust in clients and partners.

7. Corporate Social Responsibility (CSR): Engaging in CSR activities not only

benefits society but also enhances the company’s image. This could include
supporting education initiatives, environmental conservation, or community
development projects.

8. Talent Development: Investing in the continuous development of employees

through training, workshops, and skill enhancement programs can ensure that
the company always has a skilled workforce ready to tackle new challenges.

9. Client Relationship Management: Strengthening relationships with existing

clients through excellent service and personalized attention can lead to
longterm partnerships and repeat business.

2
.2

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Vision, Mission and Values of the Organization :

2.2.1 Vision:
To be a leading catalyst for talent development and empowerment, transforming
lives and communities across India.

To empower a billion aspirations by unlocking human potential, fostering

inclusive growth, and creating a vibrant ecosystem of talent, innovation, and
entrepreneurship.

2.2.2 Mission
To identify, nurture, and showcase talent from diverse backgrounds, providing
opportunities for education, skill development, and employment, thereby
fostering socio-economic growth and inclusivity.

To discover, nurture, and showcase talent, providing access to quality

education, skill development, and employment opportunities, thereby
transforming lives and communities.

VALUES :
Core Values of Naresh Technologies Institute:
1. Quality Education: Committed to delivering industry-oriented, high-quality
training in IT and software development through experienced faculty and realtime
project-based learning.
2. Practical Learning Approach :Focus on hands-on learning and real-time project
experience to ensure students are job-ready and skilled in current technologies.
3. Student-Centric Environment :Providing a supportive and engaging learning
environment that caters to the individual growth and development of each
student.
4. Industry Relevance :Curriculum and training programs are regularly updated to
match current industry trends and demands, ensuring students stay ahead.
5. Discipline and Professionalism :Encouraging punctuality, responsibility, and
pr

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ofessional behavior both in learning and future workplace environments.

6. Affordability and Accessibility :Striving to make quality technical education
accessible to a broad audience with cost-effective courses and flexible learning
options.
7. Integrity and Ethics : Upholding transparency, honesty, and ethical conduct in all
academic and professional dealings.
8. Career Support and Guidance :Providing career counseling, resume building, and
placement assistance to help students achieve their career goals.
9. Innovation and Continuous Improvement :Promoting a culture of innovation,
creativity, and constant improvement among students and trainers alike.
10. Community and Collaboration :Fostering collaboration among students,
alumni, and industry professionals to build a strong tech-learning community.

CHAPTER-3 INTERNSHIP PART

The decision was taken under the National Education Policy (NEP)2020.New
guidelines from the University Grants Commission (UGC) students in recognized
Indian universities will have to compulsorily do research internship for eight to
ten weeks. The decision was taken after it was announced under NEP 2020that
internships will now be promote handmade compulsory. These internship
program primarily at the employability of students and to help develop research
capabilities in students.
The Govt. of Andhra Pradesh, Higher Education Department has introduced
Skills and Skill Development courses along with three mandatory internships
during their graduation. The Andhra Pradesh State Council of Higher education
has given the instructions to all the colleges and universities. Hence, the
internship is mandatory for the undergraduate students. The Commissioner of
the Collegiate Education and concerned universities are the implementing
authorities. Here I am going to explain the internship, Firstly I selected the
domain of Embedded Systems, Attended the online classes, Follow the material
ls for the preparation of the modules. I have successfully completed the
M

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odules of the domain and what kind of skills I acquired etc., already is cussing
in this chapter.

3.1 Internship and Its Importance

An internship is a period of work experience offered by the organization for
ultimate period of time. Once confined to graduates, internship is used practice
for a wide range of placements in businesses, non-profit organizations and
government agencies. They are typically undertaken by students and graduates
looking to gain relevant skills and experience in a particular field. The students
will get benefit from these placements because they often recruit employees
from their best interns, who have known capabilities, thus saving time and
money in the long run.

In addition, an internship can be used to build a professional network that can

assist with letters of recommendation or lead to future employment
opportunities. The benefit of bringing an intern into full time employment is
that they are already familiar with the company, there for to no training.
Internships provide current college students with the ability to participate in a
field of their choice to receive hands-on learning about a particular future
career, preparing them for full-time work following graduation.

Companies in search of interns often find and place student sin mostly
unpaid internships, for a fee. These companies charge students to assist wither
search, promising to refund the fee if no internship is found. The programs vary
and aim to provide internship placement sat companies. Some companies may
also provide controlled housing in a city, mentorship, support, networking,
weekend activities or academic credit. Some program so extra add-ons such as
languages classes, networking events, local excursions, and academic options.

Some companies specifically fund scholarships and grants for lowincome

applicants. Critics of internship criticize the practice of requiring certain
accountable by their academic institution. For example, a student may be
awarded academic credit only after their university receives a positive review
f

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rom the intern’s super or at the sponsoring organization.

3.2 Internship Responsibilities

• VLSI Architect responsibilities include designing and Implementing software of
embedded devices and systems.

• Review and design code, integrate and validate new product designs, and

• Develop system software from design through debugging.

• Attending the online classes on time.

• Performing research on the basic concepts.

• Designing, Debugging, Developing, Testing.

• Knowledge of programming languages such as Verilog.

• Knowledge of hardware components like Microprocessors, Memory

• Power supplies, communication systems.

3.3 Skills Acquired during Internship

While getting an internship is one part of the internship process, it is
complete only when grasp the relevant skills through my experience. I will get to
learn a lot of technical skills. Softs kills are basic necessity to become a
professional. Learned Basic knowledge in VLSI.
• It teaches us show to design a circuit using different microcontrollers.
• I have learned how to write a code using C in VLSI.
• Learned how to interface various components.

• It improved bugging skills.

• Understanding of design patterns and VLSI system design patterns.

Others kills acquired:

• Communication skills.

• Critical thinking.

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esearch and Analysis.

• Capability to learn in situations that are outside of their comfort zone

• Patience

• Team work

• Abilities in problem solving and the generation of new ideas for answers.

3.4 VERILOG

Verilog is a Hardware Description Language (HDL) used for designing and

modeling digital circuits. It allows engineers to describe hardware behavior at
various abstraction levels, from simple gates to complex systems like
processors. Verilog is widely used in FPGA and ASIC design.

Features

I. Supports different modeling styles (Structural, Behavioral, Dataflow)

II. Used for simulation and synthesis of digital circuits

III. Similar to programming languages like C but focuses on hardware modeling

History

I. Developed in 1G84 by Phil Moorby and Prabhu Goel at Gateway Design

Automation.

II. Acquired by Cadence Design Systems in 1990.

III. Standardized as IEEE 1364 in 1995 and later improved in 2001 and 2005.

IV. Replaced by SystemVerilog (IEEE 1800), but still widely used in industry.

Importance

Verilog enables efficient hardware design through:

I. Fast Prototyping – Quickly test designs using simulation tools.

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II. RTL Design – Used in Register Transfer Level (RTL) abstraction.

III. FPGA s ASIC Implementation – Used in chip fabrication.

IV. Verification s Debugging – Helps identify design flaws before manufacturing.

Basics of Digital Design

Before diving into Verilog, it's important to understand basic digital circuit concepts:

I. Logic Gates (AND, OR, NOT, NAND, NOR, XOR)

II. Combinational Circuits (Multiplexers, Decoders, Encoders)

III. Sequential Circuits (Flip-Flops, Registers, Counters)

Example:

module and_gate( input A, input B, output

Y) assign Y = A & B; endmodule

Testbench for AND Gate

module testbench; reg A, B; wire Y;

and_gate uut (A, B, Y); initial begin
$monitor("A = %b, B = %b, Y = %b", A, B, Y);

A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1;
#10; $finish; end
endmodule

Explanation
I. assign is used for continuous assignment in combinational logic.

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II. #10; represents a 10-time unit delay between test cases.

III. $monitor prints values whenever they change.

Example: module and_gate( input A,

input B, output Y); assign Y = A & B;

endmodule

• module defines the module name (and_gate).

• input and output define ports.

• assign is used for combinational logic.

• endmodule marks the end of the module.

Syntax
A Verilog module follows this syntax:
module <module_name> (input/output ports);
// Internal signals (if needed)

// Combinational or Sequential logic endmodule

Example: 2-to-1 Multiplexer (MUX)

module mux2to1 ( input A, input B, input sel,
output Y); assign Y = sel ? B : A; // If sel=1, Y=B; else, Y=A
endmodule

Testbench for 2:1 MUX

module testbench; reg A, B, sel; wire Y;
mux2to1 uut (A, B, sel, Y); initial begin
$monitor("A = %b, B = %b, sel = %b, Y = %b", A, B, sel, Y);
A = 0; B = 1; sel = 0; #10;
A

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= 0; B = 1; sel = 1; #10;
A = 1; B = 0; sel = 0; #10;

A = 1; B = 0; sel = 1; #10;
$finish;
end
endmodule

Simulation && Synthesis

I. Simulation
• Used to test and verify the behavior of the design before hardware implementation.

• Involves testbenches and waveform analysis.

• Does not consider hardware constraints.

II. Synthesis
• Converts Verilog code into a hardware circuit (gates, flip-flops, etc.).

• Used to generate netlists for FPGA and ASIC designs.

• Requires synthesizable coding techniques.

Example:
Behavioral code is valid for simulation but may not be synthesizable:
always @(A or B)
Y = A & B; // May work in simulation but is not always
synthesizable For synthesis, we must ensure hardware representation:
assign Y = A & B; // Synthesis-friendly combinational logic

Full Adder in Verilog

A full adder adds two bits along with a carry-in and produces a sum and
carryout.

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module full_adder ( input

A, input B, input Cin,
output Sum, output Cout
);
assign Sum = A ^ B ^ Cin; assign Cout = (A
& B) | (B & Cin) | (A & Cin); endmodule

Testbench for Full Adder module testbench;

reg A, B, Cin; wire Sum, Cout; full_adder uut (A, B,
Cin, Sum, Cout); initial begin
$monitor("A = %b, B = %b, Cin = %b | Sum = %b, Cout = %b", A,

B, Cin, Sum, Cout);

A = 0; B = 0; Cin = 0; #10;
A = 0; B = 0; Cin = 1; #10;
A = 0; B = 1; Cin = 0; #10;
A = 0; B = 1; Cin = 1; #10;
A = 1; B = 0; Cin = 0; #10;
A = 1; B = 0; Cin = 1; #10;
A = 1; B = 1; Cin = 0; #10;
A = 1; B = 1; Cin = 1; #10;
$finish;
end
endmodule

D Flip-Flop module
d_flip_flop ( input D, input clk,
output reg Q); always

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@(posedge clk) Q <= D;

endmodule

Testbench for D Flip-Flop module testbench; reg D, clk; wire

Q; d_flip_flop uut (D, clk, Q); always #5 clk = ~clk; // Clock toggles
every 5 time units initial begin clk = 0; D = 0;
#10; D = 1;

#10; D = 0;
#10; D = 1;

#10; D = 0;
#10;
$finish;
end
endmodule

Data Types and Operators in Verilog

Verilog has a variety of data types, which are used to describe different
hardware elements. Understanding these types is crucial for designing both
combinational and sequential circuits. Data Types in Verilog

1. Nets (wire)

• Represents physical connections between components.

• Cannot hold or store a value; they must be continuously driven by some other
signal.

• Used in combinational circuits and for connecting different modules.

• Typically assigned values using assign statements.

Example: Using wire in a Combinational Circuit
module and_gate ( input A, input B, output wire Y); assign Y =

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A & B; // Continuous assignment using a wire endmodule

2. Registers (reg)

• Represents a storage element (like a D flip-flop or latch).

• Can hold a value across clock cycles.

• Used in sequential circuits and controlled by always blocks.

• Must be updated inside a procedural block (always or initial).

module d_flip_flop ( input D,

input clk, output reg Q
);

always @(posedge

clk) Q <= D;

endmodule

3. Integer (integer)
• Used for loop counters and calculations.

• Cannot be synthesized into hardware but is useful for testbenches.

Example: Using an Integer for
Looping integer i; initial begin for (i =
0; i < 10; i = i + 1) $display("i = %d", i);
end

4. Parameter (parameter)

• A constant value that cannot change during simulation.

• Used for making code reusable and flexible.

Example: Parameterized Adder module adder

#(parameter WIDTH = 4) ( input [WIDTH-1:0] A, input
[

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WIDTH-1:0] B, output [WIDTH-1:0] Sum

);
assign Sum = A + B;
endmodule

Operators

Arithmetic Operators

Operator Description Example

+ Addition A+ B
- Subtraction A-B
* Multiplication A*B
/ Division A/B
% Modulus A% B
Example: Arithmetic Operations

assign Sum = A + B;
assign Diff = A - B; assign
Product = A * B; assign
Remainder = A % B;

Bitwise Operators

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Operator Description Example

& AND A& B
| OR A|B
^ XOR A^ B
~ NOT ~A
Example: Bitwise Operations
assign Out1 = A & B; // AND
assign Out2 = A | B; // OR
assign Out3 = A ^ B; // XOR
assign Out4 = ~A;

Logical Operators

Operator Description Example

&& Logical AND A && B
|| Logical OR A || B
! Logical NOT !A
Example: Logical Operations
assign Result = (A > B) && (B < C); // Logical AND

Shift Operators

Operator Description Example

<< Logical Left Shift A << 2
>> Right Right Shift A >> 2
<<< Arithmetic Left Shift A<<<2

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>>> Arithmetic Right Shift A>>>2

Example: Using Shift Operators

assign ShiftLeft = A << 1; // Multiply by 2 assign ShiftRight = A

>> 1; // Divide by 2

5. Reduction Operators
Reduction operators perform bitwise operations on all bits of a vector.

Operator Description Example

& AND reduction &A
| | |A
^ XOR reduction ^A

Example: Using Reduction Operators

assign and_reduce = &A; // Logical AND of all bits in A
assign or_reduce = |A; // Logical OR of all bits in A assign
xor_reduce = ^A; // Logical XOR of all bits in A

Constants and Parameters in Verilog

I. Constants in Verilog
Verilog allows the use of constants, which are values that do not change during
simulation. These are mainly used for defining fixed values like clock periods,
bus widths, and predefined logic values.

Constants Using parameter

• A parameter is a constant that helps in writing reusable and configurable code.

• Parameters are assigned values at the time of module instantiation.

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Example: Defining a Constant Width for a 4-bit

Adder module adder #(parameter WIDTH = 4) ( input
[WIDTH-1:0] A, input [WIDTH-1:0] B, output [WIDTH-1:0]
Sum); assign Sum = A + B; endmodule

Overriding a Parameter at Instantiation

adder #(.WIDTH(8)) adder_inst (.A(A),.B(B),.Sum(Sum));

• Here, we override the default WIDTH = 4 with WIDTH = 8 at instantiation.

II. Local Parameters (localparam)

• localparam is similar to parameter, but it cannot be overridden at instantiation.
Example: Using localparam module example;
localparam SIZE = 8; // Fixed constant value reg [SIZE-
[1:0] data;

endmodule
Defining Constants Using define

• The define directive allows macro-style constant definitions.

• Used for global constants across multiple files.

Example: Using define

`define DATA_WIDTH 8 module

memory;
reg [`DATA_WIDTH-1:0] mem_data;
endmodule

Procedural vs. Continuous Assignments

Verilog has two types of assignment methods:

Type Description Example

Continuous Used with wire, represents assign Y = A & B;

Assignment combinational logic

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Procedural Used with reg, updates inside always @(posedge clk)

Assignment always block Q <= D;

I. Continuous Assignment

(assign) Works outside of always

blocks.

• Used for combinational logic.

• Only works with wire data type.

Example: Using assign in a Combinational Circuit

module or_gate ( input A, input B, output wire Y);

assign Y = A | B; // Continuous assignment
endmodule

Procedural Assignment (always block)

Used in sequential circuits and complex
logic.

• Works inside always blocks.

• Requires reg data type.

Example: Using always in a Sequential Circuit module d_flip_flop (
input D, input clk, output reg Q); always @(posedge clk) // Triggered on clock
edge Q <= D; // Non-blocking assignment endmodule

Blocking vs. Non-Blocking Assignments

Assignment Sym Used in Execution

Type bol

Blocking = Combinational C Executes immediately, line by

Sequential line

Logic

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Non- <= Sequential Logic Executes in parallel (suitable

Blocking for flip-flops)

Example: Difference Between = and <=

always @(posedge clk) begin

A = B; // Blocking assignment C <=
D; // Non-blocking assignment end

Conditional Statements in Verilog

Conditional statements are used to implement decision-making logic.

if-else Statement

• Used for making decisions inside an always block.

• Similar to C programming language.

Example: Implementing a 2:1 MUX Using if-else
module mux2to1 ( input A, input B, input sel, output reg Y);
always @(*) begin if (sel) Y = B; else
Y = A; end

endmodule case

Statement

• Used for multiplexer-like structures.

• More efficient than multiple if-else statements.

Example: 4:1 Multiplexer Using case module mux4to1 (
input [1:0] sel, input A, B, C, D, output reg Y); always @(*) begin
case (sel)
2'b00: Y = A;
2'b01: Y = B;
2
'b1

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0: Y = C;
2'b11: Y = D; default: Y =
0; endcase

end
endmodule

casez and casex Statements

• casez treats z( high impedance) as a wildcard.

• casex treats x( unknown) as a wildcard.

Example: casez for a Priority Encoder module

priority_encoder ( input [3:0] in, output reg [1:0] out); always @(*)
begin casez (in)
4'b1???: out = 2'b11;
4'b01??: out = 2'b10;
4'b001?: out = 2'b01;
4'b0001: out = 2'b00; default:
out = 2'bxx; endcase end
endmodule

Loops in Verilog

Loops in Verilog are used primarily in testbenches and behavioral

modeling to execute repetitive tasks efficiently. However, loops in Verilog
behave differently compared to software programming languages like C
because they are typically unrolled at compile time for synthesis.

Types of Loops in Verilog

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Loop Type Description Usage

for Executes a block of code for a defined Used for counters and iterative
number of iterations logic

while Executes a block of code while a Used in testbenches for waiting

condition is true conditions

repeat Repeats a block of code a fixed Used for delays and waveform
number of times generation

forever Runs indefinitely Used for clock generation

for Loop
• A for loop is the most commonly used loop in Verilog.

• It requires an initialization, condition, and increment statement.

• Typically used in testbenches and for generating repetitive signals in simulation.

Example: Using a for Loop in a
Testbench module testbench; integer i;
initial begin for (i = 0; i < 8; i = i + 1) begin
$display("Iteration: %d",
i); end end endmodule
Example: for Loop for Register Initialization module
register_array; reg [7:0] registers [0:15]; // 16 registers of 8-bit
width integer i; initial begin for (i = 0; i < 16; i = i + 1)
registers[i] = 8'hFF; // Initialize all registers to 0xFF end
endmodule while Loop

• Runs while the condition is true.

• Unlike for, it does not require an increment statement.

• Used in testbenches for waiting on conditions.

Example: Using while Loop in a
T

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estbench module testbench; integer count;

initial begin count = 0; while (count < 5) begin
$display("Count = %d", count); count = count + 1;

end end
endmodule

repeat Loop

• Executes a block of code a fixed number of times.

• Used when the number of iterations is predetermined.

Example: Using repeat for a Pulse
Signal module pulse_generator; reg clk;
initial begin repeat (10) begin
#5 clk = ~clk; // Toggle clock every 5 time units
end end endmodule forever Loop

• Runs indefinitely until stopped by an external condition.

• Used in clock generation for testbenches.

Example: Clock Generation Using forever
module clock_gen; reg clk; initial begin clk = 0; forever #5
clk = ~clk; // Toggle clock every 5 time units end
endmodule

Example: Counter Using a for Loop

A 4-bit up-counter using a for loop inside a sequential always block.

module up_counter ( input clk, input reset, output
reg [3:0] count); always @(posedge clk or posedge
reset) begin if (reset) count <= 4'b0000; else

count <= count + 1;

end endmodule

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Counters and FSM

Counters and state machines are widely used in digital circuits for timing
operations, control sequencing, and implementing complex digital logic. This
section covers counter designs and finite state machines (FSMs) using loops and
conditional statements.
Counters in Verilog
Counters are sequential circuits that increment or decrement values based on
clock pulses.

Simple 4-bit Up Counter

A 4-bit up counter increments its value on every positive clock edge.

Code: 4-bit Up Counter module
up_counter ( input clk, input reset, output reg
[3:0] count); always @(posedge clk or posedge
reset) begin
if (reset)
count <= 4'b0000; // Reset the counter to 0 else count <=
count + 1; // Increment count on each clock cycle end
endmodule

4-bit Down Counter

A down counter decrements its value on every clock cycle.

Code: 4-bit Down Counter
module down_counter ( input clk,
input reset,

output reg [3:0] count); always @(posedge clk or

posedge reset) begin if (reset) count <= 4'b1111; //
Reset to max value (15) else
count <= count - 1; // Decrement count
e

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nd endmodule

1. Modulo-N Counter (Using a Loop)

A Modulo-N counter counts from 0 to N-1 and then resets.
Code: Mod-10 Counter (Counts 0 to 3)
module mod10_counter ( input clk,
input reset, output reg [3:0] count); always
@(posedge clk or posedge reset) begin if (reset) count
<= 4'b0000; else if (count == 9)
count <= 4'b0000; // Reset when count reaches 9 else
count <= count + 1;
end endmodule

2. Counter Using a for Loop

Instead of writing a long sequence of if-else conditions, we can use a for loop.
Code: Counter with Loop for Initialization
module counter_with_loop; reg [3:0] count; integer
i; initial begin for (i = 0; i < 10; i = i + 1) begin count
= i;
#10;
$display("Count: %d", count);

end

end
endmodule;

FSM
State machines are used for controlling sequential logic in digital design.
They transition between different states based on inputs.

1. Types of FSMs
FSMs can be classified into two types:

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FSM Type Description

Moore FSM Output depends only on the current state
Mealy FSM Output depends on both current state and inputs

2. Example: 3-State Moore FSM

This FSM has three states: S0 → S1 → S2 → S0.
State Encoding
Binary Encoding 2'b00

2'b01

2'b10

Code: 3-State Moore

FSM module moore_fsm (
input clk, input
reset,
output reg [1:0] state
);

parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

always @(posedge clk or posedge reset) begin if
(reset) state <= S0; // Reset to initial state else
begin
case (state)
S0: state <= S1; S1: state <= S2;
S

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2: state <= S0; default: state <=

S0; endcase end end endmodule

3. Example: Mealy FSM for Sequence Detector

A Mealy FSM generates an output based on both state and input.
Code: Detects "101"
Sequence module mealy_fsm (
input clk, input reset, input
in, output reg out
);
typedef enum reg [1:0] {S0, S1, S2} state_t; state_t state;
always @(posedge clk or posedge reset) begin if (reset)
state <= S0; else begin
case (state)
S0: state <= (in) ? S1 : S0; S1: state <= (in) ? S1 :
S2;
S2: begin if (in) begin state <=
S1; out <= 1; // Sequence
detected end
else begin state <= S0; out <= 0;
end end default: state <= S0;
endcase
end end
endmodule

Comparing Moore and Mealy FSMs

Feature Moore FSM Mealy FSM
Output Depends Current State Current State + Inputs
on

Timing More stable (delayed Faster response

response)

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Design Complexity Easier More complex

Level of abstraction

Verilog allows different levels of abstraction for designing digital circuits. The
three primary modeling styles in Verilog are:

I. Structural Modeling – Describes a circuit as an interconnection of logic gates

and components.

II. Dataflow Modeling – Uses Boolean expressions and assign statements to

describe the circuit.

III. Behavioral Modeling – Uses procedural constructs like always blocks, if-
else, and case statements to describe the behavior of a circuit.

IV. Mixed-Level Modeling – A combination of all three modeling styles in a single

design.

Structural Modeling
• Represents a circuit as a collection of interconnected components (gates,
multiplexers, adders, etc.).

• Similar to designing a circuit using a schematic diagram in hardware.

• Uses gate-level primitives (and, or, xor, etc.) and module instantiation for

hierarchy. example

1. Implementing an AND Gate Using Structural

Modeling module and_gate ( input A, input B, output Y);
and U1 (Y, A, B); // Instantiating an AND gate endmodule

2.
A Half Adder performs binary addition of two inputs (A and B) and produces:
• Sum = A B( XOR operation)

• Carry = A & B( AND operation)

Code: Half Adder Using Structural Modeling
module half_adder ( input A,
i

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nput B, output Sum, output Carry); xor G1 (Sum, A, B); // XOR gate for
Sum and G2 (Carry, A, B); // AND gate for Carry endmodule

3.
A Full Adder extends a Half Adder by adding a Carry-in (Cin).
Logic Equations for a Full Adder
• Sum = A B Cin

• Carry-out = (A & B) | (B & Cin) | (A & Cin)

Code: Full Adder Using Half Adders
module full_adder ( input A,
input B, input Cin, output Sum, output Cout);
wire S1, C1, C2;
half_adder HA1 (.A(A), .B(B), .Sum(S1), .Carry(C1));
half_adder HA2 (.A(S1), .B(Cin), .Sum(Sum), .Carry(C2)); or
G1 (Cout, C1, C2); // OR gate for Carry-out endmodule

4.
A Ripple Carry Adder (RCA) connects multiple full adders in sequence to add
multi-bit numbers

Code: 4-bit Ripple Carry Adder

module ripple_carry_adder ( input [3:0]

A, input [3:0] B, input Cin, output [3:0]
Sum, output Cout); wire C1, C2, C3;
full_adder FA1
(.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(C1));
full_adder FA2
(.A(A[1]), .B(B[1]), .Cin(C1), .Sum(Sum[1]), .Cout(C2));
full_adder FA3
(.A(A[2]), .B(B[2]), .Cin(C2), .Sum(Sum[2]), .Cout(C3));
full_adder FA4

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(.A(A[3]), .B(B[3]), .Cin(C3), .Sum(Sum[3]), .Cout(Cout));

endmodule

Advantages and Disadvantages of Structural Modeling

Advantages Disadvantages
Closely resembles hardware design Difficult to write for large designs
Reusable components simplify Debugging is complex compared to
testing behavioral modeling

Accurate timing since it's gate-level Slower simulation than behavioral

modeling

Dataflow Modeling
Dataflow modeling describes circuits using Boolean equations and
continuous assignments (assign). This abstraction level focuses on how
data flows between inputs and outputs rather than individual gates.

• Uses assign statements instead of gate-level components.

• Provides a more compact and readable representation than structural modeling.

• Typically used for combinational logic circuits.

Syntax
assign <output> = <expression>;

• assign is a continuous assignment (executes whenever inputs change).

• <expression> can contain bitwise, logical, arithmetic, and shift operators.

1. AND, OR, XOR, and NOT Gate
module logic_gates ( input A,
input B, output AND_out, output OR_out, output XOR_out, output
NOT_A); assign AND_out = A & B; assign OR_out = A | B; XOR_out = A ^
B; assign NOT_A= ~A; endmodule
A

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half adder performs binary addition and produces a Sum and a Carry output.
Logic Equations
• Sum = A B

• Carry = A & B
Code: Half Adder Using Dataflow module half_adder ( input A, input B,
output Sum, output Carry); assign Sum = A ^ B; // XOR for Sum assign
Carry = A & B; // AND for Carry endmodule

II. Full Adder Using Dataflow Modeling

A full adder adds two bits and a carry-in (Cin), producing a Sum and Carry-out
(Cout).
Logic Equations
• Sum = A B Cin

• Cout = (A & B) | (B & Cin) | (A & Cin)

Code: Full Adder Using Dataflow module
full_adder ( input A, input B, input Cin, output
Sum, output Cout
);
assign Sum = A ^ B ^ Cin; assign Cout = (A
& B) | (B & Cin) | (A & Cin); endmodule

III. 4-bit Ripple Carry Adder Using Dataflow Modeling

A ripple carry adder (RCA) connects multiple full adders in sequence to perform
multi-bit addition.
Code: 4-bit Ripple Carry Adder
(Dataflow) module ripple_carry_adder ( input
[3:0] A, input [3:0] B, input Cin, output [3:0]
Sum, output Cout
);

wire C1, C2, C3;

assign {C1, Sum[0]} = A[0] + B[0] + Cin; assign {C2,
S

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um[1]} = A[1] + B[1] + C1; assign {C3, Sum[2]} = A[2] +

B[2] + C2; assign {Cout, Sum[3]} = A[3] + B[3] + C3;
endmodule

IV. Multiplexer (MUX) Using Dataflow Modeling

1. 2-to-1 Multiplexer (MUX)

A 2:1 MUX selects one of two inputs (A or B) based on a select signal (sel).

Code: 2-to-1 MUX

module mux2to1 ( input A, input B, input sel, output Y);
assign Y = (sel) ? B : A; // Using conditional operator
endmodule

2. 4-to-1 Multiplexer Using Dataflow

A 4:1 MUX selects one of four inputs based on a 2-bit select signal (sel).
Code: 4-to-1 MUX
module mux4to1 ( input [1:0]

sel, input A, B, C, D, output Y);

assign Y = (sel == 2'b00) ? A :

(sel == 2'b01) ? B :
(sel == 2'b10) ? C :
D;

Endmodule

Behavioral Modeling
Behavioral modeling is the highest level of abstraction in Verilog. It
describes how a circuit behaves using procedural statements inside
always or initial blocks, rather than specifying individual logic gates or
Boolean expressions.

•U

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ses always blocks for describing sequential and complex combinational logic.

Includes control flow statements (if-else, case, for, while).

• Enables the description of complex circuits like state machines, counters, and
memory elements.

always Block

The always block is fundamental to behavioral modeling. It executes whenever

the specified signals change.

Syntax
always @(sensitivity_list) begin
// Procedural statements
end

• The sensitivity list determines when the block executes.

• It can be triggered by combinational logic (@(*)) or sequential logic (@(posedge

clk)).

1. 2-to-1 Multiplexer (MUX) Using always Block

module mux2to1
( input A, inputB,
input sel, output reg Y
);
always @(*) begin if
(sel) Y = B; else
Y = A; end
endmodule

2. 4-to-1 Multiplexer (MUX) Using case Statement

module mux4to1 ( input [1:0] sel, input A, B, C, D, output
reg Y); always @(*) begin case (sel)
2

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'b00: Y = A;
2'b01: Y = B;

2'b10: Y = C;
2'b11: Y = D; default: Y =
0; endcase end
endmodule

• The case statement is more efficient than multiple if-else statements for
multiplexer design.

• Always include a default case to avoid undefined outputs.

Sequential circuits depend on clock edges (posedge or negedge). The
always block runs only when the clock or reset signal changes.

1. D Flip-Flop Using Behavioral Modeling

module d_flip_flop ( input D, input clk, input reset,
output reg Q); always @(posedge clk or posedge
reset) begin if (reset) Q <= 0; else

Q <= D; end
endmodule

2. 4-bit Counter Using Behavioral Modeling

module up_counter ( input clk,
input reset, output reg [3:0] count); always @(posedge
clk or posedge reset) begin if (reset) count <=
4'b0000; // Reset counter else
count <= count + 1; // Increment counter
end endmodule

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. 4-bit Up/Down Counter Using if-else module

up_down_counter ( input clk, input reset, input up_down, // 1 for

up, 0 for down output reg [3:0] count
);
always @(posedge clk or posedge reset) begin if (reset)
count <= 4'b0000; else if (up_down)

count <= count + 1; // Up Counter else

count <= count - 1; // Down Counter end
endmodule

4. Finite State Machine (FSM) Using Behavioral Modeling

FSMs control systems where the output depends on previous states.

Example: Traffic Light Controller (FSM)

This FSM cycles between Green → Yellow → Red →
Green. module traffic_light ( input clk, input reset,
output reg [1:0] light);
typedef enum reg [1:0] {GREEN = 2'b00, YELLOW = 2'b01, RED =2'b10} state_t;
state_t state;
always @(posedge clk or posedge reset) begin if (reset) state
<= GREEN; // Start with GREEN light else begin
case (state)
GREEN: state <= YELLOW; YELLOW: state <= RED; RED: state <=
GREEN; default: state <= GREEN; endcase end end
always @(*) begin case (state)
GREEN: light = 2'b00; YELLOW: light = 2'b01; RED: light = 2'b10; default:
light =
2'b00;
endcase end

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endmodule

Modules, Ports, and Hierarchy in Verilog

In Verilog, modules are the fundamental building blocks used to design

digital circuits. A module defines the circuit's inputs, outputs, and

internal functionality. This chapter will cover: Modules and Ports

I. Module
A module in Verilog is similar to a function in programming languages like
C. It encapsulates logic that can be reused and instantiated multiple times
in a design.

A module consists of:

• Module Name – The identifier for the module.

• Port List – Defines inputs and outputs.

• Internal Logic – Defines the behavior using structural, dataflow, or behavioral

modeling.

Syntax
module <module_name> (port_list);
// Internal signals (if needed)
// Circuit functionality

endmodule

Example:

module and_gate ( input A, input B, output

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Y); assign Y = A & B; // AND operation

endmodule example

module port_example ( input wire A, input wire B, output reg Y, inout wire Z);
always @(*) begin
Y = A & B; // Combinational logic
end endmodule

Rules
• Inputs must be type wire( default).

• Outputs can be wire (for combinational logic) or reg (for sequential logic).

• inout ports are used for bidirectional communication, but require tristate
buffers.

Connecting Multiple Modules

I. Instantiating a Module Inside Another Module

To use a module inside another module, we need module instantiation.
Example: Instantiating the and_gate
Module module top_module (
input A, input B, output Y
);
and_gate U1 (.A(A), .B(B), .Y(Y)); // Instantiating and_gate

endmodule

Example:
A Full Adder can be created by instantiating two Half Adders.
Step 1: Half Adder Module
module half_adder ( input A, input
B, output Sum, output Carry
);

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ssign Sum = A ^ B; assign Carry = A & B; endmodule

Step 2: Full Adder Module (Using Two Half Adders)
module full_adder ( input A,
input B, input Cin, output Sum, output Cout
);

wire S1, C1, C2;

half_adder HA1 (.A(A), .B(B), .Sum(S1), .Carry(C1));
half_adder HA2 (.A(S1), .B(Cin), .Sum(Sum), .Carry(C2));
assign Cout = C1 | C2; endmodule

Multi-Bit Adder Using Structural Modeling

A 4-bit Ripple Carry Adder can be built using multiple Full Adder
modules. Code: 4-bit Ripple Carry Adder

module ripple_carry_adder ( input [3:0]

A, input [3:0] B, input Cin, output [3:0]
Sum, output Cout
);
wire C1, C2, C3;
full_adder FA1
(.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(C1));
full_adder FA2
(.A(A[1]), .B(B[1]), .Cin(C1), .Sum(Sum[1]), .Cout(C2));
full_adder FA3
(.A(A[2]), .B(B[2]), .Cin(C2), .Sum(Sum[2]), .Cout(C3));
full_adder FA4
(.A(A[3]), .B(B[3]), .Cin(C3), .Sum(Sum[3]), .Cout(Cout));
endmodule

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Parameterized Modules
Parameterized modules allow designers to create flexible and reusable
Verilog modules by using parameters instead of hardcoded values.

• Helps in defining generic circuits that can work for different bit-widths.

• Avoids duplicate code by modifying a single parameter.

• Useful in designs like multipliers, adders, ALUs, and memory units.

Parameterized Module module example #(parameter

WIDTH = 8) ( input [WIDTH-1:0] A, input [WIDTH-1:0] B, output

[WIDTH-1:0] Y
);
assign Y = A + B; // Simple addition endmodule

Overriding Parameters at Instantiation

A parameterized module can be customized during instantiation by
overriding its default value.
Example: Instantiating the example Module with Different Bit
Widths example #(.WIDTH(4)) adder1 (.A(A), .B(B), .Y(Y)); // 4-bit
Adder example #(.WIDTH(16)) adder2 (.A(A), .B(B), .Y(Y)); // 16-bit
Adder

Example: Parameterized N-bit Adder

Instead of creating multiple 4-bit or 8-bit adders, we design a generic N-bit
adder.
module n_bit_adder #(parameter N = 8) ( input [N-1:0] A,
input [N-1:0] B, output [N-1:0] Sum
);
assign Sum = A + B;
e

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ndmodule

Example:
A N-bit multiplexer selects one of two N-bit inputs based on a select signal (sel).
module mux #(parameter WIDTH = 8) ( input [WIDTH-1:0]
A, input [WIDTH-1:0] B, input sel, output [WIDTH-1:0] Y
);
assign Y = sel ? B : A;
endmodule

Design Hierarchy and Reusability

I. What is Design Hierarchy?

• Large digital systems are designed using hierarchical modules.

• Small modules (e.g., logic gates, adders) are combined to form complex
modules
(e.g., processors).

• This approach makes debugging, simulation, and synthesis easier.

Example:

A 4-bit ALU (Arithmetic Logic Unit) performs operations like addition,

subtraction, AND, OR, XOR.
Step 1: Define an Arithmetic Module module
arithmetic_unit ( input [3:0] A, input [3:0] B, input mode,
// 0 for Add, 1 for Subtract output [3:0] Result
);
assign Result = mode ? (A - B) : (A + B);

endmodule
Step 2: Define a Logic Unit module logic_unit ( input
[

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3:0] A, input [3:0] B, input [1:0] sel, // 00: AND, 01:

OR, 10: XOR, 11: NOT A output reg [3:0] Y
);

always @(*) begin case (sel)

2'b00: Y = A & B;
2'b01: Y = A | B;
2'b10: Y = A ^ B;
2'b11: Y = ~A;

default: Y = 4'b0000; endcase

end endmodule
Step 3: Integrate into a 4-bit ALU module alu ( input [3:0] A,
input [3:0] B, input [2:0] op, // 000: ADD, 001: SUB, 010: AND,
011: OR, 100: XOR, 101: NOT A output reg [3:0] Result
);
wire [3:0] arith_result, logic_result;
arithmetic_unit AU
(.A(A), .B(B), .mode(op[0]), .Result(arith_result));
logic_unit LU (.A(A), .B(B), .sel(op[1:0]),
.Y(logic_result)); always @(*) begin case (op)
3'b000, 3'b001: Result = arith_result; // ADD or SUB

3'b010, 3'b011, 3'b100, 3'b101: Result = logic_result; // Logic

Operations default: Result = 4'b0000;
endcase end endmodule

Testbenches and Simulation in Verilog

Simulation is a crucial part of digital design. Before synthesizing a circuit, we

must verify its functionality using testbenches. A testbench is a special Verilog

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 VLSI

module that generates inputs, observes outputs, and verifies correctness.

Writing a Testbench
A testbench is a self-contained Verilog module that:

1. Generates input stimulus for the design under test (DUT).

2. Observes outputs to check correctness.

3. Uses simulation constructs ($monitor, $display, #delay) to analyze behavior.

4. Does not require input/output ports because it is not synthesized.

Structure of a Testbench
module testbench;

// 1. Declare test signals (reg for inputs, wire for outputs) reg A, B;wire Y;
// 2. Instantiate the Design Under Test (DUT) and_gate uut (.A(A), .B(B),
.Y(Y));
// 3. Generate input stimulus using an initial block initial begin
A = 0; B = 0; #10; // Apply input and wait 10 time units A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;
$finish; // End simulation
End
// 4. Display signal values initial begin
$monitor("Time = %0t | A = %b, B = %b, Y = %b", $time, A, B, Y);
End

End initial and

always Blocks

I. initial Block
• Runs only once at the beginning of the simulation.

•U

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 VLSI

sed to apply stimulus in testbenches.

Example: Applying Test Cases Using initial initial begin
A = 0; B = 0; #10;
A = 1; B = 1; #10;
$finish;
end
always
Block

• Runs continuously whenever its sensitivity list triggers.

• Used for clock generation or repeating patterns.

Example: Generating a Clock Using
always reg clk; initial clk = 0; // Start clock
at 0
always #5 clk = ~clk; // Toggle clock every 5 time units

Timing Control and Delays

#delay Statement

• Introduces a time delay before the next operation.

• Used in testbenches to space out input transitions.

Example: Delaying Input Transitions
A = 1; B = 0; #10; // Waits for 10 time units
A = 0; B = 1; #20; // Waits for 20 time units

@(posedge clk) and @(negedge clk)

• @(posedge clk) → Waits for the next rising edge of clk.

• @(negedge clk) → Waits for the next falling edge of clk. Example:
Synchronizing Inputs to Clock always @(posedge clk) begin
A <= B; end

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 VLSI

Displaying and Monitoring Signals

I. $display Statement
• Prints values once when executed.

• Similar to printf in C.
Example: Using $display
$display("A = %b, B = %b, Y = %b", A, B, Y);
$monitor Statement

• Continuously prints values whenever any of the monitored signals change.

Example: Using $monitor
$monitor("Time = %0t | A = %b, B = %b, Y = %b", $time, A, B, Y);

$dumpfile and $dumpvars

To generate waveforms for GTKWave, use $dumpfile and $dumpvars.

Example: Generating Waveform Output
initial begin

$dumpfile("waveform.vcd"); // VCD (Value Change Dump) file

$dumpvars(0, testbench); // Dumps all variables
End

Putting Everything Together: Full Testbench Example

Example: Testbench for a Full Adder module

testbench; reg A, B, Cin; wire Sum, Cout;
// Instantiate the Full Adder module full_adder uut (.A(A),
.B(B), .Cin(Cin), .Sum(Sum), .Cout(Cout));

// Apply input stimulus initial begin

$dumpfile("full_adder.vcd");
$dumpvars(0, testbench);
A = 0; B = 0; Cin = 0; #10;
A = 0; B = 0; Cin = 1; #10;

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A = 0; B = 1; Cin = 0; #10;
A = 0; B = 1; Cin = 1; #10;

A = 1; B = 0; Cin = 0; #10;
A = 1; B = 0; Cin = 1; #10;
A = 1; B = 1; Cin = 0; #10;
A = 1; B = 1; Cin = 1; #10;
$finish; // End simulation
end

// Monitor outputs initial begin

$monitor("Time = %0t | A = %b, B = %b, Cin = %b | Sum = %b, Cout = %b",
$time, A, B, Cin, Sum, Cout);
end endmodule

Combinational Logic Design in Verilog

Combinational logic circuits are fundamental to digital design. Unlike

sequential circuits, combinational circuits do not have memory and their
output depends only on the current inputs.

Implementing Logic Gates in Verilog

Example: 2-Input Logic Gates in Verilog
module logic_gates ( input A,
input B, output AND_out, output OR_out, output XOR_out, output NOT_A);
assign AND_out = A & B; assign OR_out = A | B; assign XOR_out = A ^ B;
assign NOT_A = ~A; endmodule
Testbench for Logic Gates module
testbench; reg A, B; wire AND_out,
OR_out, XOR_out, NOT_A; logic_gates
uut
(.A(A), .B(B), .AND_out(AND_out), .OR_out(OR_out), .XOR_out(XOR_out),
.NOT_A(NOT_A));
i

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nitial begin
$monitor("A = %b, B = %b, AND = %b, OR = %b, XOR = %b, NOT A
= %b", A, B, AND_out, OR_out, XOR_out, NOT_A);

A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;
$finish;

end
endmodule

Multiplexers and Demultiplexers

I. What is a Multiplexer (MUX)?

A multiplexer (MUX) selects one of multiple inputs and passes it to the

output based on a select signal.

2-to-1 Multiplexer in Verilog

module mux2to1 (input A, input B, input sel, output Y);
assign Y = sel ? B : A; // If sel=1, Y=B; else, Y=A endmodule

4-to-1 Multiplexer Using case module mux4to1 ( input [1:0]

sel, input A, B, C, D, output reg Y); always @(*) begin case (sel)
2'b00: Y = A;
2'b01: Y = B;

2'b10: Y = C; 2'b11:
Y = D; endcase end
endmodule

Encoders and Decoders

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2-to-4 decoder module decoder2to4 ( input [1:0] sel,

output reg [3:0] Y); always @(*) begin case (sel)
2'b00: Y = 4'b0001;
2'b01: Y = 4'b0010;
2'b10: Y = 4'b0100;
2'b11: Y = 4'b1000;
endcase end
endmodule
Encoder
Example: 4-to-2 Encoder module encoder4to2 (
input [3:0] Y, output reg [1:0] sel); always @(*) begin
case (Y)
4'b0001: sel = 2'b00;
4'b0010: sel = 2'b01;
4'b0100: sel = 2'b10;
4'b1000: sel = 2'b11;
default: sel = 2'bxx;
endcase end
endmodule

Arithmetic Logic Unit (ALU)

An ALU (Arithmetic Logic Unit) performs arithmetic and logic operations.

Example: 4-bit ALU in
Verilog module alu ( input

[3:0] A, input [3:0] B,

input [2:0] op, output reg
[3:0] Result
);
always @(*) begin case (op)
3

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'b000: Result = A + B; 3'b001: Result = A - B; 3'b010: Result = A & B;

3'b011: Result = A | B; 3'b100: Result = A ^ B; 3'b101: Result = ~A;
default: Result = 4'b0000; endcase end endmodule

Sequential Logic Design in Verilog

Flip-Flops and Latches

Flip-Flop
A flip-flop is a sequential storage element that stores one bit of data and updates
its state on a clock edge (posedge clk or negedge clk).

Flip-Flop Type Description

D Flip-Flop Stores the value of D on the clock edge
T Flip-Flop Toggles its state on each clock cycle
JK Flip-Flop Can toggle, set, or reset based on inputs
SR Flip-Flop Stores 1 or 0 unless both inputs are 1
(invalid state)

D Flip-Flop in Verilog
A D flip-flop stores the input (D) on the rising edge of the clock.
Code: D Flip-Flop with Asynchronous
Reset module d_flip_flop ( input D, input
clk, input reset, output reg Q
);
always @(posedge clk or posedge
reset) begin if (reset)
Q <= 0; // Reset output to 0 else
Q <= D; // Store D on clock edge end
e

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ndmodule

T Flip-Flop in Verilog
A T flip-flop toggles its state whenever T = 1 on the clock edge.

Code: T Flip-Flop module

t_flip_flop ( input T, input clk,
input reset, output reg Q
);

always @(posedge clk or posedge

reset) begin if (reset) Q <= 0;
else if (T)
Q <= ~Q; // Toggle when T=1 end
endmodule

JK Flip-Flop in Verilog
A JK flip-flop is a universal flip-flop that can be configured as a D, T, or
SR flipflop.
Code: JK Flip-Flop

module jk_flip_flop ( input J,

input K, input clk, input reset, output reg Q
);
always @(posedge clk or posedge reset) begin if
(reset) Q <= 0; else if (J == 0 && K == 0)
Q <= Q; // No change else if (J == 0 && K == 1)
Q <= 0; // Reset else if (J == 1 && K == 0)
Q <= 1; // Set else
Q <= ~Q; // Toggle

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end endmodule

Registers and Counters

Register
A register is a group of multiple flip-flops used to store multi-bit data.

Register Type Description

Shift Register Shifts data left or right on each clock cycle
Parallel Register Stores multiple bits simultaneously
Universal Register Supports both parallel and serial
operations

4-bit Shift Register in Verilog

A shift register moves data left or right on each clock cycle.

Code: 4-bit Shift Register module shift_register (

input clk,nput reset, input serial_in, output reg [3:0] Q

);
always @(posedge clk or posedge reset) begin if (reset)
Q <= 4'b0000;
Else

Q <= {Q[2:0], serial_in};

End

Endmodule

Counters in Verilog
A counter is a register that increments or decrements on clock pulses.
Counter Type Description
Up Counter Increments on every clock cycle

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Down Counter Decrements on every clock cycle

Up/Down Counter Can count both up and down

Code: 4-bit Up Counter module

up_counter ( input clk, input reset,
output reg [3:0] count
);
always @(posedge clk or posedge reset) begin if (reset)
count <= 4'b0000; // Reset to 0 else
count <= count + 1; // Increment
end endmodul

Code: 4-bit Up/Down Counter

module up_down_counter ( input clk, input reset, input mode,

// 1 for up, 0 for down output reg [3:0] count
);
always @(posedge clk or posedge reset) begin if (reset)
count <= 4'b0000; else if (mode)
count <= count + 1; // Up Count else
count <= count - 1; // Down Count end
endmodule

Finite State Machines (FSMs)

Finite State Machines (FSMs) are used to model sequential logic circuits
where the output depends not only on current inputs but also on past
states. They are widely used in digital design for tasks such as traffic light
control, sequence detection, and communication protocols.

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I. Types of FSMs
There are two main types of FSMs in digital design:

FSM Type Output Depends On Example Applications

Moore FSM Only the current state Traffic lights, counters
Mealy FSM Both the current state and inputs Sequence detectors, protocol
controllers

II. Moore FSM

Example: 3-State Counter

A Moore FSM produces outputs based only on its current state.
State Transition Table
Current State Next State Output
S0 (00) S1 (01) 00
S1 (01) S2 (10) 01
S2 (10) S0 (00) 10

code: 3-State Moore

FSM module moore_fsm (
input clk, input
reset,
output reg [1:0] state, output reg
[1:0] out
);
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
always @(posedge clk or posedge reset) begin if
(reset) state <= S0; // Start at state S0 else begin
c

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 VLSI

ase (state)
S0: state <= S1; S1: state <= S2;
S2: state <= S0; default: state <=
S0; endcase end end

// Output logic depends only on the state always

@(*) begin case
(state)

S0: out = 2'b00; S1: out =

2'b01; S2: out = 2'b10; default:
out = 2'b00; endcase end
endmod ule

Mealy FSM

Example: Sequence Detector ("101")

A Mealy FSM produces outputs based on both current state and inputs.

State Transition Table for Detecting "101"

Current State Input (X) Next State Output (Y)

S0 (Start) 1 S1 0
S1 (Got "1") 0 S2 0
S2 (Got "10") 1 S1 1 (Detected "101")
S2 (Else) 0 S0 0

Code: 3-State Mealy FSM for "101" Detection

module mealy_fsm ( input clk, input reset, input X, //

Serial input output reg Y // Output signal
)

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 VLSI

;
typedef enum reg [1:0] {S0, S1, S2} state_t; state_t state;

always @(posedge clk or posedge reset) begin if (reset)

state <= S0; else begin
case (state)
S0: state <= (X) ? S1 : S0; S1: state <= (X) ? S1 :
S2; S2: begin if (X) begin state <= S1;
Y <= 1; // Sequence "101" detected
end else begin state<=S0; Y<=0;
end end endmodule

Memory Design in Verilog

Memory is an essential component of digital systems, used for storing data

and instructions. In Verilog, memory can be designed using register arrays,
RAM, ROM, FIFO, and LIFO structures.

Memory Design Using Verilog

Verilog allows memory modeling using register arrays. Memory elements are
declared using:

reg [DATA_WIDTH-1:0] memory [0:DEPTH-1];

where DATA_WIDTH is the word size and DEPTH is the number of words.

I. Read-Only Memory (ROM) Implementation

A ROM stores predefined values and does not allow writing operations.
C

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 VLSI

ode: 8x4 ROM (8 locations, 4-bit data)

module rom ( input [2:0] address,
output reg [3:0] data
);

always @(*) begin case (address)

3'b000: data = 4'b0001; 3'b001: data = 4'b0010;
3'b010: data = 4'b0011; 3'b011:

data = 4'b0100; 3'b100: data = 4'b0101; 3'b101: data = 4'b0110; 3'b110:

data = 4'b0111; 3'b111: data = 4'b1000; default: data =
4'b0000; endcase end endmodule

Random Access Memory (RAM) Implementation

A RAM module allows both read and write operations.
Code: 8x4 RAM (8 locations, 4-bit data) module
ram ( input clk, input we, // Write Enable
input [2:0] address, input [3:0] data_in,
output reg [3:0] data_out
);
reg [3:0] memory [7:0]; // 8x4 memory

always @(posedge clk) begin if (we)

memory[address] <= data_in; // Write operation else
data_out <= memory[address]; // Read operation
end endmodule

When we = 1, data is written; when we = 0, data is read.

FIFO and LIFO Memory Implementation

I. First-In, First-Out (FIFO) Memory

A FIFO buffer stores data in the order it was received (queue behavior).
Code: FIFO Buffer (4-bit, 8-depth) module fifo
(

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 VLSI

input clk, input reset, input wr_en, input

rd_en,
input [3:0] data_in, output reg [3:0] data_out, output reg full,
output reg empty
);

reg [3:0] memory [7:0]; // 8-depth FIFO reg [2:0] wr_ptr, rd_ptr, count;
always @(posedge clk or posedge reset) begin if (reset) begin wr_ptr <= 0;
rd_ptr <= 0; count <= 0; end else begin if (wr_en && !full) begin
memory[wr_ptr] <= data_in; wr_ptr<= wr_ptr + 1; count <= count + 1; end if
(rd_en && !empty) begin data_out <= memory[rd_ptr]; rd_ptr <= rd_ptr + 1;
counter<=count-1; end end end always@(*)begin

full = (count == 8);

empty= (count == 0);

end endmodule

Last-In, First-Out (LIFO) Memory (Stack)

A LIFO (stack) works on a push-pop principle.
Code: LIFO Stack module lifo ( input clk,
input reset, input push, input pop,
input [3:0] data_in, output reg [3:0] data_out, output reg full,
output reg empty
);
reg [3:0] stack [7:0]; // 8-depth stack reg [2:0] sp; // Stack pointer
always @(posedge clk or posedge reset) begin if (reset) begin
sp <= 0; end else begin if (push && !full) begin stack[sp]
<= data_in; sp <= sp + 1; end if (pop && !empty) begin sp

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 VLSI

<= sp - 1; data_out <= stack[sp];

end end
end

always @(*) begin full = (sp ==

8); empty = (sp == 0); end
endmodule

CHAPTER-4
CHAPTER-4: ACTIVITY LOGS ACTIVITY LOG FOR THE FIRST
WEEK

Brief description of Person In

Day & the daily activity Learning Charge
Date
Outcome Signature

Day–1 Did the registration How to apply the

20.12.2024 internship.
process in XILINX website.

Day-2
22.12.2024
I applied for State council How to apply the
internships.
of higher
education virtual
internship.

Day–3
23.12.2024 Shortlisted mail is received
from A.P.
Selected for State
council of higher
education internship

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 VLSI

Day–4 I started the

24.12.2024 internship. Started with basic
learning.

Day–5 Basics about the

25.12.2024 I attended the 1st internship.
support session of
overview.

WEEKLY REPORT-1

WEEK–1 (From Dt.20.12.2024 to Dt.25.12.2024)

Objective of the Activity done: Registration in APSCHE portal.

Detailed Report: After completion of our semester, I knew about our internship
on 20.12. 2024.I went through the detail view of the internship on 20.12.2024
to 19.04.2025 I registered in NTCS portal. I get confirmation from NTCS on
17.12.2024. I created my profile in portal on
17.12.2024. I went through some Industry contents on 18.12.2024.

RKCE DEPARTMENT OF ECE Page No: 63

 VLSI

ACTIVITY LOG FOR THE SECOND WEEK

Day & Person In

Date Brief description of
Charge
the daily activity Learning
Outcome Signature

Basics about
I started to complete the Verilog HDL.
Day–1
modules of
27.12.2024
program on Verilog
HDL

Day-2 Completed overview of

30.12.2024 Verilog HDL. Learn about
the overview of
Verilog HDL.

RKCE DEPARTMENT OF ECE Page No: 64

 VLSI

Day–3
31.12.2024 Completed history of Learned about the
Verilog HDL. history of Verilog
HDL.

Day–4 I completed the Learn about

02.12.2024 history. history.

Day–5 Completed the history. Learn about the

03.12.2024 history.

WEEKLYREPORT-2

WEEK–2 (From Dt.27.12.2024 to Dt.03.01.2025)

Objective of the Activity done: Verilog HDL-Module Installation Detailed
Report: I started learning about the modules .I started to complete the modules
of program on Verilog HDL.I have listened and learned about the history of
Verilog HDL.I took some quiz and finally completed unit 1 succesfully.

RKCE DEPARTMENT OF ECE Page No: 65

 VLSI

ACTIVITY LOG FOR THE THIRD WEEK

Day & Learning Person In

Date Brief description of the
Outcome Charge
daily activity
Signature

RKCE DEPARTMENT OF ECE Page No: 66

 VLSI

Day–1
06.01.2025 Learned about
Design Styles.
Design Styles.

Completed introduction to Learned about

Bottom design. Bottom designs.
Day–2
07.01.2025

Day–3 Completed introduction to Learned about top

08.01.2025 Bottom design. design.

Day–4 I learn about Top

09.01.2025 design.
Learn about
abstraction levels
of Verilog.

Day–5 I did some homework on

10.01.2025 Behavioural levels.

Learn about the

contents of
Behavioural levels.

WEEKLY REPORT-3

WEEK–3(From Dt.06.01.2025 to Dt.010.01.2025)

O

RKCE DEPARTMENT OF ECE Page No: 67

 VLSI

bjective of the Activity done: Learning about designs & behavioural Detailed
Report: During this week I went through some online classes and installed the
prescribed software. And practiced the explained topics. I have learned about the
design styles and also mainly learned about top design. I did some practice on
behavioural levels and finally completed gate level programs.

ACTIVITY LOG FOR THE FOURTH WEEK

RKCE DEPARTMENT OF ECE Page No: 68

 VLSI

Day & Learning Person In

Date Brief description of the
Outcome Charge
daily activity
Signature

Day–1
20.01.2025
I attended the online Clarifications about
mentored technical
the doubts.
sessions.

Day–2
21.01.2025 I went through the Learn about
unit go further with project detection.
object detection.

Day–3 Learn about the VLSI

22.01.2025 design flow.
I completed the
advantages of VLSI
design flow.

Day–4
23.01.2025 I went through the Learn about the
XILINX software to get XILINX software.
started.

Day–5
24.01.2025 Completed the software Learn about the
tools. software tools.

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 VLSI

WEEKLY REPORT-4

WEEK–4(From Dt.20.01.2025 to Dt.24.01.2025)

Objective of the Activity done: Learning of design flow and XILINX
Detailed Report: I went through those online classes. Here I learned about the
design flow of the Verilog HDL. Later I have learned through the XILINX
software. I completed the software tools and also done my practice sessions.

RKCE DEPARTMENT OF ECE Page No: 70

 VLSI

ACTIVITY LOG FOR THE FIFTH WEEK

Day & Learning Person In

Brief description of the
Date Outcome Charge
daily activity
Signature

Day–1 I completed how to

27.01.2025 create a project. Learn about how
create a project.

Day-2 I completed how to open

28.01.2025 a project.
Doubt
clarification.

Day–3
29.01.2025 I cleared all my doubts in Doubt
question-andanswer
clarification.
session.

Day–4 Learn about

30.01.2025 I went through how to do product the
Device and Design flow of
device and design
project.
flow of project.

Day–5 Learn about

31.01.2025 creating new
I completed about how to
source window.
create a new source
window.

WEEKLY REPORT-5

WEEK–5(From Dt.27.01.2025 to Dt.31.01.2025)

Objective of the Activity done: Obtaining the subject
Detailed Report: They have given online classes to us. Here I learned about
how to create a project. They have conducted some question-andanswer

RKCE DEPARTMENT OF ECE Page No: 71

 VLSI

session. I have cleared my doubts. Finally I created a new source window .

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 VLSI

ACTIVITY LOG FOR THE SIXTH WEEK

Brief description
Day & the daily activity Learning Person In
Date Outcome Charge
Signature

Learned about how

I learned about to creating of HDL
Day–1
source file.
03.02.2025 how to creating of
HDL source
file.

Day-2 I learned about

04.02.2025
I learned about how Verilog source
window.
to define
Verilog source
window.

Day–3 Learned about all the

05.02.2025 I revisited all the units.
units for writing the
assignment.

Day–4 Learned about all the

06.02.2025 I revisited all the units.
units for writing the
assignment.

Day–5 Learn all the units.

07.02.2025 I revisited all the
units for writing the
assignment.

RKCE DEPARTMENT OF ECE Page No: 73

 VLSI

WEEKLY REPORT-6

WEEK–6(From Dt.03.02.2025 to Dt.07.02.2025)

Objective of the Activity done: Learned clearly about HDL file Detailed
Report: I attended orientation classes. In this week I have learned some more
topics. I clearly learned about how to create a HDL source file. I revised all the
learned unit again. And also mainly understood how to edit the source file.

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 VLSI

ACTIVITY LOG FOR THE SEVENTH WEEK

Learning Person In
Day & Date Brief description of the Outcome Charge
daily activity
Signature

Day–1
10.02.2025
I learned about how to Learned about the
create and assign a create and assign
statement using OR statement using OR
gate. gate.

Day-2
11.02.2025 I learned about the Complete about the
synthesis and
synthesis and
implementation of the implementation of
design. the design.

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 VLSI

Day–3
12.02.2025 Implementing the design. Completed
implementing a
design.

Learn about the functional Learned about the

Day–4 simulation of
combinational design. functional
13.02.2025
simulation of
combinational
design.

Learn about
simulating and
Day–5
viewing the output
14.02.2025 waveforms. Learned about
simulating and
viewing the output
waveforms.

WEEKLY REPORT-7

WEEK–7(From Dt.10.02.2024 to Dt.14.02.2024)

Objective of the Activity done: Learned about VLSI
Detailed Report: I attended orientation class. In this week I have learned some
more topics. I have learned about assign a statement based on gates. Learnt
about simulating and output waveforms.
Learned about some circuits also.

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ACTIVITY LOG FOR THE 8th WEEK

Learning Person In
Day & Date Brief description of the Outcome Charge
daily activity
Signature

Day–1
17.02.2025
I learned about how to Learned about the
create and assign a create and assign
statement using OR statement using OR
gate. gate.

Day-2
18.02.2025 I learned about the Complete about the
synthesis and synthesis and
implementation of the implementation of
design. the design.

Day–3
19.02.2025 Implementing the design.
Completed
implementing a
design.

Learn about the functional Learned about the

Day–4 simulation of
combinational design. functional
20.02.2025
simulation of
combinational
design.

Learn about simulating

and
Day–5
viewing the output
21.02.2025 waveforms. Learned about
simulating and
viewing the output
waveforms.

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WEEKLY REPORT

– 8 WEEK 8 (From 17.02.2025 to 21.02.2025)

Objective of the Activity: To deepen knowledge in VLSI by learning about

combinational and sequential circuits, and to practice circuit implementation using
simulation tools.
Detailed Report: In this week, I continued learning about VLSI with a focus on both
combinational and sequential circuits. I explored how to design and implement
various logic circuits such as multiplexers, demultiplexers, encoders, decoders, and flip-
flops.
We were introduced to Verilog programming for writing hardware description language
(HDL) code to represent these circuits. I practiced writing Verilog code for different logic
modules and simulated them using software tools to observe output waveforms and
verify their behavior.
Additionally, I learned how to debug simulation errors and interpret waveform results,
which helped improve my understanding of timing and functionality in digital systems.

ACTIVITY LOG FOR THE 9th WEEK

Learning Person In
Day & Date Brief description of the Outcome Charge
daily activity
Signature

Day–1
03.03.2025
I learned about how to Learned about the
create and assign a create and assign
statement using OR statement using OR
gate. gate.

Day-2
04.03.2025 I learned about the Complete about the
synthesis and synthesis and
implementation of the
implementation of
design. the design.

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 VLSI

Day–3
05.03.2025 Implementing the design.
Completed
implementing a
design.

Learn about the functional Learned about the

Day–4 simulation of
combinational design. functional
06.03.2025
simulation of
combinational
design.

Learn about
simulating and
Day–5
viewing the output
07.03.2025 waveforms. Learned about
simulating and
viewing the output
waveforms.

– 9 WEEK 9 (From 03.03.2025 to 07.03.2025)

Objective of the Activity: To enhance proficiency in VLSI by working on advanced

Verilog concepts and implementing real-time digital system designs.
Detailed Report: In this week, I focused on advancing my knowledge in Verilog
programming by working on more complex digital designs. I learned about finite state
machines (FSMs) and how they are used in designing sequential systems.
I practiced writing Verilog code for Moore and Mealy machines, and simulated their
behavior to understand the difference in output response with respect to state
transitions. I also explored timing analysis and synthesis of digital circuits using
simulation tools, which gave me a clearer view of how HDL code translates to actual
hardware.
In addition, I started working on a mini project that involves designing a basic digital
system using the concepts I have learned so far. This activity improved my design

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thinking and problem-solving skills.

ACTIVITY LOG FOR THE 10th WEEK

Learning Person In
Day & Date Brief description of the Outcome Charge
daily activity
Signature

Day–1
10.03.2025
I learned about how to Learned about the
create and assign a create and assign
statement using OR statement using OR
gate. gate.

Day-2
11.03.2025 I learned about the Complete about the
synthesis and synthesis and
implementation of the implementation of
design. the design.

Day–3
12.03.2025
Implementing the design.
Completed
implementing a
design.

Learn about the functional Learned about the

Day–4 simulation of
combinational design. functional
13.03.2025
simulation of
combinational
design.

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Learn about
simulating and
Day–5
viewing the output
14.03.2025 waveforms. Learned about
simulating and
viewing the output
waveforms.

–10 WEEK 10 (From 10.03.2025 to

14.03.2025)

Objective of the Activity:To apply VLSI concepts in project development and gain
hands-on experience in integrating multiple modules into a complete digital system.
Detailed Report:During this week, I continued working on my mini project, which
involved integrating various Verilog modules into a functional digital system. I focused
on combining combinational and sequential logic blocks to achieve the desired
operation.
I learned how to structure larger Verilog projects using hierarchical design, which
helped me manage and debug the code more efficiently. I also paid attention to
testbenches and wrote simulation scripts to verify the functionality of each module
before integration.
Additionally, I explored the synthesis process in FPGA design, gaining insight into how
Verilog code is mapped to hardware. This gave me a practical understanding of real-
world digital system implementation. The project work this week significantly
strengthened my understanding of design flow, from coding to simulation and synthesis.

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ACTIVITY LOG FOR THE 11th WEEK

Learning Person In
Day & Date Brief description of the Outcome Charge
daily activity
Signature

Day–1
17.03.2025
I learned about how to Learned about the
create and assign a create and assign
statement using OR statement using OR
gate. gate.

Day-2
18.03.2025 I learned about the Complete about the
synthesis and synthesis and
implementation of the implementation of
design. the design.

Day–3
19.03.2025 Implementing the design.
Completed
implementing a
design.

Learn about the functional Learned about the

Day–4 simulation of
combinational design. functional
20.03.2025
simulation of
combinational
design.

Learn about
simulating and
Day–5
viewing the output
21.03.2025 waveforms. Learned about
simulating and
viewing the output
waveforms.

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–11WEEK 11-(From 17.03.2025 to 21.03.2025)

Objective of the Activity:To finalize and test the mini project by verifying all design
modules and evaluating system performance through simulation and synthesis.
Detailed Report:In this week, I focused on completing and testing my mini
project. I verified the functionality of the integrated system through rigorous
simulation using testbenches and made necessary corrections to ensure accurate
output.
I also worked on optimizing the Verilog code to improve resource utilization and
timing performance during synthesis. This process helped me understand the
importance of writing efficient code for real-time applications.
Additionally, I explored waveform analysis in more depth, identifying glitches and
timing issues and resolving them using techniques like proper clocking and state
management.
Finally, I documented the project development process, including design
architecture, simulation results, and final observations. This week gave me a strong
sense of how theoretical VLSI concepts are applied in practical digital system
design.

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ACTIVITY LOG FOR THE 12th WEEK

Learning Person In
Day & Date Brief description of the Outcome Charge
daily activity
Signature

Day–1
24.03.2025
I learned about how to Learned about the
create and assign a create and assign
statement using OR statement using OR
gate. gate.

Day-2
25.023.2025 I learned about the Complete about the
synthesis and synthesis and
implementation of the implementation of
design. the design.

Day–3
26.02.2025 Implementing the design.
Completed
implementing a
design.

Learn about the functional Learned about the

Day–4 simulation of
combinational design. functional
27.03.2025
simulation of
combinational
design.

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 VLSI

Learn about
simulating and
Day–5
viewing the output
28.03.2025 waveforms. Learned about
simulating and
viewing the output
waveforms.

WEEKLY REPORT -12

WEEK 12-(From 24.03.2025
to 28.03.2025)

Objective of the Activity:To review the overall learning from the VLSI module, present
the mini project, and reflect on the outcomes and skills gained.
Detailed Report:This week marked the conclusion of the VLSI training. I focused
on finalizing and presenting my mini project. I prepared a comprehensive
presentation that included the project objectives, design flow, Verilog
implementation, simulation results, synthesis overview, and conclusions.
As part of the final review, I revisited all the key topics covered throughout the
course such as logic gate design, combinational and sequential circuits, Verilog
HDL, FSMs, simulation, and synthesis. I also participated in a Q&A session and
received feedback on my project work, which helped me recognize areas of strength
and opportunities for improvement.
Overall, this week was a valuable reflection on the skills and knowledge acquired

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over the past weeks. I feel more confident in understanding digital design
concepts and applying them using industry-standard tools and techniques.

CHAPTER 5: OUTCOMES DESCRIPTION

5.1 Course Outcomes:

VLSI Design Internship – Course Outcomes (COs)

1. CO1: Apply fundamental knowledge of digital and analog electronics to understand
VLSI design principles and methodologies.
2. CO2: Demonstrate the ability to design and simulate combinational and sequential
digital circuits using HDL (Verilog/VHDL).
3. CO3: Analyze the performance and timing issues of VLSI circuits using industry-
standard EDA tools (like Xilinx, Cadence, or Synopsys).
4. CO4: Develop layout designs and perform physical verification (DRC/LVS) for
CMOS circuits.
5. CO5: Work collaboratively in a team environment and apply problem-solving
strategies for real-time VLSI design challenges.
6. CO6: Document and present VLSI-based project work professionally using
appropriate technical standards.

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5.2 real time technical skills acquired

1. HDL Programming (Verilog/VHDL) o Developed and tested RTL models for

combinational and sequential circuits.
o Hands-on experience writing testbenches for functional simulation.

2. FPGA Implementation
o Synthesized HDL code and deployed it on FPGA boards (e.g., Xilinx Spartan or
Artix).
o Worked on I/O pin mapping, clock constraints, and bitstream generation.

3. EDA Tool Proficiency o Gained practical skills in tools such as Xilinx

Vivado, ModelSim, or Cadence Virtuoso.
o Performed simulation, synthesis, and timing analysis of digital designs.

4. RTL-to-GDSII Design Flow (for ASIC)

o Understood stages like synthesis, floorplanning, placement, clock tree synthesis,
and routing.
o Learned the use of physical verification techniques such as DRC and LVS.
5. CMOS Circuit Design & Analysis
o Designed CMOS inverters, logic gates, and latches using schematic and layout
tools.
o Analyzed power, area, and timing metrics of VLSI designs.
6. Timing and Power Analysis o Performed static timing analysis
(STA) and optimized timing paths.
o Used tools to estimate power consumption and suggested low-power design

techniques.
7. Team Collaboration and Project Documentation o
Worked in teams using version control tools like Git.
Prepared design documentation, simulation reports, and presented final project
outcomes

5.

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3 managerial skills acquired

1. Project Planning and Time Management

Learned to define project goals, set realistic deadlines, and break complex VLSI
tasks into manageable phases.
Effectively prioritized tasks to meet milestones within tight timelines.

2. Team Collaboration and Coordination

Collaborated with peers in a team-based environment to divide responsibilities,
track progress, and resolve design issues.
Participated in regular team meetings and reviews to align on goals and share
updates.
3. Effective Communication
Improved technical communication by explaining design decisions, presenting
results, and writing documentation clearly.
Gained confidence in presenting VLSI concepts and project outcomes to mentors
and technical panels.

4. Problem Solving and Decision Making

Tackled real-time technical challenges with a structured problem-solving
approach.
Made informed decisions based on simulation results, tool feedback, and design
constraints.
5. Adaptability and Learning Agility
Quickly adapted to new tools and workflows in VLSI design environments.
Maintained a learning mindset while working with advanced tools and
industry-standard practices.
6. Leadership and Initiative
Took initiative to suggest improvements in project workflows or propose alternate
design approaches.

5.4 improvement of communication skills

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Improving communication skills during an internship involves a combination of self-

awareness, active learning, and consistent practice. Here are several strategies that can
be employed to enhance communication skills during an internship:
1. Active Listening:
• Engage Actively: Pay close attention to what others are saying, show interest
through body language, nodding, and maintaining eye contact.
• Clarify and Confirm: Ask questions to clarify points and confirm your
understanding of the information provided.
2. Effective Verbal Communication:
• Clarity: Speak clearly and at a moderate pace. Avoid using jargon or overly
complex language.
• Conciseness: Be concise and to the point. Avoid unnecessary elaboration.
• Confidence: Speak confidently, even if you are uncertain. Confidence in your tone
can enhance your message.
3. Written Communication:
• Professional Emails: Practice writing clear, concise, and professional emails. Use
proper grammar, punctuation, and formatting.
• Documentation: Improve your skills in documenting processes, projects, and
reports. Clear documentation is crucial in professional settings.
4. Non-Verbal Communication:
• Body Language: Be mindful of your body language. Maintain an open and
approachable posture.
• Facial Expressions: Be aware of your facial expressions; they convey emotions
and intentions.
5. Empathy and Emotional Intelligence:
• Put Yourself in Others' Shoes: Understand the perspectives of your colleagues,
superiors, and clients.
• Manage Emotions: Learn to manage your emotions, especially in challenging
situations. Remain calm and composed.

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. Feedback and Adaptability:

• Accept Feedback: Be open to constructive criticism. Use feedback as a tool for
improvement.
• Adapt to Your Audience: Tailor your communication style based on the audience
(e.g., colleagues, supervisors, clients). Understand their preferences and adjust
your approach accordingly.
7. Presentation Skills:
• Preparation: Prepare thoroughly for presentations. Rehearse to improve
confidence and fluency.
• Engage the Audience: Encourage interaction during presentations. Ask questions
and involve your audience.

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VLSI

5.5 technological developments observed and relevant to the subject area

of training (focus on digital technologies relevant to your job role)

During the course of my VLSI Design Internship, I observed several cutting-edge technological
advancements that are shaping the future of digital system design and semiconductor industries:
1. Advanced FinFET and GAAFET Technologies o The industry is moving beyond traditional planar
transistors to FinFET and emerging GAAFET architectures to enhance speed, reduce leakage power,
and enable further miniaturization.
2. Rise of System-on-Chip (SoC) Design o There's a growing trend toward integrating multiple
functionalities — processors, memory, I/O — into a single SoC, enabling compact, power-efficient,
and high-performance solutions for mobile and embedded systems.
3. Automation through EDA Tools o Enhanced Electronic Design Automation (EDA) tools now offer
advanced features like realtime power estimation, constraint-driven synthesis, and AI-assisted place
& route, significantly improving design efficiency and accuracy.
4. Low Power Design Techniques
o As power efficiency becomes critical, techniques like clock gating, dynamic voltage scaling,

and multi-VDD design are increasingly being adopted in digital design workflows.
5. FPGA Advancements o Modern FPGAs come with high-speed transceivers, hardened processor
cores, and AI accelerators, making them suitable for rapid prototyping of complex applications
including AI/ML and high-speed networking.
6. Shift Toward AI and ML in VLSI o Machine Learning is being integrated into chip design
verification, test pattern generation, and performance optimization, marking a shift toward intelligent
and adaptive hardware design.
7. Design for Testability (DFT) Innovations o Techniques such as boundary scan, built-in self-test
(BIST), and scan chain compression are being increasingly automated and improved to enhance chip
reliability and yield.
8. Open Source VLSI Tools
Tools like OpenLane, Magic, and KLayout are enabling learners and startups to explore end-to-end chip
design workflows without expensive licenses

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 Student Self-Evaluation of the Long-Term Internship

Student Name :K. MANOHAR

Registration No : 22MC5A0422
Term of Internship : 16 Weeks 20.12.2024 to 19.04.2025
Date of Evaluation :
Organization Name & Address : Naresh Technologies & Consultancy Services
Please rate your performance in the following areas:
Rating Scale: Letter grade of CGPA calculation to be provided

1 Oral communication 1 2 3 4 5
2 Written communications 1 2 3 4 5

3 Pro activeness 1 2 3 4 5
4 Interaction ability with community 1 2 3 4 5

5 Positive Attitude 1 2 3 4 5
6 Self-confidence 1 2 3 4 5

7 Ability to learn 1 2 3 4 5
8 Work Plan and organization 1 2 3 4 5
9 Professionalism 1 2 3 4 5

10 Creativity 1 2 3 4 5
11 Quality of work done 1 2 3 4 5

12 Time Management 1 2 3 4 5
13 Understanding the Community 1 2 3 4 5
14 Achievement of Desired Outcomes 1 2 3 4 5

15 OVER ALL PERFORMANCE 1 2 3 4 5

Date: Signature of the Student

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Evaluation by the Supervisor of the Intern Organization

Student Name : K.MANOHAR

Registration No : 22MC5A0422
Term of Internship : 16 weeks from :20.12.2024to:19.04.2025 Date
of Evaluation :
Organization Name & Address: Naresh Technologies & Consultancy Services
Name & Address of the supervisor With
mobile number :

Please rate the student’s performance in the following areas:

Please note that your evaluation shall be done independent to the student’s Self
-evaluation

Rating Scale:1 is lowest and 5 Is highest rank

1 Oral communication 1 2 3 4 5

2 Written communication 1 2 3 4 5

3 Pro activeness 1 2 3 4 5

4 Interaction ability with community 1 2 3 4 5

5 Positive Attitude 1 2 3 4 5

6 Self-confidence 1 2 3 4 5

7 Ability to learn 1 2 3 4 5

8 Work Plan and organization 1 2 3 4 5

9 Professionalism 1 2 3 4 5

10 Creativity 1 2 3 4 5

11 Quality of work done 1 2 3 4 5

12 Time Management 1 2 3 4 5

13 Understanding the Community 1 2 3 4 5

14 Achievement of Desired Outcomes 1 2 3 4 5

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15 OVERALL PERFORMANCE 1 2 3 4 5

Date: Signature of the Supervisor

EVALUATION
Internal Evaluation for Long Term Internship (Virtual)
Objectives:

• To integrate the or and practice.

• To learn to appreciate work and its function towards the future.

• To develop work habits and attitude necessary for job success.

• To develop communication, interpersonal and other critical skills in the

future job.

• To acquired skills required for the world of work.

Assessment Model:

• There shall only be internal evaluation.

• The Faculty Guide assigned is in-charge of the learning activities of the

students and for the comprehensive and continuous assessment of the
students.

• The assessment is to be conducted for100 marks.

• The number of credits assigned is 4. Later the marks shall be converted into
grad de points to include finally in the SGPA and CGPA.

• The weightings shall be:

o Activity Log 25marks

o Internship Evaluation 50marks

o Overall Presentation 25marks

• Activity Log is their cord of the day -to- day activities. The Activity Log is
assessed on an individual basis, thus allowing for individual members
w

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ithin groups to be assessed this way. The assessment will take into
consideration the individual student’s involvement in the assigned work.

• While evaluating the student’s Activity Log, the following shall be

considered-

a. The individual student’s effort and commitment.

b. The originality and quality of the work produced by the individual

student.

c. The student’s integration and co-operation with the work assigned.

d. The completeness of the Activity Log.

• The Internship Evaluations the following component and based on Weekly

Reports and Out comes Description

a. Description of the Work Environment.

b. Real Time Technical Skills acquired.

c. Managerial Skills acquired.

d. Improvement of Communication Skills.

e. Team Dynamics
Technological Development scored

MARKS STATEMENT

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(To be used by the Examiners)

INTERNAL ASSESSMENT STATEMENT

Name of the Student : K. MANOHAR

Program of Study : B. tech

Year of Study : 4th-year

Group : Electronics & Communication Engineering

Register No/H.T. NO : 22MC5A0422

Name of the college : RK COLLEGE OF ENGINEERING

University : JNTU, Kakinada

Sl. No Evaluation Criterion Maximum Marks

Marks Awarded

1. Activity Log 25

2. Internship Evaluation 50

3. Overall Presentation 25

GRANDTOTAL 100

Date: Signature of the Faculty Guide

Certified by

Date:

RKCE DEPARTMENT OF ECE Page No: 98