Dayananda Sagar College of Engineering

Department of Electronics and Communication Engineering

Shavige Malleshwara Hills, Kumaraswamy Layout, Bangalore – 560 111.
(An Autonomous Institute affiliated to VTU, Approved by AICTE & ISO 9001:2008 Certified)
Accredited by National Assessment and Accreditation Council (NAAC) with ‘A’ grade

AAT

Program: B.E. Branch: ECE

Course: Advanced Digital Design Semester/Section :5th Sem-D
Course Code: 22EC552 Date: 23/12/2024

A Report on

“ AXI - PROTOCOL ”

Submitted by

SHASHWAT DINESH NAIK

1DS22EC206 SHRINIDHI L BHIJAPUR
1DS22EC211 RAHUL K 1DS23EC423
SATISH K GOWDA 1DS22EC199

Faculty In-charge

Dr. Madhura R
CONTENTS:

1. Abstract
2. Introduction
3. Literature Survey
3. Problem Definition
4. Objectives
5. Main Block Diagram
Explanation to each
section
6. Comparision Table
Comparision with proposed and Existing (previous papers) simulation results
7. Results and Discussions

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 ABSTRACT

This project demonstrates the implementation and simulation of a simplified AXI protocol- based Master-Slave
Communication system using the Verilog HDL. The AXI (Advanced eXtensible Interface) protocol, is a widely
used standard in high -performance Sysytem-on-Chip(SoC) designs, provides efficient and reliable data transfer
mechanisms between different hardware components. The implementation models a simplified master-slave
interaction to explore the protocol’s capabilities in handling the data transaction, ensuring the high performance
and scalability.
In this design the master acts as the initiator, controlling read and write operations, while the slave responds to these
requests by managing the data within an internal memory array. The system incorporates independent channels
for write addressing, write data, read addressing, and read data, allowing concurrent operations and improving
throughout. A handshake mechanism, utilizing valid and ready signals, ensures synchronized and reliable
communication between the master and slave.
The project stimulates the key operation of the AXI protocol, including the writing data to specific memory
addresses and retrieving data from those addresses. This implementation serves as a foundational study for
understanding the AXI protocol behavior. The simulation asserts the correct functionality of the protocol,
including the successful execution of read and write operation with the proper acknowledgment and data
integrity. The design also demonstrates the principles of pipelined communication and transaction-based
interfacing, which are essential for high performance SoC designs. This project serves as a stepping stone for
further exploration of advanced AXI features, such as burst transfers, multi-master environment, and integration
into larger hardware designs.

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INTRODUCTION

The Advanced eXtensible Interface(AXI) protocol is a widely used on chip communication standard, part of the
ARM advanced Microcontroller Bus Architecture(AMBA) family. It is designed to facilitate high-speed and
efficient data transfers between the various components in a System-on-Chip(SoC), such as processors, memory
controllers, and peripherals. The AXI protocol plays a vital role in modern digital designs by providing the
robust and scalable framework for data communication. It is characterized by its high- performance and
independent transaction channels. It supports both read and write transaction through separate channels,
allowing pipelined and concurrent operations. This feature enhances throughput and makes it ideal for high-
bandwidth application such as processing, multimedia systems, and real -time computing.
Key features of AXI Protocol:
 Independent Channels: uses 5 independent channels like Write address, write address, write response,
read address, read data.
 Handshake Mechanism: Synchronization between components is achieved through valid and ready
signals, which establish reliable communication and maintain data integrity.
 Burst Transfers: AXI protocol supports the multiple data transfers in a single transaction, improving the
efficiency for large data blocks.
 Out-of-Order Transactions: The protocol allows transactions to complete in an order different from their
initiation, which is beneficial for optimizing system performance.
 Scalability: AXI is scalable and supports multi-master and multi-slave configurations, making it suitable
for complex SoC designs.
The AXI protocol is the backbone of the modern digital systems due to its flexibility and high performance. It
enables designers to implement efficient interconnections between processing elements and memory
subsystems, crucial for achieving the speed and reliability required in advanced applications. As SoC’s become
increasingly complex, understanding the principles and implementation of AXI protocol is essential for
engineering working areas like embedded systems. Signal processing, and VLSI design.

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LITERATURE SURVEY:

LITERATURE AUTHORS CONTENT:

“Verification of AMBA AXI on-Chip Nikhil Gaikwad, Vijay.N. Patil This paper outlines the use of
Communication Protocol” Verilog to create the
communication environment for
the AXI protocol. It focuses on
ensuring the reliability of read and
write operations, verifying burst
transactions like INCR, and
WRAP, and maintaining
compliance with protocol
standards. This work highlights the
crtitical role of robust verification
in achieving reliable on-chip
communication for SoC designs.

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PROBLEM DEFINITION:
The assignment aims to implement the basic AMBA protocol- based communication system with both master
and slave functionality. However, there is a need to verify the correctness of data transfers, address handling,
and protocol compliance in a stimulated environment. The problem is to develop and validate the AXI-based
communication model where the master initiates read and write operations, the slave responds appropriately.
The challenge is to ensure that the read and write occur with the correct handshaking, address management, and
data integrity, while also implementing the necessary responses and synchronization between master and slave
components.

OBJECTIVES:
 Implement the AXI Master- Slave: Design the system where the master performs read and write
operations, and the slave responds accordingly.
 Stimulate the data transfer: Ensuring that data is correctly transferred from the master to the slave and
vice versa.
 Ensuring proper Handshaking: implement the necessary handshaking signals to synchronize read and
write operations between the master and slave.

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 BLOCK DIAGRAM:

There are five independent channels between an AXI master and slave. They are the:
 Read address channel
 Read data channel
 Write address channel
 Write data channel
 Write response channel
The address channels are used to send address and control information while performing a basic handshake between
master and slave. The data channels are where the information to be exchanged is placed .
A master reads data from and writes data to a slave. Read response information is placed on the read data channel,
while write response information has a dedicated channel. This way the master can verify a write transaction
has been completed. Every exchange of data is called a transaction. A transaction includes the address and
control

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information, the data sent, as well as any response information. The actual data is sent in bursts which contain
multiple transfers.
Much like the AHB, ASB, and APB signals from the previous AMBA revision, each of the AXI channels has a
number of signals associated with it. There are two global signals referred to as ACLK and ARESETn. These
are the system's global clock and reset signal, respectively. The 'n' suffix on ARESETn means this signal is
active low.
Every channel has an ID tag used for out-of-order transactions. Any transaction with the same ID must remain
in order, but transactions with different IDs may be completed in any order. This allows faster transactions to be
completed before slower ones, even if the slower transaction was issued first. For example, if a master is writing
data to multiple slaves, the transaction IDs would allow the faster slave to finish sooner.
Bus widths are implementation-specific, but these signals are shown with a 32-bit bus width. The RLAST signal
is used by the slave to signal to the master that the last data item is being transferred.
Other notable signals include the burst size, length, and type. The VALID and READY signals are used for
handshaking between master and slave. These will be discussed later in the article.
The cache, lock, and protection signals are used for caching, exclusive access (atomic operations), and illegal
access protection, respectively.
HANDSHAKING MECHANISM:
Every AXI channel contains both a VALID and a READY signal. These are used to synchronize and control the
rate of transfer. The important thing to remember here is that the source, or sender, uses the VALID signal to
indicate that either data or control information is available. The destination, or receiver, signals READY when it
is actually able to consume that information. Thus, a transfer can only occur when both the VALID and
READY signals are asserted. Also note that AXI uses the rising clock edge for all transfers.
One important note within the AXI specification is that the VALID signal of one component must never depend
on the READY signal of another. READY can wait for the VALID signal, but it doesn't have to. Following
these rules removes the chance of a deadlock occurring. If VALID is dependent on READY and READY is
dependent on VALID, it's easy to see that neither signal may be asserted, because each one is waiting on the
other.

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CODE:
module axi_master_slave
( input wire clk,
input wire reset,

// Write Address Channel

input wire awready,
output reg awvalid,
output reg [31:0]
awaddr,

// Write Data Channel

input wire wready,
output reg wvalid,
output reg [31:0] wdata,

// Write Response Channel

output reg bready,
input wire bvalid,
input wire [1:0] bresp,

// Read Address Channel

input wire arready,
output reg arvalid,
output reg [31:0] araddr,

// Read Data Channel

output reg rready,
input wire rvalid,
input wire [31:0]
rdata
);
// Internal states for simulation
reg [2:0] state;
localparam IDLE = 3'd0,
WRITE_ADDR = 3'd1,
WRITE_DATA = 3'd2,
WRITE_RESP = 3'd3,

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READ_ADDR = 3'd4,
READ_DATA = 3'd5;

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always @(posedge clk or posedge reset) begin
if (reset) begin
// Reset all signals
state <= IDLE;
awvalid <= 0;
arvalid <= 0;
wvalid <= 0;
bready <= 0;
rready <= 0;
awaddr <= 0;
araddr <= 0;
wdata <= 0;
end else begin
case (state)
IDLE: begin
// Prepare sender
awvalid <= 1;
awaddr <= 32'h0000_1234; // Example address
state <= WRITE_ADDR;
end

WRITE_ADDR:
begin if (awready)
begin awvalid <= 0;
wvalid <= 1;
wdata <= 32'hDEADBEEF; // Example data
state <= WRITE_DATA;
end
end

WRITE_DATA:
begin if (wready)
begin wvalid <= 0;
bready <= 1;
state <= WRITE_RESP;
end
end

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 WRITE_RESP:
begin if (bvalid)
begin bready <= 0;
arvalid <= 1;
araddr <= 32'h0000_1234; // Same address for read
state <= READ_ADDR;
end
end

READ_ADDR:
begin if (arready)
begin arvalid <= 0;
rready <= 1;
state <= READ_DATA;
end
end

READ_DATA:
begin if (rvalid)
begin rready <= 0;
state <= IDLE; // Cycle complete
end
end
endcase
end
end
endmodule

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TESTBENCH:
module axi_master_slave_tb();
reg clk;
reg reset;

// Signals for AXI channels

reg awready;
wire awvalid;
wire [31:0] awaddr;

reg wready;
wire wvalid;
wire [31:0] wdata;

wire bready;
reg bvalid;
reg [1:0] bresp;

reg arready;
wire arvalid;
wire [31:0] araddr;

wire rready;
reg rvalid;
reg [31:0] rdata;

// DUT instantiation
axi_master_slave uut (
.clk(clk),
.reset(reset),
.awready(awready),
.awvalid(awvalid),
.awaddr(awaddr),
.wready(wready),
.wvalid(wvalid),
.wdata(wdata),
.bready(bready),
.bvalid(bvalid),

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 .bresp(bresp),
.arready(arready),
.arvalid(arvalid),
.araddr(araddr),
.rready(rready),
.rvalid(rvalid),
.rdata(rdata)
);

// Clock generation
always #5 clk = ~clk;

// Test sequence
initial begin
// Initialize signals
clk = 0;
reset = 1;
awready = 0;
wready = 0;
bvalid = 0;
bresp = 2'b00;
arready = 0;
rvalid = 0;
rdata = 32'h0;

// Reset the design

#10 reset = 0;

// 1. Sender preparation
#10 awready = 1; // Accept write address

// 2. Receiver preparation
#10 wready = 1; // Accept write data

// 3. Handshake signals
#10 bvalid = 1; // Write response available

// 4. Flow of information
#10 arready = 1; // Accept read address
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 #10 rvalid = 1;
rdata = 32'hCAFEBABE; // Example read data

// 5. Final item
#20 $finish;
end
endmodule

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RESULTS:
The AXI master successfully initiates the read and write operations, and the slave correctly handles these
operations.

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COMPARISION TABLE :
Here's a comparison table highlighting key metrics:

Metric Provided Code PULP Platform Implementation

Dependent on state transitions;

Optimized for low latency; specific metrics
Latency (Cycles) requires simulation for exact
depend on module configuration.
measurement.

Single transaction at a time; Supports high-performance communication

Throughput
throughput limited by sequential with AXI4+ATOPs; capable of handling
(Ops/sec)
operation. multiple outstanding transactions.

Basic implementation; resource usage Designed for efficiency; actual resource usage
Resource Utilization
depends on synthesis results. varies with module and target FPGA.

Implements basic AXI protocol; may

Standard Full AXI standard compliance, including
require verification for full
Compliance AXI4, AXI4-Lite, and AXI4+ATOPs.
compliance.

Single master-slave setup; limited Modular design allows for building complex,
Scalability scalability without significant heterogeneous on-chip networks with various
modifications. topologies.

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Notes:
 Latency and Throughput: The provided code handles one transaction at a time, which may result in
higher latency and lower throughput compared to implementations that support multiple outstanding
transactions and burst operations, such as those in the PULP platform.
 Resource Utilization: The provided code is a straightforward implementation. In contrast, the PULP
platform's modules are designed for efficiency and may utilize resources more effectively, though actual
usage would depend on the specific module and target FPGA.
 Standard Compliance: While the provided code follows the basic AXI protocol, the PULP platform's
modules are verified for full compliance with AXI standards, ensuring reliable integration into larger
systems.
 Scalability: The modular nature of the PULP platform's AXI modules allows for the construction of
complex on-chip networks, offering greater scalability compared to the single master-slave setup in the
provided code.

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 CONCLUSION:
The AXI master successfully initiates the read and write operations, and the slave correctly handles these operations
ensuring data integrity during the transfers. The handshaking signals work as expected, ensuring proper
synchronization between the master and slave during the read and write transactions. The system correctly
handles and validates both INCR and WRAP burst types, with data being transferred efficiently across AXI
protocol. The slave memory stores and retrieves data correctly, with no data corruption observed during the
read/write operations. The system adheres to AMBA AXI protocol standards, with correct address mapping,
data transfer sequences, and response handling.

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