Logic Circuit Design

Module 4
Synchronous Sequential
Logic_part 3
‘Digital Design’ by Morris Mano
Dr. Rithu James
Asso. Professor
Dept. of ECE
RSET, Kochi
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 Module 4: Sequential Logic Circuits:
• Building blocks like S-R, JK and Master-Slave JK FF, Edge
triggered FF,
• Conversion of Flipflops, Excitation table and characteristic
equation.
• Implementation with verilog codes.
• Ripple and Synchronous counters and implementation in
verilog,
• Shift registers-SIPO, SISO, PISO, PIPO.
• Shift Registers with parallel Load/Shift, Ring counter and
Johnsons counter.
• Asynchronous and Synchronous counter design, Mod N
counter.
• Modeling and simulation of flipflops and counters in verilog.
 Contents
•Registers
•Shift registers
•Universal Shift Register
•Shift register Counters

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Registers
 Registers
• A register is a group of flip‐flops, each one of which shares a
common clock and is capable of storing one bit of
information.
• An n‐bit register consists of a group of n flip‐flops capable of
storing n bits of binary information.
• In addition to the flip‐flops, a register may have combinational
gates that perform certain data‐processing tasks.
• In its broadest definition, a register consists of a group of
flip‐flops together with gates that affect their operation.
• The flip‐flops hold the binary information, and the gates
determine how the information is transferred into the
register.
• The simplest register is one that consists of only flip‐flops,
without any gates.
 4-bit register operation
• The common clock input triggers all flip‐flops on the
positive edge of each pulse, and the binary data available
at the four inputs are transferred into the register.
• The value of ( I 3 , I 2 , I 1 , I 0 ) immediately before the clock
edge determines the value of ( A 3 , A 2 , A 1 , A 0 ) after the
clock edge.
• The four outputs can be sampled at any time to obtain the
binary information stored in the register.
• The input Clear_b goes to the active‐low R (reset) input of
all four flip‐flops. When this input goes to 0, all flip‐flops
are reset asynchronously. The Clear_b input is useful for
clearing the register to all 0’s prior to its clocked
operation.
• The R inputs must be maintained at logic 1 (i.e., de-
asserted) during normal clocked operation.
A register constructed with four D ‐type flip‐flops to form a
four‐bit data storage register
 Register with Parallel Load
• The transfer of new information into a register is referred to as
loading or updating the register.
• If all the bits of the register are loaded simultaneously with a
common clock pulse the loading is done in parallel .
• The load input to the register determines the action to be taken with
each clock pulse.
– When the load input is 1, the data at the four external inputs are
transferred into the register with the next positive edge of the clock.
– When the load input is 0, the outputs of the flip‐flops are connected to
their respective inputs.
• The feedback connection from output to input is necessary because
a D flip‐flop does not have a “no change” condition. With each clock
edge, the D input determines the next state of the register.
• To leave the output unchanged, it is necessary to make the D input
equal to the present value of the output (i.e., the output circulates to
the input at each clock pulse).
Shift Registers
Basic Data Movement in Shift Registers
 Shift Registers
• A register capable of shifting the binary information held in
each cell to its neighboring cell, in a selected direction, is called
a shift register.
• The logical configuration of a shift register consists of a chain of
flip‐flops in cascade, with the output of one flip‐flop connected
to the input of the next flip‐flop.
• All flip‐flops receive common clock pulses, which activate the
shift of data from one stage to the next. The output of a given
flip‐flop is connected to the D input of the flip‐flop at its right.
• This shift register is unidirectional (left‐to‐right).
• Each clock pulse shifts the contents of the register one bit
position to the right.
• The serial input determines what goes into the leftmost flip‐flop
during the shift.
• The serial output is taken from the output of the rightmost
flip‐flop.
Four-bit shift register
Serial In/ Serial Out Shift Registers
(SISO)

Serial In/ Serial Out Shift

Registers
Serial In/ Serial Out Shift Registers
Serial In/ Serial Out Shift Registers
Serial In/ Serial Out Shift Registers
Serial In/ Serial Out Shift Registers
 The difference between the serial and
the parallel mode of operation
• The datapath of a digital system is said to operate in serial mode
when information is transferred and manipulated one bit at a time.
• In contrast to parallel transfer, whereby all the bits of the register
are transferred at the same time.
• In the parallel mode, information is available from all bits of a
register and all bits can be transferred simultaneously during one
clock pulse.
• In the serial mode, the registers have a single serial input and a
single serial output. The information is transferred one bit at a time
while the registers are shifted in the same direction.
• Operations in digital computers are usually done in parallel because
that is a faster mode of operation.
• Serial operations are slower because a datapath operation takes
several clock cycles, but serial operations have the advantage of
requiring fewer hardware components.
Serial In/ Parallel Out Shift Registers (SIPO)

4 bit Serial In/ Parallel Out Shift Registers

Parallel In/ Serial Out Shift Registers (PISO)
Parallel In/ Parallel Out Shift Registers
(PIPO)
 Universal Shift Registers
• If the flip‐flop outputs of a shift register are accessible, then
information entered serially by shifting can be taken out in
parallel from the outputs of the flip‐flops.
• If a parallel load capability is added to a shift register, then data
entered in parallel can be taken out in serial fashion by shifting
the data stored in the register.
• Some shift registers provide the necessary input and output
terminals for parallel transfer.
• They may also have both shift‐right and shift‐left capabilities.
• A register capable of shifting in one direction only is a
unidirectional shift register.
• One that can shift in both directions is a bidirectional shift
register.
• If the register has both shifts and parallel‐load capabilities, it is
referred to as a universal shift register.
 The most general shift register has the
following capabilities:
1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.
3. A shift‐right control to enable the shift‐right operation and
the serial input and output lines associated with the shift
right.
4. A shift‐left control to enable the shift‐left operation and the
serial input and output lines associated with the shift left.
5. A parallel‐load control to enable a parallel transfer and the
n input lines associated with the parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the register
unchanged in response to the clock.
Other shift registers may have only some of the preceding
functions, with at least one shift operation.
The block diagram symbol of a four‐bit
universal shift register
The circuit diagram of a four‐bit universal shift register
 Working
• The circuit consists of four D flip‐flops and four multiplexers.
• The four multiplexers have two common selection inputs s0 and
s1 .
• Input 0 in each multiplexer is selected when s1s0 = 00, input 1 is
selected when s1s0 = 01, and similarly for the other two inputs.
• The selection inputs control the mode of operation of the register
according to the function entries in Table .
Four-to-one-line multiplexer
• When s1s0 = 00, the present value of the register is applied to the
D inputs of the flip‐flops.
– This condition forms a path from the output of each flip‐flop into the
input of the same flip‐flop, so that the output recirculates to the input
in this mode of operation.
– The next clock edge transfers into each flip‐flop the binary value it held
previously, and no change of state occurs.
• When s1s0 = 01, terminal 1 of the multiplexer inputs has a path to
the D inputs of the flip‐flops.
– This causes a shift‐right operation, with the serial input transferred into
flip‐flop A3.
• When s1s0 = 10, a shift‐left operation results, with the other serial
input going into flip‐flop A0.
• Finally, when s1s0 = 11, the binary information on the parallel
input lines is transferred into the register simultaneously during
the next clock edge.
• Note that data enters MSB_in for a shift‐right operation and
enters LSB_in for a shift‐left operation.
• Clear_b is an active‐low signal that clears all of the flip‐flops.
 Shift Register Counters

• Ring Counter
• Johnson Counter
 Ring Counter
• Timing signals that control the sequence of operations in a
digital system can be generated by a shift register or by a
counter with a decoder.
• A ring counter is a circular shift register with only one
flip‐flop being set at any particular time; all others are
cleared.
• The single bit is shifted from one flip‐flop to the next to
produce the sequence of timing signals.
• The initial value of the register is 1000 and requires
Preset/Clear flip‐flops.
• The single bit is shifted right with every clock pulse and
circulates back from T3 to T0. Each flip‐flop is in the 1 state
once every four clock cycles and produces one of the four
timing signals.
• Each output becomes a 1 after the negative‐edge transition
of a clock pulse and remains 1 during the next clock cycle.
Ring Counter
Preset the 1st Flip Flop
Clear the rest Flip Flops

10 – bit Ring Counter

 Ring Counter-
initial value1000000000
Timing Diagram – 10 Bit Ring Counter-initial value
0101000000
 Johnson Counter
• A k ‐bit ring counter circulates a single bit among the flip‐flops to provide k
distinguishable states.
• The number of states can be doubled if the shift register is connected as a
switch‐tail ring counter.
• A switch‐tail ring counter is a circular shift register with the complemented
output of the last flip‐flop connected to the input of the first flip‐flop.
• The circular connection is made from the complemented output of the
rightmost flip‐flop to the input of the leftmost flip‐flop.
• The register shifts its contents once to the right with every clock pulse, and at
the same time, the complemented value of the E flip‐flop is transferred into
the A flip‐flop.
• Starting from a cleared state, the switch‐tail ring counter goes through a
sequence of eight states.
• In general, a k ‐bit switch‐tail ring counter will go through a sequence of 2 k
states.
• Starting from all 0’s, each shift operation inserts 1’s from the left until the
register is filled with all 1’s. In the next sequences, 0’s are inserted from the
left until the register is again filled with all 0’s.
Johnson Counter

Table for 4 bit Johnson Counter

 Johnson Counter
Clock Pulse Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
Johnson Counter
Johnson Counter

Timing Diagram