SE Sem-IV
Microprocessor
CSC405
Module - 1
The Intel Microprocessors 8086 Architecture
By Prof. Sunil Katkar
Department of Computer Engineering, VCET
Module -1
The Intel Microprocessors 8086 Architecture
Objective
To equip students with the fundamental knowledge and basic technical
competence in the field of Microprocessors.
Outcome
At the end of the course student will be able to:
Identify the components and their functions in Intel 8086 microprocessors.
Module -1
The Intel Microprocessors 8086 Architecture
1.1 8086 CPU Architecture,
1.2 Programmer’s Model
1.3 Functional Pin Diagram
1.4 Memory Segmentation
1.5 Banking in 8086
1.6 De multiplexing of Address/Data bus
1.7 Functioning of 8086 in Minimum mode and Maximum mode
1.8 Timing diagrams for Read and Write operations in minimum and
maximum mode
1.9 Interrupt structure and its servicing
8086 Intel Architecture
Bus Interface Unit (BIU)
BIU fetches instructions, reads data
from memory and I/O ports, writes
data to memory and I/ O ports.
Execution Unit (EU)
EU executes instructions that have
already been fetched by the BIU.
BIU and EU functions separately.
8086 Intel Architecture - Execution Unit (EU)
• Instruction Decoder
• Control Unit
• Arithmetic Logic Unit
• Operand Register
• General Purpose Registers
• Flag Register
• Special Purpose Registers
Stack Pointer(SP)
Other Pointer and Index Register
8086 Microprocessor Architecture Registers and Special Functions
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations
BX Base register Used to hold base value in base addressing mode to access memory
data
CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions
DX Data Register Used to hold data for multiplication and division operations
SP Stack Pointer Used to hold the offset address of top stack memory
BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory
SI Source Index Used to hold index value of source operand (data) for string
instructions
6
DI Data Index Used to hold the index value of destination operand (data) for string
operations
Execution Unit (EU)
8086 INTEL Auxiliary Carry Flag
Carry Flag
ARCHITECT
Flag Register
This is set, if there is a carry from the
lowest nibble, i.e, bit three during
This flag is set, when there is
addition, or borrow for the lowest
URE nibble, i.e,
subtraction.
bit three, during
a carry out of MSB in case of
addition or a borrow in case
of subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
OF DF IF TF SF ZF AF PF CF
Overflow Flag Tarp Flag
This flag is set, if an overflow occurs, i.e, if the result of If this flag is set, the processor
a signed operation is large enough to accommodate in a enters the single step execution
destination register. The result is of more than 7-bits in mode by generating internal
size in case of 8-bit signed operation and more than 15- interrupts after the execution of
bits in size in case of 16-bit sign operations, then the
each instruction
overflow will be set.
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
7
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode.
external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address
towards the lowest address, i.e., auto incrementing mode.
disables these interrupts.
8086 Intel Architecture -Bus Interface Unit (BIU)
• Instruction Queue
• Segment Register
Code Segment Register
Data Segment Register
Stack Segment Register
Extra Segment Register
• Instruction Pointer
8086 Intel Architecture Bus Interface Unit
Instruction Queue
A group of First-In-First-Out (FIFO) in
which up to 6 bytes of instruction code
are pre fetched from the memory ahead
of time.
This is done in order to speed up the
execution by overlapping instruction
fetch with execution.
This mechanism is known as pipelining.
8086 Intel Architecture Bus Interface
Unit
Segmentation
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8086 Intel Architecture Bus Interface Unit
Significance of CS and IP
Alternative way to represent a 20 bit physical address is
Segment base : Offset 11
348A:4214
Default Segment Register
In an instruction only the offset
address is mentioned.
The segment register is fixed for
each of the pointer registers.
MEMORY BANKING IN 8086
13
INTEL 8086 - Pin Diagram
14
INTEL 8086 - Pin Details
Power Supply
5V 10%
Ground
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
15
Duty cycle: 33%
INTEL 8086 - Pin Details
Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
D0 when ALE is 0. multiplexed
address/data bus
contains address
information.
16
INTEL 8086 - Pin Details
INTERRUPT
Non - maskable
interrupt
Interrupt
acknowledge
Interrupt request 17
INTEL 8086 - Pin Details
Direct
Memory
Access
Hold
Hold
acknowledge
18
INTEL 8086 - Pin Details
Address/Status Bus
Address bits A19 –
A16 & Status bits S6
– S3
19
INTEL 8086 - Pin Details
Bus High Enable/S7
Enables most
significant data bits
D15 – D8 during read
or write operation.
S7: Always 1.
20
INTEL 8086 - Pin Details
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode
Pins
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Minimum Mode- Pin Details
Read Signal
Write Signal
Memory or I/0
Data
Transmit/Receive
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Data Bus Enable
Maximum Mode - Pin Details
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory
Status Signal
110: write memory Inputs to 8288 to
111: none -passive generate eliminated
signals due to max
mode.
23
Maximum Mode - Pin Details
Lock Output
Used to lock peripherals off the
system DMA
Activated by using the LOCK: prefix Request/Grant
on any instruction
Lock Output
24
Maximum Mode - Pin Details
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of opcode
Queue Status
Used by numeric
coprocessor (8087) 25
Latch 8282 Trans receiver 8286
Clock Generator 8284
External Circuit to Reset 8086 (Power on RESET Circuit)
8086 Microprocessor
Pins and Signals Min/ Max Pins
The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.
In the minimum mode of operation the
microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.
In the maximum mode the 8086 can work
in multi-processor or co-processor
configuration.
Minimum or maximum mode operations
are decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates in
minimum mode otherwise it operates in
Maximum mode.
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8086 Microprocessor
Pins and Signals Minimum mode signals
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied
to VCC (logic high)
8086 itself generates all the bus control signals
DT/𝐑 (Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers
𝐃𝐄𝐍 (Data Enable) Output signal from the processor
used as out put enable for the transceivers
ALE (Address Latch Enable) Used to demultiplex the
address and data lines using external latches
M/𝐈𝐎 Used to differentiate memory access and I/O
access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.
𝐖𝐑 Write control signal; asserted low Whenever
processor writes data to memory or I/O port
𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt
request is accepted by the processor, the output is
low on this line.
31
8086 Microprocessor
Pins and Signals Minimum mode signals
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied
to VCC (logic high)
8086 itself generates all the bus control signals
HOLD Input signal to the processor form the bus masters
as a request to grant the control of the bus.
Usually used by the DMA controller to get the
control of the bus.
HLDA (Hold Acknowledge) Acknowledge signal by the
processor to the bus master requesting the control
of the bus through HOLD.
The acknowledge is asserted high, when the
processor accepts HOLD.
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‘Read’ Cycle timing Diagram for Minimum Mode
‘Write’ Cycle timing Diagram for Minimum Mode
8086 Microprocessor
Pins and Signals Maximum mode signals
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)
Pins 24 -31 are reassigned
𝑺𝟎 , 𝑺 𝟏 , 𝑺𝟐 Status signals; used by the 8086 bus controller to
generate bus timing and control signals. These are
decoded as shown.
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8086 Microprocessor
Pins and Signals Maximum mode signals
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)
Pins 24 -31 are reassigned
𝑸𝑺𝟎 , 𝑸𝑺𝟏 (Queue Status) The processor provides the status
of queue in these lines.
The queue status can be used by external device to
track the internal status of the queue in 8086.
The output on QS0 and QS1 can be interpreted as
shown in the table.
37
8086 Microprocessor
Pins and Signals Maximum mode signals
During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)
Pins 24 -31 are reassigned
𝐑𝐐/𝐆𝐓𝟎 , (Bus Request/ Bus Grant) These requests are used
𝐑𝐐/𝐆𝐓𝟏 by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.
These pins are bidirectional.
The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏
𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix
instruction.
Remains active until the completion of the
instruction prefixed by LOCK.
The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while
executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.
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Maximum Mode 8086 System
39
8288 Bus Controller
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Maximum Mode 8086 System
• Here, either a numeric coprocessor of the type 8087 or another
processor is interfaced with 8086.
• The Memory, Address Bus, Data Buses are shared resources
between the two processors.
• The control signals for Maximum mode of operation are
generated by the Bus Controller chip 8288.
• The three status outputs S0*, S1*, S2* from the processor are
input to 8288.
• The outputs of the bus controller are the Control Signals, namely
DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc.
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Memory Write timing in
Maximum Mode
42
Memory Read timing in
Maximum Mode
43
Interrupts of 8086
Interrupt Service Routines
8086 Programmer’s Model
ES Extra Segment
CS Code Segment
BIU registers
(20-bit address) SS Stack Segment
DS Data Segment
IP Instruction Pointer
EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS
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