Lecture 4&5
Lecture 4&5
Lecture-4
Sequential Circuit
Introduction
Sequential logic circuits are those, whose output depends not only on the present value of the
input but also on previous values of the input signal (history of values) which is in contrast to
combinational circuits where output depends only on the present values of the input, at any
instant of time. Sequential circuit can be considered as combinational circuit with feedback
circuit. Sequential circuit uses a memory element like flip – flops as feedback circuit in order to
store past values. The block diagram of a sequential logic is shown below:
Flip-Flop: The Flip-flop is also a building block of synchronous sequential circuits. It has two
stable states. It can store one bit of information. Flip flops will have a clock signal. Their state
changes depending on the clock pulse .These devices will is having two states and a feedback
path.
The SR flip – flop is one of the fundamental parts of the sequential circuit logic. SR flip – flop is
a memory device and a binary data of 1 – bit can be stored in it. SR flip – flop has two stable
states in which it can store data in the form of either binary zero or binary one.
SR flip – flop is one of the most vital components in digital logic and it is also the most basic
sequential circuit that is possible. The S and R in SR flip – flop means ‘SET’ and ‘RESET’
respectively. Hence it is also called Set – Reset flip – flop. The symbolic representation of the
SR Flip Flop is shown below:
Inputs
2 AND Gates
2 NOR gates
This simple flip-flop is basically a one-bit memory bistable device that has two inputs, one
which will “SET” the device (meaning the output = “1”), and is labelled S and one which will
“RESET” the device (meaning the output = “0”), labelled R.
Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop back to its
original state with an output Q that will be either at a logic level “1” or logic “0” depending upon
this set/reset condition.
Truth Table:
Lecture-5
In the SR flip flop an uncertain state occurred. This can be avoided by using D flip flop. Here D
stands for “Data”.
It is constructed from SR flip flop. The two inputs (S &R) of the clocked SR flip flop are
connected to an inverter.
It is one of the most widely used flip – flops. It has a clock signal (Clk) as one input and Data
(D) as other. There are two outputs and these outputs are complement to each other.
(3) JK Flip-Flop:
The basic S-R NOR flip-flop circuit has many advantages and uses in sequential logic circuits
but it suffers from two basic switching problems.
2. if Set or Reset change state while the enable (EN) input is high the
Then to overcome these two fundamental design problems with the SR flip-flop design, the JK
flip Flop was developed.
This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to
be a universal flip-flop circuit. The two inputs labelled “J” and “K” are not shortened abbreviated
letters of other words, such as “S” for Set and “R” for Reset, but are themselves autonomous
letters chosen by its inventor Jack Kilby to distinguish the flip-flop design from other types.
The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop
with the same “Set” and “Reset” inputs. The difference this time is that the “JK flip flop” has no
invalid or forbidden input states of the SR Latch even when S and R are both at logic “1”.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal
to logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”.
Block Diagram