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VLSI Assignment (1,2) 22KD-C

The document outlines a series of questions related to the fabrication processes and characteristics of MOSFETs, CMOS technology, and digital logic design using NMOS and CMOS transistors. It includes tasks such as explaining fabrication steps, discussing design flows, and constructing various logic gates with layout diagrams. The submission deadline for these tasks is set for March 17, 2025.

Uploaded by

Balaji Gorusu
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30 views2 pages

VLSI Assignment (1,2) 22KD-C

The document outlines a series of questions related to the fabrication processes and characteristics of MOSFETs, CMOS technology, and digital logic design using NMOS and CMOS transistors. It includes tasks such as explaining fabrication steps, discussing design flows, and constructing various logic gates with layout diagrams. The submission deadline for these tasks is set for March 17, 2025.

Uploaded by

Balaji Gorusu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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LENDI INSTITUTE OF ENGINEERING AND TECHNOLOGY

(An Autonomous Institution)


Approved by A.I.C.T.E & permanently affiliated to JNTU-GV, Vizianagaram
Accredited by NAAC with “A” Grade
Jonnada (Village), Denkada (Mandal), Vizianagaram Dist – 535 005
Phone No. 08922-241111, 241112
E-Mail: [email protected] Website: www.lendi.org
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGGINERING

Question.

1 Explain the nMOS fabrication process steps with neat diagrams


2 Determine the relation between Ids verses Vds for MOSFET
3 What is threshold voltage of a MOS device and explain5 its significance
4 With neat sketches explain the CMOS inverter fabrication process with neat
diagram
5 Determine the pull up to pull down Ratio (Zpu/Zpd) for NMOS inverter driven by
different forms of pull-ups used as load in CMOS enhancement
6 Estimate Pull-up to Pull-down Ratio (Zpu/Zpd) for NMOS inverter driven by
another NMOS inverter through one or more pasns transistor.
7 Derive an equation to demonstrate the trans-conductance in MOSFET
8 Discuss ASIC design flow with neat diagram.
9 Discuss the structure of MOSFET, the formation of channel and current
conduction in n-channel MOSFET with neat diagram.
1 Explain the working principle of Bi-CMOS inverter and compare Bi-CMOS
0 technology with CMOS technology.
Discuss Latch-up in CMOS circuits and outline the problems associated with
Latch-up.

Question.

1 Utilize only NMOS transistors and design NAND gate, NOR gate.
Why NMOS transistor is placed in the pull down network?
2 Show different forms of pull up network and discuss their advantages and
disadvantages. Develop using NMOS and CMOS
technology.
3 Construct a 3 input XOR gate using NMOS and CMOS technology.
Discuss stick diagram rules.
4 Construct the schematic and stick diagram of NMOS inverter.
Develop a layout diagram for NMOS inverter.
5 Construct the schematic and stick diagram of CMOS inverter.
Develop a layout diagram for CMOS inverter.
6 Construct the schematic diagram, stick diagram, and layout diagram of 3 input
CMOS NAND gate.
7 Discuss λ-based layout design rules.
LENDI INSTITUTE OF ENGINEERING AND TECHNOLOGY
(An Autonomous Institution)
Approved by A.I.C.T.E & permanently affiliated to JNTU-GV, Vizianagaram
Accredited by NAAC with “A” Grade
Jonnada (Village), Denkada (Mandal), Vizianagaram Dist – 535 005
Phone No. 08922-241111, 241112
E-Mail: [email protected] Website: www.lendi.org
8 Demonstrate different types of µm-based (micro meter) layout design rules.
9 Explain the layout design rules associated with Bi-CMOS technology.
Construct the layout diagram of Bi-
CMOS inverter.
1 Design using minimum number of gates and construct it’s schematic
0 diagram, stick diagram, and layout diagram.

Submit on or before: 17.03.2025

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