VERILOG PROGRAMMING

PART B-EXPERIMENT 1
VERILOG IMPLEMENTATION OF HALF
ADDER AND FULL ADDER
Aim: To write and simulate Verilog code for half
adder and full adder using Xilinx Isim simulator
tool.
a) Half adder
Program:
module half_adder(sum,carry,a,b);
output sum, carry;
input a,b;
assign sum= a^b;
assign carry= a & b;
endmodule

Testbench:
module ha_test;
reg a,b;
wire sum, carry;
half_adder ha(sum,carry,a,b);

initial begin
a=0; b=0;
#100
 a=0; b=1;
#100
a=1; b=0;
#100
a=1;
b=1;
end
endmodule

b)Full adder
module full_adder(sum,cout,a,b,cin);
output sum,cout;
input a,b,cin;
wire s1,c1,c2;
half_adder ha1(s1,c1,a,b);
half_adder ha2(sum,c2,s1,cin);
or or1(cout,c1,c2);
endmodule

module half_adder(sum,carry,a,b);
output sum, carry;
input a,b;
assign sum= a^b;
assign carry= a & b;
endmodule

Testbench:
module test_fa;
reg a,b,cin;
wire sum, cout;
full_adder ha(sum,cout,a,b,cin);

initial begin
a=0; b=0; cin=0;
#100
a=0; b=0; cin=1;
#100
a=0; b=1; cin=0;
#100
a=0; b=1; cin=1;
#100
a=1; b=0; cin=0;
#100
a=1; b=0; cin=1;
#100
a=1; b=1; cin=0;
#100
a=1; b=1; cin=1;
end
endmodule

Result: Verilog code for half adder and full

adder are written, simulated and verified the
output.

EXPERIMENT 2
 VERILOG IMPLEMENTATION OF 4x1
MULTIPLEXER
Aim: To write and simulate Verilog code for 4x1
multiplexer using Xilinx Isim simulator tool.
module multiplexer (y, d0,d1,d2,d3,s0,s1);
output y;
input d0,d1,d2,d3,s0,s1;
assign y= s1?(s0?d3:d2): (s0?d1:d0);
endmodule

Testbench
module test_mult;
reg d0,d1,d2,d3,s0,s1;
wire y;
multiplexer mutl1 (y, d0,d1,d2,d3,s0,s1);
initial begin
s0=0; s1=0; d0=1; d1=0; d2=1; d3=1;
#100;
s0=0; s1=1;
#100;
s0=1; s1=0;
#100;
s0=1; s1=1;
end
 endmodule

Result: Verilog code for 4x1 multiplexer is

written, simulated and verified the output.

EXPERIMENT 3
VERILOG IMPLEMENTATION OF A
FUNCTION USING 8x1 MULTIPLEXER
Aim: To write and simulate a verilog code for
implementing the function y=Σm(1,3,7) using 8x1
multiplexer.
Program:
module multi(output y, input
s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
wire s01,s11,s21,y1,y2,y3,y4,y5,y6,y7,y8;
not n1(s01,s0);
not n2(s11,s1);
not n3(s21,s2);
and a1(y1,s01,s11,s21,d0);
and a2(y2,s01,s11,s2,d1);
and a3(y3,s01,s1,s21,d2);
and a4(y4,s01,s1,s2,d3);
and a5(y5,s0,s11,s21,d4);
and a6(y6,s0,s11,s2,d5);
and a7(y7,s0,s1,s21,d6);
and a8(y8,s0,s1,s2,d7);
or o1(y,y1,y2,y3,y4,y5,y6,y7,y8);
endmodule

module func_multi(output yout, input a,b,c);

multi
m1(yout,a,b,c,1'b0,1'b1,1'b0,1'b1,1'b0,1'b0,1'b0,
1'b1);
endmodule

Testbench
module test_mult_func;
reg a,b,c;
wire yout;
func_multi m1(yout,a,b,c);
initial begin
a=0; b=0; c=0;
#100
a=0; b=0; c=1;
#100
a=0; b=1; c=0;
#100
a=0; b=1; c=1;
#100
a=1; b=0; c=0;
 #100
a=1; b=0; c=1;
#100
a=1; b=1; c=0;
#100
a=1; b=1; cin=1;
end
endmodule

Result: Verilog code for implementing the

function y=Σm(1,3,7) using 8 x1 multiplexer is
written, simulated and verified the output.

EXPERIMENT 4
VERILOG IMPLEMENTATION OF FLIP FLOPS
Aim: To write and simulate Verilog code for D flip
flop and JK flip flop Xilinx Isim simulator tool.
a) D flip flop
Program:
module dflip(input clk,d,preset,clear,output reg
q,qbar);
always @(posedge clk)
begin
if(clear==0 && preset==1)begin
q<=0;
qbar<=1; end
else if(clear==1 && preset==0) begin
q<=1;
qbar<=0; end
else if(clear==1 && preset ==1 && d==0) begin
q<=0;
qbar<=1; end
else if(clear==1 && preset==1 && d==1) begin
q<=1;
qbar<=0; end
else begin
q<=0;
qbar<=1; end
end
endmodule
Testbench:
module test_dflip;
reg clk,d,preset,clear;
wire q, qbar;
dflip dff(clk,d,preset,clear,q,qbar);
initial begin
clk=0; clear=0; preset=1; d=1;
#100;
clear=1; preset=0;
#100;
clear=1; preset=1;
#100;
d=0;
end
always #5 clk=!clk;
endmodule

b)JK flip flop

Program:
module jkflip(input clk,preset, clear,j,k,output reg
q,qbar);
always @(negedge clk)
begin
if(preset==1 && clear==0)
begin
q<=0;
qbar<=1;
end
else if (preset==0 && clear==1)
begin
q<=1;
qbar<=0;
end
else if (preset==1 && clear==1 && j==0 && k==0)
begin
q<=q;
qbar<=qbar;
end
else if(preset==1 && clear==1 && j==0 && k==1)
begin
q<=0;
qbar<=1;
end
else if(preset==1 && clear==1 && j==1 && k==0)
begin
q<=1;
qbar<=0;
end
else if(preset==1 && clear==1 && j==1 && k==1)
begin
q<=~q;
qbar<=~qbar;
end
else begin
q<=0;
qbar<=1;
end
end
endmodule

Testbench:
module test_jk;
reg clk,preset, clear,j,k;
wire q, qbar;
jkflip jkff(clk,preset, clear,j,k,q,qbar);
initial begin
clk=0;j=0;k=0;clear=0;preset=1;
#100;
j=0;k=0;clear=1;preset=0;
#100;
j=1;k=0;clear=1;preset=1;
#100;
j=1;k=1;clear=1;preset=1;
end
always #5 clk=!clk;
endmodule

Result: Verilog codes for D flipflop and JK flip flop

are written, simulated and verified the output.

EXPERIMENT 5
VERILOG IMPLEMENTATION OF RING
COUNTER
Aim: To write and simulate Verilog code for 4-bit
ring counter using Xilinx Isim simulator tool.
Program:
module dflip(input clk,d,preset,clear,output reg
q,qbar);
always @(posedge clk)
begin
if(clear==0 && preset==1)begin
q<=0;
qbar<=1; end
else if(clear==1 && preset==0) begin
q<=1;
qbar<=0; end
else if(clear==1 && preset ==1 && d==0) begin
q<=0;
qbar<=1; end
else if(clear==1 && preset==1 && d==1) begin
q<=1;
qbar<=0; end
else begin
q<=0;
qbar<=1; end
end
endmodule
module ring(input clk, preset1,clear1,output[3:0] q);
wire [3:0] qbar;
dflip dff1(clk,q[3],preset1,1'b1,q[0],qbar[0]);
dflip dff2(clk,q[0],1'b1,clear1,q[1],qbar[1]);
dflip dff3(clk,q[1],1'b1,clear1,q[2],qbar[2]);
dflip dff4(clk,q[2],1'b1,clear1,q[3],qbar[3]);
endmodule
Testbench:
module test_ring;
reg clk,preset1,clear1;
wire [3:0] q;
ring r1(clk,preset1,clear1,q);
initial begin
clk=0; clear1=0; preset1=0;
#100;
clear1=1; preset1=1;
end
always #5 clk=!clk;
endmodule

Result: Verilog code for 4-bit ring counter is written,

simulated and verified the output.
 EXPERIMENT 6
VERILOG IMPLEMENTATION OF 3-BIT
UP/DOWN ASYNCHRONOUS COUNTER
Aim: To write and simulate Verilog code for 3-bit
up/down asynchronous counter using Xilinx Isim
simulator tool.
module asynchronous(input clk,
preset1,clear1,m,output[2:0] q,qbar);
wire clk1,clk2;
jkflip jff1(clk,preset1,clear1,1’b1,1’b1,q[0],qbar[0]);
xor xro1(clk1,q[0],m);
jkflip
jff2(clk1,preset1,clear1,1’b1,1’b1,q[1],qbar[1]);
xor xro2(clk2,q[1],m);
jkflip
jff3(clk2,preset1,clear1,1’b1,1’b1,q[2],qbar[2]);
endmodule
module jkflip(input clk,preset, clear,j,k,output reg
q,qbar);
always @(negedge clk)
begin
if(preset==1 && clear==0)
begin
q<=0;
qbar<=1;
end
else if (preset==0 && clear==1)
begin
q<=1;
qbar<=0;
end
else if (preset==1 && clear==1 && j==0 && k==0)
begin
q<=q;
qbar<=qbar;
end
else if(preset==1 && clear==1 && j==0 && k==1)
begin
q<=0;
qbar<=1;
end
else if(preset==1 && clear==1 && j==1 && k==0)
begin
q<=1;
qbar<=0;
end
else if(preset==1 && clear==1 && j==1 && k==1)
begin
q<=~q;
qbar<=~qbar;
end
else begin
q<=0;
qbar<=1;
end
end
endmodule

Testbench:
module test_asynch;
reg clk,preset1,clear1,m;
wire [2:0] q,qbar;
asynchronous asy1(clk, preset1,clear1,m,q,qbar);
initial begin
clk = 0;
preset1 = 1;
clear1 = 0;
m = 0;
#100;
clear1=1;
#80
preset1=0;
m=1;
#10;
preset1=1;
end
always #5 clk=!clk;
endmodule
Result: Verilog code for 3-bit asynchronous up/down
counter is written, simulated and verified the output.
 FOR REFERENCE
1. DEMULTIPLEXER
module demultiplexer(d0,d1,d2,d3,in1,s0,s1);
input in1, s0,s1;
output d0,d1,d2,d3;
wire s01,s11;
not n1(s0,s01);
not n2(s1,s11);
and a1(s01,s11,in1,d0);
and a2(s01,s1,in1,d1);
and a3(s0,s11,in1,d2);
and a4(s0,s1,in1,d3);
endmodule

2. FLIP FLOP

SR flip flop
module flips(input clk,s,r,output reg q,qbar);
always @(posedge clk)
begin
if (s==0 && r==0)
begin
q=q;
qbar=qbar;
end
else if(s==0 && r==1)
begin
q=0;
qbar=1;
end
else if(s==1 && r==0)
begin
q=1;
qbar=0;
end
else begin
q=0;
qbar=1;
end
end
endmodule