Registers

A Register is a collection of flip flops. A flip flop is used to store single bit digital data. For
storing a large number of bits, the storage capacity is increased by grouping more than one
flip flops. If we want to store an n-bit word, we have to use an n-bit register containing n
number of flip flops.
The register is used to perform different types of operations. For performing the operations,
the CPU uses these registers. The faded inputs to the system will store into the registers.
The result returned by the system will store in the registers. There are the following
operations which are performed by the registers:
Fetch:
It is used
o To take the instructions given by the users.
o To fetch the instruction stored into the main memory.
Decode:
The decode operation is used to interpret the instructions. In decode, the operation
performed on the instructions is identified by the CPU. In simple words, the decode
operation is used to decode the instructions.ullscreen
Execute:
The execution operation is used to store the result produced by the CPU into the memory.
After storing this result, it is displayed on the user screen.
Types of Registers
There are various types of registers which are as follows

MAR or Memory Address Register

The MAR is a special type of register that contains the memory address of the data and
instruction. The main task of the MAR is to access instruction and data from memory in the
execution phase. The MAR stores the address of the memory location where the data is to
be read or to be stored by the CPU.
Program Counter
The program counter is also called an instruction address register or instruction pointer. The
next memory address of the instruction, which is going to be executed after completing the
execution of current instruction, is contained in the program counter. In simple words, the
program counter contains the memory address of the location of the next instruction.
Accumulator Register
The CPU mostly uses an accumulator register. The accumulator register is used to store the
system result. All the results will be stored in the accumulator register when the CPU
produces some results after processing.
MDR or Memory Data Register
Memory Data Register is a part of the computer's control unit. It contains the data that we
want to store in the computer storage or the data fetched from the computer storage. The
MDR works as a buffer that contains anything for which the processor is ready to use it. The
MDR contains the copied data of the memory for the processor. Firstly the MDR holds the
information, and then it goes to the decoder.
The data which is to be read out or written into the address location is contained in
the Memory Data Register.
The data is written in one direction when it is fetched from memory and placed into the
MDR. In write instruction, the data place into the MDR from another CPU register. This CPU
register writes the data into the memory. Half of the minimal interface between the
computer storage and the micro program is the memory data address register, and the
other half is the memory data register.
Index Register
The Index Register is the hardware element that holds the number. The number adds to the
computer instruction's address to create an effective address. In CPU, the index register is a
processor register used to modify the operand address during the running program.
Memory Buffer Register
Memory Buffer Register is mostly called MBR. The MBR contains the Metadata of the data
and instruction written in or read from memory. In simple words, it adds is used to store the
upcoming data/instruction from the memory and going to memory.
Data Register
The data register is used to temporarily store the data. This data transmits to or from a
peripheral device.
Shift Register
A group of flip flops which is used to store multiple bits of data and the data is moved from
one flip flop to another is known as Shift Register. The bits stored in registers shifted when
the clock pulse is applied within and inside or outside the registers. To form an n -bit shift
register, we have to connect n number of flip flops. So, the number of bits of the binary
number is directly proportional to the number of flip flops. The flip flops are connected in
such a way that the first flip flop's output becomes the input of the other flip flop.
A Shift Register can shift the bits either to the left or to the right. A Shift Register, which
shifts the bit to the left, is known as "Shift left register", and it shifts the bit to the right,
known as "Right left register".
The shift register is classified into the following types:

o Serial In Serial Out

o Serial In Parallel Out
o Parallel In Serial Out
o Parallel In Parallel Out
o Bi-directional Shift Register
o Universal Shift Register
Serial IN Serial OUT
In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially. In SISO, a single bit
is shifted at a time in either right or left direction under clock control.
Initially, all the flip-flops are set in "reset" condition i.e. Y 3 = Y2 = Y 1 = Y0 = 0. If we pass the
binary number 1111, the LSB bit of the number is applied first to the Din bit. The D3 input of
the third flip flop, i.e., FF-3, is directly connected to the serial data input D3. The output Y 3 is
passed to the data input d 2 of the next flip flop. This process remains the same for the
remaining flip flops. The block diagram of the "Serial IN Serial OUT" is given below.
Block Diagram:

Operation
When the clock signal application is disabled, the outputs Y 3 Y2 Y1 Y0 = 0000. The LSB bit of
the number is passed to the data input Din, i.e., D3. We will apply the clock, and this time the
value of D3 is 1. The first flip flop, i.e., FF-3, is set, and the word is stored in the register at
the first falling edge of the clock. Now, the stored word is 1000.

The next bit of the binary number, i.e., 1, is passed to the data input D 2. The second flip flop,
i.e., FF-2, is set, and the word is stored when the next negative edge of the clock hits. The
stored word is changed to 1100.

The next bit of the binary number, i.e., 1, is passed to the data input D 1, and the clock is
applied. The third flip flop, i.e., FF-1, is set, and the word is stored when the negative edge
of the clock hits again. The stored word is changed to 1110.

Similarly, the last bit of the binary number, i.e., 1, is passed to the data input D 0, and the
clock is applied. The last flip flop, i.e., FF-0, is set, and the word is stored when the clock's
negative edge arrives. The stored word is changed to 1111.
Truth Table

Serial IN Parallel OUT

In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip flop, and
outputs are fetched in a parallel way. The data is passed bit by bit in the register, and the
output remains disabled until the data is not passed to the data input. When the data is
passed to the register, the outputs are enabled, and the flip flops contain their return value
Below is the block diagram of the 4-bit serial in the parallel-out shift register. The circuit
having four D flip-flops contains a clear and clock signal to reset these four flip flops. In SIPO,
the input of the second flip flop is the output of the first flip flop, and so on. The same clock
signal is applied to each flip flop since the flip flops synchronize each other. The parallel
outputs are used for communication.
Block Diagram

Parallel IN Serial OUT

In the "Parallel IN Serial OUT" register, the data is entered in a parallel way, and the
outcome comes serially. A four-bit "Parallel IN Serial OUT" register is designed below. The
input of the flip flop is the output of the previous Flip Flop. The input and outputs are
connected through the combinational circuit. Through this combinational circuit, the binary
input B0, B 1, B2, B3 are passed. The shift mode and the load mode are the two modes in
which the "PISO" circuit works.
Load mode
The bits B0, B1, B2, and B 3 are passed to the corresponding flip flops when the second,
fourth, and sixth "AND" gates are active. These gates are active when the shift or load bar
line set to 0. The binary inputs B0, B1, B2, and B3 will be loaded into the respective flip-flops
when the edge of the clock is low. Thus, parallel loading occurs.
Shift mode
The second, fourth, and sixth gates are inactive when the load and shift line set to 0. So, we
are not able to load data in a parallel way. At this time, the first, third, and fifth gates will be
activated, and the shifting of the data will be left to the right bit. In this way, the "Parallel IN
Serial OUT" operation occurs.
Block Diagram

Parallel IN Parallel OUT

In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel way in the
register. The inputs A0, A1, A2, and A 3, are directly passed to the data inputs D0, D1, D2, and
D3 of the respective flip flop. The bit of the binary input is loaded to the flip flops when the
negative clock edge is applied. The clock pulse is required for loading all the bits. At the
output side, the loaded bits appear.
Block Diagram

Bidirectional Shift Register

The binary number after shifting each bit of the number to the left by one position will be
equivalent to the number produced by multiplying the original number by 2. In the same
way, the binary number after shifting each bit of the number to the right by one position
will be equivalent to the number produced by dividing the original number by 2.
For performing the multiplication and division operation using the shift register, it is
required that the data should be moved in both the direction, i.e., left or right in the
register. Such registers are called the "Bidirectional" shift register.
Below is the diagram of 4-bit "bidirectional" shift register where DR is the "serial right shift
data input", DL is the "left shift data input", and M is the "mode select input".
Block Diagram

o The first, third, fifth, and seventh AND gates will be enabled, but the second, fourth,
sixth, and eighth AND gates will be disabled.
o The data present on the data input DR is shifted bit by bit from the fourth flip flop to
the first flip flop when the clock pulse is applied. In this way, the shift right operation
occurs.
2) Shift left operation (M=0)
o The second, fourth, sixth and eighth AND gates will be enabled, but the AND gates
first, third, fifth, and seventh will be disabled.
o The data present on the data input DR is shifted bit by bit from the first flip flop to
the fourth flip flop when the clock pulse is applied. In this way, the shift right
operation occurs.
Universal Shift Register
A register where the data is shifted in one direction is known as the "uni-directional" shift
register. A register in which the data is shifted in both the direction is known as "bi-
directional" shift register. A "Universal" shift register is a special type of register that can
load the data in a parallel way and shift that data in both directions, i.e., right and left.
The input M, i.e., the mode control input, is set to 1 to perform the parallel loading
operation. If this input set to 0, then the serial shifting operation is performed. If we connect
the mode control input with the ground, then the circuit will work as a "bi-
directional" register. The diagram of the universal shift register is given below. When the
input is passed to the serial input, the register performs the "serial left" operation. When
the input is passed to the input D, the register performs the serial right operation.
Block Diagram

Counters
A special type of sequential circuit used to count the pulse is known as a counter, or a
collection of flip flops where the clock signal is applied is known as counters.
The counter is one of the widest applications of the flip flop. Based on the clock pulse, the
output of the counter contains a predefined state. The number of the pulse can be counted
using the output of the counter.
Truth Table

There are the following types of counters:

o Asynchronous Counters
o Synchronous Counters
Asynchronous or ripple counters
The Asynchronous counter is also known as the ripple counter. Below is a diagram of the 2-
bit Asynchronous counter in which we used two T flip-flops. Apart from the T flip flop, we
can also use the JK flip flop by setting both of the inputs to 1 permanently. The external
clock pass to the clock input of the first flip flop, i.e., FF-A and its output, i.e., is passed to
clock input of the next flip flop, i.e., FF-B.
Block Diagram
Signal Diagram

Operation
1. Condition 1: When both the flip flops are in reset condition.
Operation: The outputs of both flip flops, i.e., QA QB, will be 0.
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will toggle, and the output of this flip flop will change
from 0 to 1. The output of this flip flop will be taken by the clock input of the next
flip flop. This output will be taken as a positive edge clock by the second flip flop.
This input will not change the second flip flop's output state because it is the
negative edge triggered flip flop.
So, QA = 1 and QB = 0
3. Condition 3: When the second negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 1 to 0. This output will be taken as a negative edge clock by the second
flip flop. This input will change the second flip flops output state because it is the
negative edge triggered flip flop.
So, QA = 0 and QB = 1.
4. Condition 4: When the third negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 0 to 1. This output will be taken as a positive edge clock by the second
flip flop. This input will not change the second flip flop's output state because it is
the negative edge triggered flip flop.
So, QA = 1 and QB = 1
5. Condition 5: When the fourth negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 1 to 0. This output will be taken as a negative edge clock by the second
flip flop. This input will change the output state of the second flip flop.
So, QA = 0 and QB = 0
Synchronous counters
In the Asynchronous counter, the present counter's output passes to the input of the next
counter. So, the counters are connected like a chain. The drawback of this system is that it
creates the counting delay, and the propagation delay also occurs during the counting stage.
The synchronous counter is designed to remove this drawback.
In the synchronous counter, the same clock pulse is passed to the clock input of all the flip
flops. The clock signals produced by all the flip flops are the same as each other. Below is
the diagram of a 2-bit synchronous counter in which the inputs of the first flip flop, i.e., FF-
A, are set to 1. So, the first flip flop will work as a toggle flip-flop. The output of the first flip
flop is passed to both the inputs of the next JK flip flop.
Logical Diagram

ripples through the circuit. The n-MOD ripple counter forms by combining n number of flip-
flops. The n-MOD ripple counter can count 2n states, and then the counter resets to its
initial value.
Features of the Ripple Counter:
o Different types of flip flops with different clock pulse are used.
o It is an example of an asynchronous counter.
o The flip flops are used in toggle mode.
o The external clock pulse is applied to only one flip flop. The output of this flip flop is
treated as a clock pulse for the next flip flop.
o In counting sequence, the flip flop in which external clock pulse is passed, act as LSB.
Based on their circuitry design, the counters are classified into the following types:
Up Counter
The up-counter counts the states in ascending order.
Down Counter
The down counter counts the states in descending order.
Up-Down Counter
The up and down counter is a special type of bi-directional counter which counts the states
either in the forward direction or reverse direction. It also refers to a reversible counter.
Binary Ripple Counter
A Binary counter is a 2-Mod counter which counts up to 2-bit state values, i.e., 22 = 4
values. The flip flops having similar conditions for toggling like T and JK are used to construct
the Ripple counter. Below is a circuit diagram of a binary ripple counter.
In the circuit design of the binary ripple counter, two JK flip flops are used. The high voltage
signal is passed to the inputs of both flip flops. This high voltage input maintains the flip
flops at a state 1. In JK flip flops, the negative triggered clock pulse use.

The outputs Q 0 and Q1 are the LSB and MSB bits, respectively. The truth table of JK flip flop
helps us to understand the functioning of the counter.

When the high voltage to the inputs of the flip flops, the fourth condition is of the JK flip flop
occurs. The flip flops will be at the state 1 when we apply high voltage to the input of the
flip-flop. So, the states of the flip flops passes are toggled at the negative going end of the
clock pulse. In simple words, the flip flop toggle when the clock pulse transition takes place
from 1 to 0.
The state of the output Q0 change when the negative clock edge passes to the flip flop.
Initially, all the flip flops are set to 0. These flip flop changes their states when the passed
clock goes from 1 to 0. The JK flip flop toggles when the inputs of the flip flops are one, and
then the flip flop changes its state from 0 to 1. For all the clock pulse, the process remains
the same.

The output of the first flip flop passes to the second flip flop as a clock pulse. From the
above timing diagram, it is clear that the state of the second flip flop is changed when the
output Q0 goes transition from 1 to 0. The outputs Q0 and Q1 treat as LSB and MSB. The
counter counts the values 00, 01, 10, 11. After counting these values, the counter resets
itself and starts counting again from 00, 01, 10, and 1. The count values until the clock
pulses are passed to J0K0 flip flop.

Ring Counter
A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The
only difference between the shift register and the ring counter is that the last flip flop
outcome is taken as the output in the shift register. But in the ring counter, this outcome is
passed to the first flip flop as an input. All of the remaining things in the ring counter are the
same as the shift register.
In the Ring counter
No. of states in Ring counter = No. of flip-flop used
Below is the block diagram of the 4-bit ring counter. Here, we use 4 D flip flops. The same
clock pulse is passed to the clock input of all the flip flops as a synchronous counter.
The Overriding input(ORI) is used to design this circuit.
The Overriding input is used as clear and pre-set.
 The output is 1 when the pre-set set to 0. The output is 0 when the clear set to 0. Both PR
and CLR always work in value 0 because they are active low signals.
1. PR = 0, Q = 1
2. CLR = 0, Q = 0
These two values(always fixed) are independent with the input D and the Clock pulse (CLK).
Working
The ORI input is passed to the PR input of the first flip flop, i.e., FF-0, and it is also passed to
the clear input of the remaining three flip flops, i.e., FF-1, FF-2, and FF-3. The pre-set input
set to 0 for the first flip flop. So, the output of the first flip flop is one, and the outputs of the
remaining flip flops are 0. The output of the first flip flop is used to form the ring in the ring
counter and referred to as Pre-set 1.

In the above table, the highlighted 1's are pre-set 1.

The Pre-set 1 is generated when
o ORI input set to low, and that time the Clk doesn't care.
o
o When the ORI input set to high, and the low clock pulse signal is passed as the
negative clock edge triggered.
A ring forms when the pre-set 1 is shifted to the next flip-flop at each clock pulse.
So, 4-bit counter, 4 states are possible which are as follows:
1. 1000
2. 0100
3. 0010
4. 0001
Types of Ring Counter
The ring counter is classified into two parts which are as follows:
Straight Ring Counter
The Straight Ring Counter refers to as One hot Counter. The outcome of the last flip-flop is
passed to the first flip-flop as an input. In the ring counter, the ORI input is passed to the PR
input for the first flip flop and to the clear input of the remaining flip flops.
Note: The straight ring counter circulates the single 1 (or 0) bit around the ring.
Logic Diagram

Truth Table

Signal Diagram

Twisted Ring Counter

The Twisted Ring Counter refers to as a switch-tail ring Counter. Like the straight ring
counter, the outcome of the last flip-flop is passed to the first flip-flop as an input. In the
twisted ring counter, the ORI input is passed to all the flip flops as clear input.
Note: The twisted ring counter circulates a stream of 1's followed by 0 around the ring.
Logic Diagram

Truth Table

Signal Diagram
Signal Diagram

Operation
1. Condition 1: When both the flip flops are in reset condition.
Operation: The outputs of both flip flops, i.e., Q A QB, will be 0.
So, QA = 0 and QB = 0
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will be toggled, and the output of this flip flop will be
changed from 0 to 1. When the first negative clock edge is passed, the output of the
first flip flop will be 0. The clock input of the first flip flop and both of its inputs will
set to 0. In this way, the state of the second flip flop will remain the same.
So, QA = 1 and QB = 0
3. Condition 2: When the second negative clock edge is passed.
Operation: The first flip flop will be toggled again, and the output of this flip flop will
be changed from 1 to 0. When the second negative clock edge is passed, the output
of the first flip flop will be 1. The clock input of the first flip flop and both of its inputs
will set to 1. In this way, the state of the second flip flop will change from 0 to 1.
So, QA = 0 and QB = 1
4. Condition 2: When the third negative clock edge passes.
Operation: The first flip flop will toggle from 0 to 1, but at this instance, both the
inputs and the clock input set to 0. Hence, the outputs will remain the same as
before.
So, QA = 1 and QB = 1
5. Condition 2: When the fourth negative clock edge passes.
Operation: The first flip flop will toggle from 1 to 0. At this instance, the inputs and
the clock input of the second flip flop set to 1. Hence, the outputs will change from 1
to 0.
So, QA = 0 and QB = 0
 Johnson Counter
The Johnson counter is similar to the Ring counter. The only difference between
the Johnson counter and the ring counter is that the outcome of the last flip flop is passed
to the first flip flop as an input. But in Johnson counter, the inverted outcome Q' of the last
flip flop is passed as an input. The remaining work of the Johnson counter is the same as
a ring counter. The Johnson counter is also referred to as the Creeping counter.
In Johnson counter
1. No. of states in Johnson counter = No. of flip-flop used
2. Number of used states=2n
3. Number of unused states=2n - 2*n
Below is the diagram of the 4-bit Johnson counter. Like Ring counter, four D flip flops are
used in the 4-bit Johnson counter, and the same clock pulse is passed to all the input of the
flip flops.

Truth Table

CP Q1 Q2 Q3 Q4

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 1 1 1
The above table state that
o The counter produces the output 0000 when there is no clock input passed(0).
o The counter produces the output 1000 when the 1 st clock pulse is passed to the flip
flops.
 o The counter produces the output 1100 when the 2 nd clock pulse is passed to the flip
flops.
o The counter produces the output 1110 when the 3 rd clock pulse is passed to the flip
flops.
o The counter produces the output 1111 when the 4 th clock pulse is passed to the flip
flops.
o The counter produces the output 0111 when the 5 th clock pulse is passed to the flip
flops.
o The counter produces the output 0011 when the 6 th clock pulse is passed to the flip
flops.
o The counter produces the output 0001 when the 7th clock pulse is passed to the flip
flops.
Timing diagram

Advantages
o The number of flip flops in the Johnson counter is equal to the number of flip flops in
the ring counter, and the Johnson counter counts twice the number of states the
ring counter can count.
o The Johnson counter can also be designed by using D or JK flip flop.
o The data is count in a continuous loop in the Johnson ring counter.
o The circuit of the Johnson counter is self-decoding.
Disadvantages
o The Johnson counter is not able to count the states in a binary sequence.
o In the Johnson counter, the unutilized states are greater than the states being
utilized.
o The number of flip flops is equal to one half of the number of timing signals.
o It is possible to design the Johnson counter for any number of timing sequences.